JP4947345B2 - Method of joining substrate and device using Au-Sn alloy solder paste - Google Patents

Method of joining substrate and device using Au-Sn alloy solder paste Download PDF

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JP4947345B2
JP4947345B2 JP2006191349A JP2006191349A JP4947345B2 JP 4947345 B2 JP4947345 B2 JP 4947345B2 JP 2006191349 A JP2006191349 A JP 2006191349A JP 2006191349 A JP2006191349 A JP 2006191349A JP 4947345 B2 JP4947345 B2 JP 4947345B2
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alloy solder
substrate
flux
solder paste
alloy
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JP2007173768A (en
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石川　　雅之
正好 小日向
昭史 三島
怜子 小川
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Mitsubishi Materials Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
    • H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step

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  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of using, particularly, an Au-Sn alloy solder paste to bond an element, for example an LED device, to a substrate. <P>SOLUTION: In the method of bonding the substrate 1 and element 3, the Au-Sn alloy solder paste 2 is mounted on or coated onto the substrate, and thereafter it is reflow-processed in a non-acidification atmosphere. The flux residue of the reflow-processed Au-Sn alloy solder paste is removed by cleaning to form a solidified Au-Sn alloy solder layer on the substrate surface. A non-halogen flux is coated or a small amount of non-halogen flux is coated to account for 1 to 15 percent of bottom area of the element. After the element is mounted on the non-halogen flux, the element is bonded to the substrate by the reflow processing in the non-acidification atmosphere. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

この発明は、Ａｕ−Ｓｎ合金はんだペーストを用いて多くの素子を基板に接合する方法に関するものであり、特にＡｕ−Ｓｎ合金はんだペーストを用いて熱影響を受けて劣化し易いＬＥＤ（発光ダイオード）素子など一度に大量に基板に接合する方法に関するものである。   The present invention relates to a method of bonding many elements to a substrate using an Au—Sn alloy solder paste, and particularly, an LED (light emitting diode) that is susceptible to deterioration due to thermal effects using an Au—Sn alloy solder paste. The present invention relates to a method for bonding a large amount of elements to a substrate at one time.

一般に、ＬＥＤ（発光ダイオード）素子、ＧａＡｓ光素子、ＧａＡｓ高周波素子、熱伝素子などの半導体素子と基板との接合、微細かつ高気密性が要求されるＳＡＷフィルター、水晶発振子などのパッケージ封止などには、Ａｇペースト、Ａｕ−Ｓｎ箔材、Ａｕバンプ、Ａｕ−Ｓｎ合金はんだペーストなどが使用されていた。   In general, bonding of semiconductor elements such as LED (light emitting diode) elements, GaAs optical elements, GaAs high frequency elements, and heat transfer elements and substrates, SAW filters that require fine and high airtightness, sealing of packages such as crystal oscillators, etc. For example, Ag paste, Au—Sn foil material, Au bump, Au—Sn alloy solder paste and the like have been used.

Ａｇペーストは、Ａｇ材料自身の熱伝導性が悪いだけでなく、基板と素子の間に発生するボイドが多かった。つまり、接合領域がボイドにより減少してしまい、熱抵抗を低下させると共に、接合部の信頼性にも問題があった。そのために、特に熱がこもると破損もしくは急激に特性が低下するようなＬＥＤ（発光ダイオード）素子は基板との接合部の熱伝導性が非常に重要であるところから、ＬＥＤ（発光ダイオード）素子と基板との接合には熱伝導性が良くかつ信頼性が高い接合部を形成するＡｕ−Ｓｎ合金はんだ箔材(リボンなど)、Ａｕバンプ、Ａｕ−Ｓｎ合金はんだペーストが用いられている。   The Ag paste not only has a poor thermal conductivity of the Ag material itself, but also has many voids generated between the substrate and the element. That is, the bonding area is reduced by voids, which reduces the thermal resistance and also has a problem with the reliability of the bonded portion. For this reason, LED (light-emitting diode) elements whose characteristics are damaged or suddenly deteriorate when heat is trapped are particularly important for the thermal conductivity of the junction with the substrate. For bonding to the substrate, Au—Sn alloy solder foil material (ribbon or the like), Au bump, or Au—Sn alloy solder paste that forms a highly reliable and highly reliable bonded portion is used.

しかし、Ａｕ−Ｓｎはんだ合金箔材(リボンなど)は、材料自身の熱伝導性は高いが接合時の濡れ性が悪いため接合領域を十分に広く取ることができず、また箔材表面には酸化膜が多いため溶融したＡｕ−Ｓｎはんだ合金の流動性が悪い。そのため加熱溶融しながら荷重をかけて接合する工法もあるが、加熱時間が長くまた長時間荷重をかけて接合しなければならないことから、熱を長時間かけることが好ましくないＬＥＤ（発光ダイオード）素子に適用することができない。さらに、Ａｕ−Ｓｎはんだ合金箔材の場合、濡れ性が悪いことにより接合面積が小さいという欠点があった。   However, Au-Sn solder alloy foil materials (ribbons, etc.) have high thermal conductivity, but the wettability during bonding is poor, so that the bonding area cannot be made sufficiently wide. Since there are many oxide films, the fluidity of the molten Au—Sn solder alloy is poor. For this reason, there is a method of joining by applying a load while heating and melting, but an LED (light emitting diode) element in which it is not preferable to apply heat for a long time because the heating time is long and it is necessary to apply a load for a long time. Cannot be applied to. Furthermore, in the case of the Au—Sn solder alloy foil material, there is a drawback that the bonding area is small due to poor wettability.

また、Ａｕバンプ法による素子の接合は、素子全体にＡｕ−Ｓｎはんだ合金接合層が接合していないため、Ａｕ−Ｓｎはんだ合金接合層と接合していない部分の熱伝導が悪く、また、このＡｕバンプ法では３００℃以上の温度で荷重をかけながら接合を行なうが、３００℃以上高温を長時間保持する必要があり、熱影響を受けて劣化しやすいＬＥＤ（発光ダイオード）素子に適用することができなかった。
そのため、近年、熱影響を受けて劣化しやすいＬＥＤ（発光ダイオード）素子の接合には接合信頼性の一層優れたＡｕ−Ｓｎ合金はんだペーストが多く用いられるようになってきた。このＡｕ−Ｓｎ合金はんだペーストは、Ｓｎ：１５〜２５質量％（好ましくはＳｎ：２０質量％）を含有し、残りがＡｕおよび不可避不純物からなる組成を有するＡｕ−Ｓｎ共晶合金ガスアトマイズ粉末とロジン、活性剤、溶剤および増粘剤からなる市販のフラックスとを混合して作られる。
このＡｕ−Ｓｎ合金はんだペーストを使用して素子と基板を接合すると接合部がＡｕ−Ｓｎはんだ合金であるので熱伝導性が良く接合信頼性も高いこと、ペーストであるので複数の接合部に一括供給でき、さらに一括熱処理できること、リフロー時にフラックスがＡｕ−Ｓｎはんだ合金表面を覆っているために酸化膜が少なく、そのため、接合時の溶融Ａｕ−Ｓｎはんだ合金の流動性が大きく、濡れが良くなって接合面積を拡大することができるところから素子全面を接合すること、さらに接合時に過剰な荷重をかける必要がないこと,などのメリットがある。このＡｕ−Ｓｎ合金はんだペーストを用いて基板と素子を接合するには、まず、図２（ａ）に示されるように、基板１にＡｕ−Ｓｎ合金はんだペースト２を搭載または塗布する。次に、このＡｕ−Ｓｎ合金はんだペースト２の上に図２（ｂ）に示されるように素子３を搭載し、この状態で加熱してリフロー処理を施したのち冷却すると、図２（ｃ）に示されるように、Ａｕ−Ｓｎ合金はんだ接合層４０を介してと基板１と素子３が接合し、Ａｕ−Ｓｎ合金はんだ接合層４０の周囲にフラックス残渣層５が形成される。この形成されたフラックス残渣層５は洗浄し除去して、図２（ｄ）に示されるように、接合が完了する（特許文献１または２など参照）。
特開２００３−１０５４６２ 特開２００３−２６０５８８ In addition, since the Au-Sn solder alloy bonding layer is not bonded to the entire element in the bonding of the elements by the Au bump method, the heat conduction of the portion not bonded to the Au-Sn solder alloy bonding layer is poor. In the Au bump method, bonding is performed while applying a load at a temperature of 300 ° C. or higher. However, it is necessary to maintain a high temperature of 300 ° C. or higher for a long time, and it is applied to an LED (light emitting diode) element that is easily deteriorated due to thermal influence. I could not.
For this reason, in recent years, Au-Sn alloy solder pastes with higher bonding reliability have been frequently used for bonding LED (light-emitting diode) elements that are easily deteriorated under the influence of heat. This Au—Sn alloy solder paste contains Sn: 15 to 25% by mass (preferably Sn: 20% by mass), and the remainder is composed of Au and inevitable impurities. Au—Sn eutectic alloy gas atomized powder and rosin It is made by mixing a commercially available flux consisting of an activator, a solvent and a thickener.
When an element and a substrate are bonded using this Au—Sn alloy solder paste, the bonding portion is an Au—Sn solder alloy, so that the thermal conductivity is good and the bonding reliability is high. It can be supplied and heat treated together, and the flux covers the surface of the Au-Sn solder alloy during reflow, so there is little oxide film. Thus, there are merits such as bonding the entire surface of the element from the point that the bonding area can be expanded, and that it is not necessary to apply an excessive load at the time of bonding. In order to join the substrate and the element using this Au—Sn alloy solder paste, first, as shown in FIG. 2A, the Au—Sn alloy solder paste 2 is mounted or applied to the substrate 1. Next, the element 3 is mounted on the Au—Sn alloy solder paste 2 as shown in FIG. 2B, heated in this state, subjected to reflow treatment, and then cooled. As shown in FIG. 5, the substrate 1 and the element 3 are bonded together through the Au—Sn alloy solder bonding layer 40, and the flux residue layer 5 is formed around the Au—Sn alloy solder bonding layer 40. The formed flux residue layer 5 is washed and removed, and the joining is completed as shown in FIG. 2D (see Patent Document 1 or 2).
JP 2003-105462 A JP 2003-260588 A

（イ）前記Ａｕ−Ｓｎ合金はんだペースト２の上に図２（ｂ）に示されるように素子３を搭載し、この状態で加熱してリフロー処理を施すことにより、図２（ｃ）に示されるように、Ａｕ−Ｓｎ合金はんだ接合層４０を介してと基板１と素子３を接合させるためには高温で長時間加熱のリフロー処理を施さなければならず、高温で長時間の加熱に弱いＬＥＤ素子などの素子にはこの接合方法は好ましくない。さらに図２（ｂ）に示されるようにＡｕ−Ｓｎ合金はんだペースト２の上に素子３を搭載し、この状態で加熱してリフロー処理を施すと、Ａｕ−Ｓｎ合金はんだペースト２の上に素子３が被さっているために、Ａｕ−Ｓｎ合金はんだペースト２が溶融するに際してペーストから発生したガスが逃げ場を失ってボイドが発生しやすく、ボイドが発生すると素子３と基板１との接合面積が少なくなり、接合面積が少なくなると素子３に発生した熱の放熱性が悪くなるなどの欠点があった。
（ロ）また、ペーストの特徴を生かし、大きな一枚の基板にディスペンスや印刷によりＡｕＳｎ合金はんだペーストを一度に供給し、リフロー処理することで一度に数千個の点状のＡｕＳｎ合金を形成することができるが、その点状のＡｕＳｎ合金の上に一度に数千個の素子を搭載し、これを加熱炉に装入してリフロー処理を施すと、加熱炉までの移動に際して素子が落下することがあり、その部分が不良品となって歩留を低下させることが予想される。 (A) The element 3 is mounted on the Au—Sn alloy solder paste 2 as shown in FIG. 2B, and heated in this state to perform a reflow process, as shown in FIG. 2C. As described above, in order to join the substrate 1 and the element 3 through the Au—Sn alloy solder joint layer 40, a reflow process of heating at a high temperature for a long time must be performed, which is vulnerable to a long time heating at a high temperature. This joining method is not preferable for elements such as LED elements. Further, as shown in FIG. 2B, when the element 3 is mounted on the Au—Sn alloy solder paste 2 and heated in this state to perform reflow treatment, the element is placed on the Au—Sn alloy solder paste 2. 3, when the Au—Sn alloy solder paste 2 is melted, the gas generated from the paste loses the escape field and is likely to generate voids. When the voids are generated, the bonding area between the element 3 and the substrate 1 is small. Therefore, when the bonding area is reduced, there is a disadvantage that heat dissipation of the heat generated in the element 3 is deteriorated.
(B) Taking advantage of the characteristics of the paste, AuSn alloy solder paste is supplied to a large single substrate by dispensing or printing at a time, and reflow treatment is performed to form several thousand pointed AuSn alloys at a time. However, when thousands of elements are mounted on the pointed AuSn alloy at a time and charged into a heating furnace and subjected to a reflow process, the elements drop when moving to the heating furnace. In some cases, it is expected that the product will be defective and the yield will be reduced.

この発明は、前記（イ）および（ロ）の問題点を同時に解決することを目的とするものである。   The object of the present invention is to solve the problems (a) and (b) at the same time.

本発明者らは、前記課題を解決すべく研究を行った。その結果、
（ａ）Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのちリフロー処理し、リフロー処理したＡｕ−Ｓｎ合金はんだペーストのフラックス残渣部分を洗浄により除去して基板表面に凝固Ａｕ−Ｓｎ合金はんだ層を形成し、この凝固Ａｕ−Ｓｎ合金はんだ層の上に素子を載せてリフロー処理すると、素子を基板の上に形成されたＡｕ−Ｓｎ合金はんだ層の上に直接搭載してはんだ付けすることから、従来よりも短時間の加熱処理で素子を基板に接合することができるために特に熱に弱いＬＥＤ素子の接合に有効である、
（ｂ）この場合、凝固したＡｕ−Ｓｎ合金はんだ層上に素子を載せてあるので滑り易く、移動時などに少しの振動を与えても素子が落下することがあり、これを防止するためにこの凝固したＡｕ−Ｓｎ合金はんだ層の上に一般にフラックス残渣の洗浄を行う必要がないといわれているノンハロゲンフラックスを塗布し、このフラックス残渣の洗浄を行う必要がないノンハロゲンフラックスの上に素子を搭載すると、ノンハロゲンフラックスは粘着性を有するところから素子の取り付きもよくなって、移動時などに少しの振動を与えても素子が落下することが無く、また、凝固したＡｕ−Ｓｎ合金はんだ層の上に塗布したノンハロゲンフラックスは、素子の接合終了後にフラックス残渣を洗浄する必要がないこと、
（ｃ）前記ノンハロゲンフラックスは、凝固したＡｕ−Ｓｎ合金はんだ層の上に素子の底面積の１〜１５％の面積となるように少量塗布しても、移動時などに少しの振動を与えても素子が落下することが無く、ノンハロゲンフラックスはその塗布量が極めて少ないことからボイドの発生は極めて少なく、また素子の接合終了後にフラックス残渣を洗浄する必要がないので一層好ましいこと、などの知見を得られたのである。 The present inventors have conducted researches to solve the above problems. as a result,
(A) The Au—Sn alloy solder paste is mounted on or applied to the substrate and then reflowed, and the flux residue of the reflowed Au—Sn alloy solder paste is removed by washing to solidify the Au—Sn alloy solder layer on the substrate surface. When the element is placed on this solidified Au—Sn alloy solder layer and reflowed, the element is directly mounted on the Au—Sn alloy solder layer formed on the substrate and soldered. In addition, since the element can be bonded to the substrate by heat treatment in a shorter time than conventional, it is particularly effective for bonding an LED element that is weak against heat.
(B) In this case, since the element is placed on the solidified Au—Sn alloy solder layer, it is easy to slip, and the element may fall even if a slight vibration is given during movement, etc. On the solidified Au-Sn alloy solder layer, a non-halogen flux, which is generally said to be unnecessary to clean the flux residue, is applied, and the device is mounted on the non-halogen flux which does not need to be cleaned. Then, since the non-halogen flux has adhesiveness, the element can be easily attached, and even if a slight vibration is applied during movement, the element does not fall, and on the solidified Au—Sn alloy solder layer. The non-halogen flux applied to the substrate does not need to be cleaned of flux residue after the bonding of the elements.
(C) Even if a small amount of the non-halogen flux is applied on the solidified Au—Sn alloy solder layer so as to have an area of 1 to 15% of the bottom area of the device, it gives a slight vibration during movement. However, the non-halogen flux has a very small amount of coating, so there is very little voiding, and there is no need to clean the flux residue after the joining of the element. It was obtained.

この発明は、かかる知見に基づいて成されたものであって、
（１）Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち非酸化性雰囲気中でリフロー処理し、リフロー処理したＡｕ−Ｓｎ合金はんだペーストのフラックス残渣部分を洗浄し除去して基板表面に凝固Ａｕ−Ｓｎ合金はんだ層を形成し、基板表面の凝固Ａｕ−Ｓｎ合金はんだ層の表面にノンハロゲンフラックスを塗布し、このノンハロゲンフラックスの上に素子を搭載したのちリフロー処理して素子を基板に接合するＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法であって、前記ノンハロゲンフラックスが、水酸基を４〜６個有する糖類を含む還元性固体活性剤を５〜６０質量％、イソボルニル基を有する化合物を含む高粘性溶剤を１０〜６０質量％、および低粘性溶剤を２０〜７０質量％を含有するフラックスであること、
（２）Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち非酸化性雰囲気中でリフロー処理し、リフロー処理したＡｕ−Ｓｎ合金はんだペーストのフラックス残渣部分を洗浄し除去して基板表面に凝固Ａｕ−Ｓｎ合金はんだ層を形成し、基板表面の凝固Ａｕ−Ｓｎ合金はんだ層の表面に素子の底面積の１〜１５％の面積となるように少量のノンハロゲンフラックスを塗布し、このノンハロゲンフラックスの上に素子を搭載したのちリフロー処理して素子を基板に接合するＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法、
に特徴を有するものである。
This invention is made based on such knowledge,
(1) The Au—Sn alloy solder paste is mounted on or applied to the substrate and then reflowed in a non-oxidizing atmosphere, and the flux residue portion of the reflowed Au—Sn alloy solder paste is washed and removed to solidify on the substrate surface. An Au—Sn alloy solder layer is formed, a non-halogen flux is applied to the surface of the solidified Au—Sn alloy solder layer on the substrate surface, an element is mounted on the non-halogen flux , and then the reflow process is performed to bond the element to the substrate. A method of joining a substrate and an element using an Au—Sn alloy solder paste, wherein the non-halogen flux has 5 to 60% by mass of a reducing solid activator containing a saccharide having 4 to 6 hydroxyl groups and an isobornyl group. Flux containing 10 to 60% by mass of high viscosity solvent containing compound and 20 to 70% by mass of low viscosity solvent That there is,
(2) After the Au—Sn alloy solder paste is mounted or applied to the substrate, it is reflowed in a non-oxidizing atmosphere, and the flux residue of the reflowed Au—Sn alloy solder paste is washed and removed to solidify on the substrate surface. forming a Au-Sn alloy solder layer, a small amount of halogen-free flux is applied so that 1 to 15% of the area of the bottom area of the element on the surface of the coagulation Au-Sn alloy solder layer of the substrate surface, of the non-halogen flux A method of bonding a substrate and an element using an Au-Sn alloy solder paste, in which the element is mounted on the substrate and then reflowed to bond the element to the substrate;
It has the characteristics.

この発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を図面に基づいて具体的に説明する。図１はこの発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を説明するための斜視説明図である。   A method for joining a substrate and an element using the Au—Sn alloy solder paste of the present invention will be specifically described with reference to the drawings. FIG. 1 is a perspective view for explaining a method of joining a substrate and an element using the Au—Sn alloy solder paste of the present invention.

図１（ａ）に示されるように、基板１にＡｕ−Ｓｎ合金はんだペースト２を搭載または塗布し、この状態でリフロー処理を施したのち冷却すると、図１（ｂ）に示されるように、Ａｕ−Ｓｎ合金はんだペースト２が溶融して凝固Ａｕ−Ｓｎ合金はんだ層４とその周囲にフラックス残渣層５が形成され、その後、フラックス残渣層５を洗浄して、図１（ｃ）に示されるように、基板１の上に凝固Ａｕ−Ｓｎ合金はんだ層４を形成する。この凝固Ａｕ−Ｓｎ合金はんだ層４の上に、図１（ｄ）に示されるように、ノンハロゲンフラックス５１を薄く塗布する。ノンハロゲンフラックス５１の塗布量は特に限定されるものではないが、その塗布面積は素子の底面積の１〜１５％の範囲内の面積となるように塗布することが一層好ましい。図１（ｄ）は、素子の底面積の１〜１５％の範囲内の面積となるようにノンハロゲンフラックス５１を少量塗布した状態を示している。   As shown in FIG. 1 (a), when an Au—Sn alloy solder paste 2 is mounted or applied to the substrate 1, and after reflow treatment in this state, cooling is performed, as shown in FIG. 1 (b), The Au—Sn alloy solder paste 2 is melted to form a solidified Au—Sn alloy solder layer 4 and a flux residue layer 5 therearound, and then the flux residue layer 5 is washed, as shown in FIG. Thus, the solidified Au—Sn alloy solder layer 4 is formed on the substrate 1. On the solidified Au—Sn alloy solder layer 4, a non-halogen flux 51 is thinly applied as shown in FIG. The coating amount of the non-halogen flux 51 is not particularly limited, but it is more preferable that the non-halogen flux 51 is coated so that the coating area is in the range of 1 to 15% of the bottom area of the element. FIG. 1D shows a state in which a small amount of non-halogen flux 51 is applied so as to have an area within the range of 1 to 15% of the bottom area of the element.

素子の底面積の１〜１５％の面積となるように限定して塗布することが一層好ましい理由は、素子の底面積の１％未満の塗布では少なすぎて素子を十分に固定することができず、一方、素子の底面積の１５％を越える面積で塗布するとボイドの発生がやや多くなり、ノンハロゲンフラックスであっても多すぎてリフロー処理後の洗浄が必要となることもあるので１５％以下の面積となるように塗布することが一層好ましいからである。   The reason why it is more preferable to apply the coating so as to be 1 to 15% of the bottom area of the element is that the application of less than 1% of the bottom area of the element is too small and the element can be sufficiently fixed. On the other hand, when it is applied in an area exceeding 15% of the bottom area of the element, the generation of voids is slightly increased, and even a non-halogen flux is too much and may require cleaning after reflow treatment, so it is 15% or less. It is because it is still more preferable to apply | coat so that it may become this area.

凝固Ａｕ−Ｓｎ合金はんだ層４の上に塗布したノンハロゲンフラックスの上に、図１（ｅ）に示されるように、素子３を搭載すると、フラックスは粘着性を有するところからノンハロゲンフラックスによって素子３が固定され、軽い振動が与えられても素子３が落下することはない。この状態で短時間リフロー処理すると、図１（ｆ）に示されるように、素子３を基板１にＡｕ−Ｓｎ合金はんだ接合層４０を介して接合し終了する。
When the element 3 is mounted on the non-halogen flux applied on the solidified Au—Sn alloy solder layer 4 as shown in FIG. 1 (e), the element 3 is caused to adhere to the non-halogen flux because the flux has adhesiveness. The element 3 does not fall even if it is fixed and given a light vibration. When the reflow process is performed for a short time in this state, the element 3 is bonded to the substrate 1 via the Au—Sn alloy solder bonding layer 40 as shown in FIG.


次に、この発明で使用するノンハロゲンフラックスについて説明する。ノンハロゲンフラックスは千住金属株式会社製のデルタラックス５２７Ｎとして市販されているものがあり、これを用いても良い。しかし、ほとんどフラックス残渣の残らない低残渣ノンハロゲンフラックスを用いることが一層好ましい。この低残渣ノンハロゲンフラックスは、水酸基を４〜６個有する糖類を含む還元性固体活性剤を全体量１００質量％に対して５〜６０質量％、イソボルニル基を有する化合物を含む高粘性溶剤を全体量１００質量％に対して１０〜６０質量％、および低粘性溶剤を全体量１００質量％に対して２０〜７０質量％を含有するフラックスである。

この低残渣ノンハロゲンフラックスに含まれる前記水酸基を４〜６個有する糖類は、エリトリトール、フルクトース、ガラクトース、グルコース、マンノース、ソルビトール、ラクトース、スクロース、キシリトール、ヘキシトール、マルチトール、ラクチトール、リビトールおよびマンニトールからなる群より選ばれた１種の化合物または２種以上の化合物であり、

前記イソボルニル基を有する化合物は、イソボルニルシクロヘキサノールまたはイソボルニルフェノールのいずれか一方またはその双方であり、
前記低粘性溶剤は、アルカンジオール、アルキレングリコール、炭化水素、テルペンおよびエーテルからなる軍より選ばれた種または２種以上であり、これらの中でも、２−エチル−１，３−ヘキサンジオール、１，５−ペンタンジオール、１，４−ブタンジオール、トリエチレングリコール、テトラエチレングリコール、テトラデカン、ａ−テルピネオール、ジベンジルエーテル、ｐ−ドデシルフェノール、２−ノニルフェノールおよび２−フェノキシエタノールからなる群より選ばれた１種または２種以上である。
以上述べたフラックスに、さらに脂肪酸アミドなどのチキソ剤を全体量１００％に対して２５％以下含有しても良い。
Next, the non-halogen flux used in the present invention will be described. Non-halogen flux is commercially available as Deltalux 527N manufactured by Senju Metal Co., Ltd., and this may be used. However, it is more preferable to use a low-residue non-halogen flux that hardly leaves a flux residue. This low-residue non-halogen flux consists of 5 to 60% by mass of a reducing solid activator containing saccharides having 4 to 6 hydroxyl groups and 100% by mass of the total amount of high viscosity solvent containing a compound having an isobornyl group. The flux contains 10 to 60% by mass with respect to 100% by mass, and 20 to 70% by mass with respect to 100% by mass of the low viscosity solvent.

The saccharide having 4 to 6 hydroxyl groups contained in the low-residue non-halogen flux is a group consisting of erythritol, fructose, galactose, glucose, mannose, sorbitol, lactose, sucrose, xylitol, hexitol, maltitol, lactitol, ribitol and mannitol One compound or two or more compounds selected from

The compound having an isobornyl group is either or both of isobornylcyclohexanol and isobornylphenol,
The low-viscosity solvent is a species selected from the army consisting of alkanediol, alkylene glycol, hydrocarbon, terpene and ether, or two or more thereof. Among these, 2-ethyl-1,3-hexanediol, 1, 1 selected from the group consisting of 5-pentanediol, 1,4-butanediol, triethylene glycol, tetraethylene glycol, tetradecane, a-terpineol, dibenzyl ether, p-dodecylphenol, 2-nonylphenol and 2-phenoxyethanol. Species or two or more.
The flux described above may further contain 25% or less of a thixotropic agent such as fatty acid amide with respect to 100% of the total amount.

この発明のＡｕ−Ｓｎ合金はんだペーストを用いた接合方法によると、素子３を基板１に粘着接合することができ、さらに基板１と素子３を接合するに必要な加熱時間（リフロー処理時間）を短くすることができるので高温長時間の加熱に弱いＬＥＤ素子などの素子の接合に適しており、さらに接合終了後にフラックス残渣を洗浄する必要がないなど産業上優れた効果をもたらすものである。   According to the bonding method using the Au—Sn alloy solder paste of the present invention, the element 3 can be adhesively bonded to the substrate 1, and the heating time (reflow treatment time) required for bonding the substrate 1 and the element 3 is reduced. Since it can be shortened, it is suitable for bonding elements such as LED elements that are vulnerable to high-temperature and long-time heating. Further, it is not necessary to clean the flux residue after the bonding is completed, and thus has excellent industrial effects.

Ｓｎ：２０質量％を含有し、残部がＡｕからなる成分組成を有し平均粒径：１０μｍを有するＡｕ−Ｓｎ合金はんだ粉末を用意し、このＡｕ−Ｓｎ合金はんだ粉末を市販のロジン系ワックスに、ロジン系ワックス：７質量％を含有し、残部がＡｕ−Ｓｎ合金はんだ粉末の配合組成となるように配合し、混合してＡｕ−Ｓｎ合金はんだペーストを作製した。
さらに、ＬＥＤ素子、メタライズ処理したアルミナ製基板および市販のノンハロゲンフラックス（千住金属製のデルタラックス５２７Ｎ）を用意した。

さらに、エリトリトール：２５質量％、イソボルニルシクロヘキサノール：イソボルニルフェノール＝８：２の割合で混合して調整された混合剤：３５質量％、テトラエチレングリコール：４０質量％からなる低残渣ノンハロゲンフラックス（以下、自社製のノンハロゲンフラックス１という）を用意した。

さらに、キシリトリトール：２０質量％、イソボルニルシクロヘキサノール：イソボルニルフェノール＝８：２の割合で混合して調整された混合剤：２０質量％、２−エチル−１，３−ヘキサンジオール：５０質量％、ステアリン酸アミド：１０質量％からなる低残渣ノンハロゲンフラックス（以下、ノンハロゲンフラックス２という）を用意した。
An Au—Sn alloy solder powder containing Sn: 20% by mass with the balance being composed of Au and having an average particle size of 10 μm is prepared, and this Au—Sn alloy solder powder is used as a commercially available rosin wax. And rosin-based wax: 7% by mass, and the remainder was blended so as to have a blended composition of Au—Sn alloy solder powder, and mixed to prepare an Au—Sn alloy solder paste.
Furthermore, an LED element, a metallized alumina substrate, and a commercially available non-halogen flux (Delta Lux 527N made by Senju Metal) were prepared.

Furthermore, a low residual non-halogen composition comprising erythritol: 25% by mass, admixture prepared by mixing at a ratio of isobornylcyclohexanol: isobornylphenol = 8: 2: 35% by mass, tetraethylene glycol: 40% by mass A flux (hereinafter referred to as “non-halogen flux 1”) was prepared.

Further, xylitolitol: 20% by mass, isobornylcyclohexanol: isobornylphenol = mixing agent prepared by mixing at a ratio of 8: 2: 20% by mass, 2-ethyl-1,3-hexanediol A low-residue non-halogen flux (hereinafter referred to as non-halogen flux 2) comprising 50% by mass and stearamide: 10% by mass was prepared.

実施例１
先に用意したアルミナ製基板の上に先に用意したＡｕ−Ｓｎ合金はんだペーストをピン転写法により塗布し、これを窒素雰囲気中の熱対流型炉に装入して２００℃に６０秒保持したのち、さらに３１０℃に３０秒間保持することによりリフロー処理を施し冷却したところ、中央に凝固Ａｕ−Ｓｎ合金はんだ層を有しその周囲にフラックス残渣が残ったＡｕ−Ｓｎ合金はんだペースト溶融部分が形成された。このＡｕ−Ｓｎ合金はんだペースト溶融部分のフラックス残渣を通常の洗浄液で洗浄し除去して凝固Ａｕ−Ｓｎ合金はんだ層を残したのち、凝固Ａｕ−Ｓｎ合金はんだ層の上に市販のノンハロゲンフラックス（千住金属製のデルタラックス５２７Ｎ）を径：３００μｍの転写ピンを用いたピン転写法により素子の底面積の８％の面積を有する少量のノンハロゲンフラックス層を形成し、このノンハロゲンフラックス層の上にＬＥＤ素子を乗せ、この状態でアルミナ製基板に振動を与えながら窒素雰囲気中の熱対流型炉に装入したがＬＥＤ素子がアルミナ製基板から落下することはなかった。ＬＥＤ素子をアルミナ製基板の上に乗せた状態で窒素雰囲気中の熱対流型炉に装入し、３１８℃に１０秒間加熱してリフロー処理を施すことにより基板表面にＬＥＤ素子を接合することができた。
接合部分を調べたところ、基板とＬＥＤ素子の間の接合面積は９５％に達し、基板とＬＥＤ素子の間のＡｕ−Ｓｎ合金はんだ接合層には５％のボイド面積しか見られなかった。ただし、ＬＥＤ素子接合部周辺にフラックス残渣が観察された。 Example 1
The previously prepared Au—Sn alloy solder paste was applied onto the previously prepared alumina substrate by the pin transfer method, and this was put into a thermal convection furnace in a nitrogen atmosphere and held at 200 ° C. for 60 seconds. After that, when reflow treatment was performed by holding at 310 ° C. for 30 seconds and cooling, an Au—Sn alloy solder paste melting portion having a solidified Au—Sn alloy solder layer in the center and a flux residue remaining around it was formed. It was done. The flux residue in the melted portion of the Au-Sn alloy solder paste is washed and removed with a normal cleaning solution to leave a solidified Au-Sn alloy solder layer, and then a commercially available non-halogen flux (Senju) is formed on the solidified Au-Sn alloy solder layer. A small amount of non-halogen flux layer having an area of 8% of the bottom area of the device is formed by a pin transfer method using a metal Deltalux 527N) with a transfer pin having a diameter of 300 μm, and an LED device is formed on the non-halogen flux layer. In this state, while the alumina substrate was vibrated, it was placed in a thermal convection furnace in a nitrogen atmosphere, but the LED element did not fall from the alumina substrate. The LED element can be bonded to the surface of the substrate by placing the LED element on an alumina substrate in a heat convection furnace in a nitrogen atmosphere and heating to 318 ° C. for 10 seconds to perform a reflow treatment. did it.
When the joint portion was examined, the joint area between the substrate and the LED element reached 95%, and only a void area of 5% was found in the Au—Sn alloy solder joint layer between the substrate and the LED element. However, a flux residue was observed around the LED element joint.

なお、接合面積はＴｏｓｈｉｂａ ＩＴ＆Ｃｏｎｔｏｒｏｌ Ｓｙｓｔｅｍ‘ｓ Ｔｏｓｈｉｃｒｏｎ−６０９０ＦＤにより測定し、ボイド面積は透過Ｘ線により測定した。
The junction area was measured by Toshiba IT & Control System's Toshiron-6090FD, and the void area was measured by transmission X-ray.

実施例２

実施例１において、Ａｕ−Ｓｎ合金はんだペースト溶融部分のフラックス残渣を通常の洗浄液で洗浄し除去して凝固Ａｕ−Ｓｎ合金はんだ層を残したのち、凝固Ａｕ−Ｓｎ合金はんだ層の上に先に用意したノンハロゲンフラックス１を径：３００μｍの転写ピンを用いたピン転写法により素子の底面積の１３％の面積を有する少量の低残渣ノンハロゲンフラックス層を形成し、この低残渣ノンハロゲンフラックス層の上にＬＥＤ素子を乗せ、この状態でアルミナ製基板に振動を与えながら窒素雰囲気中の熱対流型炉に装入したがＬＥＤ素子がアルミナ製基板から落下することはなかった。ＬＥＤ素子をアルミナ製基板の上に乗せた状態で窒素雰囲気中の熱対流型炉に装入し、３１８℃に１０秒間加熱してリフロー処理を施すことにより基板表面にＬＥＤ素子を接合することができた。
接合部分を調べたところ、基板とＬＥＤ素子の間の接合面積は９１％に達し、基板とＬＥＤ素子の間のＡｕ−Ｓｎ合金はんだ接合層に生成したボイド面積を実施例１と同様にして測定したところ９％のボイド面積しか見られなかった。そしてフラックス残渣は観察されなかった。
Example 2

In Example 1, after the flux residue of the melted portion of the Au—Sn alloy solder paste was washed and removed with a normal cleaning liquid to leave a solidified Au—Sn alloy solder layer, the solidified Au—Sn alloy solder layer was previously placed on the solidified Au—Sn alloy solder layer. A small amount of low-residue non-halogen flux layer having an area of 13% of the bottom area of the device is formed on the prepared non-halogen flux 1 by a pin transfer method using a transfer pin having a diameter of 300 μm. In this state, the LED element was placed, and while the alumina substrate was vibrated, it was placed in a thermal convection furnace in a nitrogen atmosphere, but the LED element did not fall from the alumina substrate. The LED element can be bonded to the surface of the substrate by placing the LED element on an alumina substrate in a heat convection furnace in a nitrogen atmosphere and heating to 318 ° C. for 10 seconds to perform a reflow treatment. did it.
When the joint portion was examined, the joint area between the substrate and the LED element reached 91%, and the void area generated in the Au—Sn alloy solder joint layer between the substrate and the LED element was measured in the same manner as in Example 1. As a result, only a void area of 9% was observed. And no flux residue was observed.

実施例３
実施例１において、Ａｕ−Ｓｎ合金はんだペースト溶融部分のフラックス残渣を通常の洗浄液で洗浄し除去して凝固Ａｕ−Ｓｎ合金はんだ層を残したのち、凝固Ａｕ−Ｓｎ合金はんだ層の上に先に用意したノンハロゲンフラックス２を径：３００μｍの転写ピンを用いたピン転写法により素子の底面全面に行きわたるように低残渣ノンハロゲンフラックス層を形成し、この低残渣ノンハロゲンフラックス層の上にＬＥＤ素子を乗せ、この状態でアルミナ製基板に振動を与えながら窒素雰囲気中の熱対流型炉に装入したがＬＥＤ素子がアルミナ製基板から落下することはなかった。ＬＥＤ素子をアルミナ製基板の上に乗せた状態で窒素雰囲気中の熱対流型炉に装入し、３１８℃に１０秒間加熱してリフロー処理を施すことにより基板表面にＬＥＤ素子を接合することができた。
接合部分を調べたところ、基板とＬＥＤ素子の間の接合面積は９０％に達し、基板とＬＥＤ素子の間のＡｕ−Ｓｎ合金はんだ接合層に生成したボイド面積を実施例１と同様にして測定したところ１０％のボイド面積しか見られなかった。そしてフラックス残渣は観察されなかった。 Example 3
In Example 1, after the flux residue of the melted portion of the Au—Sn alloy solder paste was washed and removed with a normal cleaning liquid to leave a solidified Au—Sn alloy solder layer, the solidified Au—Sn alloy solder layer was previously placed on the solidified Au—Sn alloy solder layer. A low-residue non-halogen flux layer is formed so that the prepared non-halogen flux 2 reaches the entire bottom surface of the device by a pin transfer method using a transfer pin having a diameter of 300 μm, and an LED element is placed on the low-residue non-halogen flux layer. In this state, the LED element was not dropped from the alumina substrate although it was placed in a thermal convection furnace in a nitrogen atmosphere while vibrating the alumina substrate. The LED element can be bonded to the surface of the substrate by placing the LED element on an alumina substrate in a heat convection furnace in a nitrogen atmosphere and heating to 318 ° C. for 10 seconds to perform a reflow treatment. did it.
When the joint portion was examined, the joint area between the substrate and the LED element reached 90%, and the void area generated in the Au—Sn alloy solder joint layer between the substrate and the LED element was measured in the same manner as in Example 1. As a result, only a void area of 10% was observed. And no flux residue was observed.

従来例１
基板にＡｕ−Ｓｎ合金はんだペーストを実施例１と同様にして塗布し、次に、このＡｕ−Ｓｎ合金はんだペーストの上にＬＥＤ素子を搭載し、この状態で温度：２００℃、６０秒間加熱した後、さらに温度：３１８℃、３０秒間加熱してリフロー処理を施し、その後、冷却し、Ａｕ−Ｓｎ合金はんだ接合層を介してと基板とＬＥＤ素子を接合した。Ａｕ−Ｓｎ合金はんだ接合層の周囲にはフラックス残渣層が形成されていたので、実施例１と同様にしてフラックス残渣層を洗浄液で洗浄し除去し、接合部分を実施例１と同様にして調べたところ、基板とＬＥＤ素子の間の接合面積は６５％であり、基板とＬＥＤ素子の間のＡｕ−Ｓｎ合金はんだ接合層には３５％のボイド面積があった。 Conventional Example 1
An Au—Sn alloy solder paste was applied to the substrate in the same manner as in Example 1. Next, an LED element was mounted on the Au—Sn alloy solder paste, and heated at a temperature of 200 ° C. for 60 seconds in this state. Thereafter, the substrate was further reflowed by heating at a temperature of 318 ° C. for 30 seconds, then cooled, and the substrate and the LED element were bonded together via an Au—Sn alloy solder bonding layer. Since a flux residue layer was formed around the Au-Sn alloy solder joint layer, the flux residue layer was washed and removed with a cleaning liquid in the same manner as in Example 1, and the joint portion was examined in the same manner as in Example 1. As a result, the bonding area between the substrate and the LED element was 65%, and the Au—Sn alloy solder bonding layer between the substrate and the LED element had a void area of 35%.

実施例１〜３および従来例１に示される結果から、従来法では２００℃、６０秒間加熱してリフロー処理を施したのち、さらに温度：３１８℃、３０秒間加熱してリフロー処理することから、高温に長時間保持してろう付けにする必要があるが、この発明の方法によると、ＬＥＤ素子を３１８℃、１０秒間保持の短時間加熱のリフロー処理するだけで基板と素子を接合することができ、特にＬＥＤ素子が高温に曝される時間が短いので熱によるＬＥＤ素子の性能低下が少なく、さらに、この発明の接合方法は、従来の接合方法に比べてボイドの発生が少ないことが分かる。   From the results shown in Examples 1 to 3 and Conventional Example 1, in the conventional method, after performing the reflow treatment by heating at 200 ° C. for 60 seconds, and further performing the reflow treatment by heating at a temperature of 318 ° C. for 30 seconds, Although it is necessary to braze by holding at a high temperature for a long time, according to the method of the present invention, the substrate and the element can be joined only by reflowing the LED element at 318 ° C. for 10 seconds. In particular, since the LED element is exposed to a high temperature for a short period of time, the performance of the LED element is less deteriorated due to heat. Further, it can be seen that the bonding method of the present invention generates less voids than the conventional bonding method.

この発明の方法により基板と素子を接合する工程を説明するための説明図である。It is explanatory drawing for demonstrating the process of joining a board | substrate and an element by the method of this invention. 従来の方法により基板と素子を接合する工程を説明するための説明図である。It is explanatory drawing for demonstrating the process of joining a board | substrate and an element with the conventional method.

符号の説明Explanation of symbols

１：基板、２：Ａｕ−Ｓｎ合金はんだペースト、３：素子、４：凝固Ａｕ−Ｓｎ合金はんだ層、５：フラックス残渣層、４０：Ａｕ−Ｓｎ合金はんだ接合層、５１：ノンハロゲンフラックス層。
1: substrate, 2: Au—Sn alloy solder paste, 3: element, 4: solidified Au—Sn alloy solder layer, 5: flux residue layer, 40: Au—Sn alloy solder joint layer, 51: non-halogen flux layer.

Claims (3)

Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち非酸化性雰囲気中でリフロー処理し、リフロー処理したＡｕ−Ｓｎ合金はんだペーストのフラックス残渣部分を洗浄して除去して基板表面に凝固Ａｕ−Ｓｎ合金はんだ層を形成し、基板表面の凝固Ａｕ−Ｓｎ合金はんだ層の表面にノンハロゲンフラックスを塗布し、このノンハロゲンフラックスの上に素子を搭載したのち非酸化性雰囲気中でリフロー処理して素子を基板に接合する接合方法であって、
前記ノンハロゲンフラックスが、水酸基を４〜６個有する糖類を含む還元性固体活性剤を５〜６０質量％、イソボルニル基を有する化合物を含む高粘性溶剤を１０〜６０質量％、および低粘性溶剤を２０〜７０質量％を含有するフラックスであることを特徴とするＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法。 After the Au—Sn alloy solder paste is mounted on or applied to the substrate, it is reflowed in a non-oxidizing atmosphere, and the flux residue portion of the reflowed Au—Sn alloy solder paste is washed and removed to solidify Au— An Sn alloy solder layer is formed, a non-halogen flux is applied to the surface of the solidified Au—Sn alloy solder layer on the substrate surface, an element is mounted on the non-halogen flux , and then the element is reflowed in a non-oxidizing atmosphere. A bonding method for bonding to a substrate,
The non-halogen flux is 5 to 60% by mass of a reducing solid activator containing a saccharide having 4 to 6 hydroxyl groups, 10 to 60% by mass of a high viscosity solvent containing a compound having an isobornyl group, and 20 of a low viscosity solvent. A method for joining a substrate and an element using an Au—Sn alloy solder paste, characterized in that the flux contains ˜70 mass%. Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち非酸化性雰囲気中でリフロー処理し、リフロー処理したＡｕ−Ｓｎ合金はんだペーストのフラックス残渣部分を洗浄して除去して基板表面に凝固Ａｕ−Ｓｎ合金はんだ層を形成し、基板表面の凝固Ａｕ−Ｓｎ合金はんだ層の表面にノンハロゲンフラックスを素子の底面積の１〜１５％の面積となるように少量塗布し、このノンハロゲンフラックスの上に素子を搭載したのち非酸化性雰囲気中でリフロー処理して素子を基板に接合することを特徴とするＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法。 After the Au—Sn alloy solder paste is mounted on or applied to the substrate, it is reflowed in a non-oxidizing atmosphere, and the flux residue portion of the reflowed Au—Sn alloy solder paste is washed and removed to solidify Au— A Sn alloy solder layer is formed, and a small amount of non-halogen flux is applied to the surface of the solidified Au—Sn alloy solder layer on the surface of the substrate so as to be 1 to 15% of the bottom area of the device. And bonding the element to the substrate by reflow treatment in a non-oxidizing atmosphere and mounting the substrate and the element using an Au—Sn alloy solder paste. 前記Ａｕ−Ｓｎ合金はんだペーストは、Ｓｎ：１５〜２５質量％を含有し、残りがＡｕおよび不可避不純物からなる組成を有するＡｕ−Ｓｎ合金粉末とフラックスとを混合して得られたＡｕ−Ｓｎ合金はんだペーストであることを特徴とする請求項１または２記載のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法。   The Au—Sn alloy solder paste contains Sn: 15 to 25% by mass, and the remainder is Au—Sn alloy obtained by mixing an Au—Sn alloy powder having a composition composed of Au and inevitable impurities and a flux. The method for joining a substrate and an element using the Au-Sn alloy solder paste according to claim 1 or 2, wherein the solder paste is used.
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