JPS63130258A - Junction structure - Google Patents
Junction structureInfo
- Publication number
- JPS63130258A JPS63130258A JP27402286A JP27402286A JPS63130258A JP S63130258 A JPS63130258 A JP S63130258A JP 27402286 A JP27402286 A JP 27402286A JP 27402286 A JP27402286 A JP 27402286A JP S63130258 A JPS63130258 A JP S63130258A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- solder
- oxide film
- junction
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims abstract description 13
- 239000000853 adhesive Substances 0.000 claims abstract description 7
- 230000001070 adhesive effect Effects 0.000 claims abstract description 7
- 238000005304 joining Methods 0.000 claims abstract description 6
- 238000005219 brazing Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 20
- 239000004065 semiconductor Substances 0.000 abstract description 16
- 239000007769 metal material Substances 0.000 abstract description 10
- 239000011800 void material Substances 0.000 abstract description 8
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 239000000945 filler Substances 0.000 description 4
- 230000004907 flux Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、対向する基体を接着剤を用いて接合する接合
構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a joining structure in which opposing substrates are joined using an adhesive.
文献、［ジャーナル オブ バキューム サイエンス
テクノロジー、エイ（Ｊ、ｖａＣｏＳＣｌ。Literature, [Journal of Vacuum Science
Technology, A (J, vaCoSCl.
’ｐｅｃｈｎｏｌ、 Ａ ） ｓ第１巻第３号、１９８
３年、第１４８０頁」に示されるように接合に用いるろ
う材表面には少なからず酸化膜の成長が見られる。この
酸化膜を十分に除去せずに接合すると、接合界面に酸化
膜が介在するため接合強度が著しく低下する。そこで、
従来、ろう材表面の酸化膜を除去するために被接合材を
機械的に摺動させたり、フラックスを用いてろう材表面
の酸化膜を溶解する工夫が行われていた。'pechnol, A)s Vol. 1 No. 3, 198
3, p. 1480, a considerable amount of oxide film has grown on the surface of the brazing material used for bonding. If this oxide film is not sufficiently removed before bonding, the oxide film will be present at the bonding interface, resulting in a significant decrease in bonding strength. Therefore,
Conventionally, attempts have been made to remove the oxide film on the surface of the brazing material by mechanically sliding the materials to be joined or using flux to dissolve the oxide film on the surface of the brazing material.
しかし、上記摺動方法では、酸化膜を完全に除去するこ
とが困難であり、また、フラックスを用いても残渣を完
全に取りきれないなどの問題がみられた。しかも、この
残渣は接合部にボイドを発生させ、接合強度を低下させ
る原因となっていた。However, with the above-mentioned sliding method, it is difficult to completely remove the oxide film, and even when flux is used, there are problems in that the residue cannot be completely removed. Moreover, this residue causes voids to occur in the bonded portion, causing a reduction in bonding strength.
本発明の目的は、フラックスを使用せずにろう材表面の
酸化膜を破り、真性なろう材による接合を可能ならしめ
ることにより、接合部にボイドがなく機械強度の優れた
接合構造を提供することにある。The purpose of the present invention is to provide a bonded structure with no voids in the joint and excellent mechanical strength by breaking the oxide film on the surface of the brazing filler metal and making it possible to bond with an intrinsic brazing filler metal without using flux. There is a particular thing.
上記目的は、予めろう材等の接着剤が被着形成され互い
に対向してなる基体のほぼ中央に上記接着剤とは異なる
等えば金属材等を配置し、これがろう材表面の酸化膜を
破る効果を利用することにより、達成される。The above purpose is to place a metal material, etc., which is different from the adhesive, approximately in the center of the substrates, which are faced to each other and are coated with an adhesive such as a brazing filler metal in advance, and this breaks the oxide film on the surface of the brazing filler metal. This is achieved by using the effect.
本発明は、互いに対向する基体の接合時に、金属材がろ
う材表面の酸化膜を破９、真性なろう材による接合を促
すように作用するので、接合部のボイド発生をなくし接
合強度を改善することができる。In the present invention, when bonding substrates facing each other, the metal material breaks the oxide film on the surface of the brazing material9 and acts to promote bonding by the intrinsic brazing material, thereby eliminating voids in the bonded portion and improving bonding strength. can do.
以下、本発明の一実施例を第１図により詳細に説明する
。Hereinafter, one embodiment of the present invention will be explained in detail with reference to FIG.
第１図は本発明による半田接合プロセスを説明する断面
図である。１１１′ｉ金属材、２は半導体チップ、３は
ヒートシンク材である。４はｐｄ−６０ｗ ｔ ％ Ｓ
ｎの予備半田層で、半導体チップ２とヒートシンク材
３のメタライズ層５に予め被着形成した。この予備半田
Ｎ４の表面には自然酸化Ｍ６が成長している。金属材１
にはＡｕもしくはＣｕなどの半田に濡れ易い金属を用い
、半導体チップ２のほぼ中央部に配置した。ここで用い
た金属材１の寸法は厚さ５０μｍ２幅１ｍｍである。FIG. 1 is a sectional view illustrating a solder bonding process according to the present invention. 111'i is a metal material, 2 is a semiconductor chip, and 3 is a heat sink material. 4 is pd-60wt%S
A preliminary solder layer of n was formed in advance to adhere to the semiconductor chip 2 and the metallized layer 5 of the heat sink material 3. Natural oxidation M6 has grown on the surface of this preliminary solder N4. Metal material 1
A metal that is easily wetted by solder, such as Au or Cu, is used for the semiconductor chip 2, and is placed approximately in the center of the semiconductor chip 2. The dimensions of the metal material 1 used here were 50 μm in thickness and 1 mm in width.
次に第１図（ｂ）に示すように予備半田層４を溶融し、
半導体チップ２に荷重を加えて半田層４を圧縮した。こ
のとき金属材１を半導体チップ２の中央に配置しである
ため金属材１のエツジ部により酸化膜６の一部が破られ
、それと同時に半田の表面張力が作用して酸化膜６は接
合周辺部へ押しやられた。この結果、第１図（Ｃ）に示
すように酸化膜６の大部分が半導体チップ２の周囲に集
まることになり、半導体チップ２の直下に真性な半田に
よる良好な接合状態が実現できた。Next, as shown in FIG. 1(b), the preliminary solder layer 4 is melted,
A load was applied to the semiconductor chip 2 to compress the solder layer 4. At this time, since the metal material 1 is placed in the center of the semiconductor chip 2, a part of the oxide film 6 is broken by the edges of the metal material 1, and at the same time, the surface tension of the solder acts and the oxide film 6 is damaged around the bonding area. I was pushed to the department. As a result, most of the oxide film 6 gathered around the semiconductor chip 2 as shown in FIG. 1(C), and a good bonding state using intrinsic solder could be achieved directly under the semiconductor chip 2.
第２図、第３図は、−例として本発明による半田接合方
式でのボイド率の低減効果を示すものである。第２図は
、半田固着試料の軟エックス線透過像であり、白色部が
ボイド部分、黒色部が半田接合部分に対応する。第２図
のＡが従来方式（半田固着時に摺動する方法）で半田接
合したものであり、第２図のＢが本発明の方式を用いて
半田接合したものである。また、第３図は、従来方式Ａ
および本発明の方式Ｂを用いて半田接合したそれぞれ１
０個の試料について測定したボイド率の分布と平均値（
Ｏ印およびΔ印）である。FIGS. 2 and 3 show, as an example, the effect of reducing the void ratio in the solder bonding method according to the present invention. FIG. 2 is a soft X-ray transmission image of the solder-fixed sample, where white parts correspond to void parts and black parts correspond to solder joint parts. A in FIG. 2 shows the solder bonded using the conventional method (sliding method when the solder is fixed), and B in FIG. 2 shows the solder bonded using the method of the present invention. Also, Figure 3 shows conventional method A.
and 1 each soldered using method B of the present invention.
Distribution and average value of void ratio measured for 0 samples (
O mark and Δ mark).
これらの結果から、本発明により約５％のボイド率に低
減できたことが明らかである。From these results, it is clear that the present invention was able to reduce the void ratio to about 5%.
以上のように本実施例によれば、半導体チップとヒート
シンク材との接合には、酸化膜が介在しないためボイド
率が低減し、接合強度が著しく改善された。As described above, according to this example, since no oxide film is present in the bonding between the semiconductor chip and the heat sink material, the void ratio is reduced and the bonding strength is significantly improved.
本発明によれば、半導体チップとヒートシンク材との接
合部には酸化膜が一切介在しないためボイドがなくなり
、接合強度が著しく改善される効果がある。これにより
、半導体チップの放熱特性が改善され、半田接合デバイ
スの信頼性向上に顕著な効果が得られる。According to the present invention, since no oxide film is present at the joint between the semiconductor chip and the heat sink material, voids are eliminated and the joint strength is significantly improved. This improves the heat dissipation characteristics of the semiconductor chip and has a significant effect on improving the reliability of solder bonded devices.
第１図は本発明の一実施例の半田接合プロセスを説明す
る断面図、第２図は従来例および本発明による半田接合
方式での接せ部の組＠を示す顕微鏡写真、第３図はボイ
ド率の低減効果を示すグラフである。
１・・・金属材、２・・・半導体チップ、３・・・ヒー
トシンク材、４・・・半田層、５・・・メタライズ層、
６・・・酸化膜・
７．〜２、代理人 弁理士 小川Ｆｙｆ勇 。
第１図
（Ｑン
５ メツライス゛’、４ １ ００イ乙ル巨Ｚ
Ｚ 図
ＣＡ） （ｆ３ジ
第３図
手続補正書（方式）
％式％
事件の表示
昭和６１ 年特許願第２７４０２２ 号発明の名称
接合構造
補正をする者
・Ｉｉ件トノｌ１ｌｌ係特許出願人
名 称 （５１０）株式会社 日 立 製作
折代 理 人
ｔ・・ン 所 〒１（Ｘｌ東京都千代田区丸の内
−丁目５番１号株式会ン１日立製作所内 Ｘ１話 ・Ｊ
弓４２１２−１１１１ Ｆ大代表）、・１行
補正の内容
】、明細−９第６百第］〜３行目、「第２図は・・印・
顕微境写真、」までの記載を下記に訂正する。
記
「第２図は半田固着試料のＸ線透過像のＸ線写真、」Fig. 1 is a cross-sectional view illustrating the solder bonding process according to an embodiment of the present invention, Fig. 2 is a microscopic photograph showing a set of contact parts in the conventional example and the solder bonding method according to the present invention, and Fig. 3 is a It is a graph showing the effect of reducing void ratio. DESCRIPTION OF SYMBOLS 1... Metal material, 2... Semiconductor chip, 3... Heat sink material, 4... Solder layer, 5... Metallized layer,
6...Oxide film/
7. ~2. Agent: Patent attorney Isamu Ogawa Fyf. Figure 1 (Qn5 Metsurai', 4 100 Ioturu Giant Z
Z Figure CA) (f3 Figure 3 Procedural amendment (method) % formula % Display of the case 1985 Patent Application No. 274022 Name of the invention Joint structure amendment person / Name of the patent applicant in relation to Ii Tono l1ll ( 510) Hitachi Co., Ltd. Production Agent Location: 1 (Xl Hitachi, Ltd., 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo, Hitachi, Ltd. Chapter X1 ・J
Bow 4212-1111 F large representative), 1 line correction contents], Specification-9 No. 600] - 3rd line, ``Figure 2 is marked...
The description up to "Microscopic photograph" has been corrected as below. ``Figure 2 is an X-ray photograph of an X-ray transmission image of a solder-fixed sample.''
Claims (1)
造において、前記接着剤と異なる部材が接合面のほぼ中
央に介在してなることを特徴とする接合構造。 ２、前記接着剤として、ろう材を用いることを特徴とす
る第１項記載の接合構造。 ３、前記部材として、金属を用いることを特徴とする第
１項記載の接合構造。[Claims] 1. A bonding structure in which opposing substrates are bonded using an adhesive, characterized in that a member different from the adhesive is interposed approximately at the center of the bonding surfaces. 2. The joining structure according to item 1, wherein a brazing material is used as the adhesive. 3. The joining structure according to item 1, wherein the member is made of metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27402286A JPS63130258A (en) | 1986-11-19 | 1986-11-19 | Junction structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27402286A JPS63130258A (en) | 1986-11-19 | 1986-11-19 | Junction structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63130258A true JPS63130258A (en) | 1988-06-02 |
Family
ID=17535866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27402286A Pending JPS63130258A (en) | 1986-11-19 | 1986-11-19 | Junction structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63130258A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877079A (en) * | 1996-12-02 | 1999-03-02 | Fujitsu Limited | Method for manufacturing a semiconductor device and a method for mounting a semiconductor device for eliminating a void |
| JP2002118294A (en) * | 2000-04-24 | 2002-04-19 | Nichia Chem Ind Ltd | Flip chip type light-emitting diode and manufacturing method thereof |
| JP2007061857A (en) * | 2005-08-31 | 2007-03-15 | Mitsubishi Materials Corp | METHOD OF JOINING SUBSTRATE AND ELEMENT USING Au-Sn ALLOY SOLDER PASTE |
| JP2008192965A (en) * | 2007-02-07 | 2008-08-21 | Denso Corp | Packaging method of semiconductor chip |
-
1986
- 1986-11-19 JP JP27402286A patent/JPS63130258A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877079A (en) * | 1996-12-02 | 1999-03-02 | Fujitsu Limited | Method for manufacturing a semiconductor device and a method for mounting a semiconductor device for eliminating a void |
| JP2002118294A (en) * | 2000-04-24 | 2002-04-19 | Nichia Chem Ind Ltd | Flip chip type light-emitting diode and manufacturing method thereof |
| JP2007061857A (en) * | 2005-08-31 | 2007-03-15 | Mitsubishi Materials Corp | METHOD OF JOINING SUBSTRATE AND ELEMENT USING Au-Sn ALLOY SOLDER PASTE |
| JP4600672B2 (en) * | 2005-08-31 | 2010-12-15 | 三菱マテリアル株式会社 | Method of joining substrate and device using Au-Sn alloy solder paste |
| JP2008192965A (en) * | 2007-02-07 | 2008-08-21 | Denso Corp | Packaging method of semiconductor chip |
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