JP4747280B2 - Method of joining substrate and device using Au-Sn alloy solder paste - Google Patents

Method of joining substrate and device using Au-Sn alloy solder paste Download PDF

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JP4747280B2
JP4747280B2 JP2006090901A JP2006090901A JP4747280B2 JP 4747280 B2 JP4747280 B2 JP 4747280B2 JP 2006090901 A JP2006090901 A JP 2006090901A JP 2006090901 A JP2006090901 A JP 2006090901A JP 4747280 B2 JP4747280 B2 JP 4747280B2
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alloy solder
substrate
solder paste
alloy
molten
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JP2007266404A (en
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石川　　雅之
正好 小日向
昭史 三島
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Mitsubishi Materials Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium

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Description

この発明は、Ａｕ−Ｓｎ合金はんだペーストを用いて基板と素子との間の接合部にボイドを発生させることなく接合する方法に関するものであり、特に使用中に発生した熱を放出する必要のある素子、例えば、ＬＥＤ（発光ダイオード）素子を基板に接合する方法に関するものである。   The present invention relates to a method of bonding without generating voids at a bonding portion between a substrate and an element using an Au—Sn alloy solder paste, and it is particularly necessary to release heat generated during use. The present invention relates to a method of bonding an element, for example, an LED (light emitting diode) element to a substrate.

ＬＥＤ（発光ダイオード）素子、ＧａＡｓ光素子、ＧａＡｓ高周波素子、熱伝素子などの半導体素子と基板との接合、特に熱がこもると破損に繋がるようなＬＥＤ（発光ダイオード）素子と基板との接合には、接合部の熱伝導性が非常に重要であるところから、熱伝導性が良くかつ信頼性が高い接合部を形成するＡｕ−Ｓｎ合金はんだ箔材(リボンなど)、Ａｕバンプ、Ａｕ−Ｓｎ合金はんだペーストが用いられていた。
For bonding a semiconductor element such as an LED (light-emitting diode) element, a GaAs optical element, a GaAs high-frequency element, or a heat transfer element to the substrate, particularly for bonding an LED (light-emitting diode) element and the substrate that may be damaged when heat is accumulated. Since the thermal conductivity of the joint is very important, an Au—Sn alloy solder foil material (ribbon or the like), Au bump, Au—Sn that forms a joint with good thermal conductivity and high reliability. An alloy solder paste was used.

しかし、Ａｕ−Ｓｎはんだ合金箔材(リボンなど)は、材料自身の熱伝導性は高いものの接合時の濡れ性が悪いため接合領域を十分に広く取ることができず、また箔材表面には酸化膜が多いため溶融したＡｕ−Ｓｎはんだ合金の流動性が悪い。そのため加熱溶融しながら荷重をかけて接合する工法もあるが、加熱時間が長くまた長時間荷重をかけて接合しなければならないことから、熱を長時間かけることが好ましくないＬＥＤ（発光ダイオード）素子に適用することができない。さらに、Ａｕ−Ｓｎはんだ合金箔材の場合、素子に荷重をかけて接合することから素子側面部にＡｕ−Ｓｎはんだ合金が這い上がりショートを起こすこともあった。
However, Au-Sn solder alloy foil materials (ribbons, etc.) have high thermal conductivity, but the wettability at the time of bonding is poor, so that the bonding area cannot be made sufficiently wide. Since there are many oxide films, the fluidity of the molten Au—Sn solder alloy is poor. For this reason, there is a method of joining by applying a load while heating and melting, but an LED (light emitting diode) element in which it is not preferable to apply heat for a long time because the heating time is long and it is necessary to apply a load for a long time. Cannot be applied to. Further, in the case of the Au—Sn solder alloy foil material, since the load is applied to the element, the Au—Sn solder alloy may creep up on the side surface of the element and cause a short circuit.

また、Ａｕバンプ法による素子の接合は、素子全体にＡｕ−Ｓｎはんだ合金接合層が接合していないため、Ａｕ−Ｓｎはんだ合金接合層と接合していない部分の熱伝導が悪く、また、このＡｕバンプ法では３００℃以上の温度で荷重をかけながら接合を行なうが、３００℃以上高温を長時間保持する必要があり、熱影響を受けて劣化しやすいＬＥＤ（発光ダイオード）素子に適用することができなかった。

そのため、近年、熱影響を受けて劣化しやすいＬＥＤ（発光ダイオード）素子の接合には接合信頼性の一層優れたＡｕ−Ｓｎ合金はんだペーストが多く用いられるようになってきた。このＡｕ−Ｓｎ合金はんだペーストは、Ｓｎ：１５〜２５質量％（好ましくはＳｎ：２０質量％）を含有し、残りがＡｕおよび不可避不純物からなる組成を有するＡｕ−Ｓｎ共晶合金ガスアトマイズ粉末とロジン、活性剤、溶剤および増粘剤からなる市販のフラックスとを混合して作られる。
In addition, since the Au-Sn solder alloy bonding layer is not bonded to the entire element in the bonding of the elements by the Au bump method, the heat conduction of the portion not bonded to the Au-Sn solder alloy bonding layer is poor. In the Au bump method, bonding is performed while applying a load at a temperature of 300 ° C. or higher, but it is necessary to maintain a high temperature of 300 ° C. or higher for a long time, and it is applied to an LED (light emitting diode) element that is easily deteriorated due to thermal influence I could not.

For this reason, in recent years, Au-Sn alloy solder pastes with higher bonding reliability have been frequently used for bonding LED (light-emitting diode) elements that are easily deteriorated under the influence of heat. This Au—Sn alloy solder paste contains Sn: 15 to 25% by mass (preferably Sn: 20% by mass), and the remainder is composed of Au and inevitable impurities. Au—Sn eutectic alloy gas atomized powder and rosin It is made by mixing a commercially available flux consisting of an activator, a solvent and a thickener.


このＡｕ−Ｓｎ合金はんだペーストを使用して素子と基板を接合すると接合部がＡｕ−Ｓｎ合金はんだであるので熱伝導性が良く接合信頼性も高いこと、ペーストであるので複数の接合部に一括供給できさらに一括熱処理できること、リフロー時にフラックスがＡｕ−Ｓｎはんだ合金表面を覆っているために酸化膜が少なく、そのため、接合時の溶融Ａｕ−Ｓｎはんだ合金の流動性が大きく、濡れが良くなって接合面積を拡大することができるところから素子全面を接合できること、さらに接合時に過剰な荷重をかける必要がないことなどのメリットがある。

このＡｕ−Ｓｎ合金はんだペーストを用いて基板と素子を接合する方法を図３の側面図に基づいて説明する。Ａｕ−Ｓｎ合金はんだペーストを用いて基板と素子を接合するには図３（ａ）に示されるように、基板１にＡｕ−Ｓｎ合金はんだペースト２を搭載または塗布する。次に、このＡｕ−Ｓｎ合金はんだペースト２の真上に図３（ｂ）に示されるように素子３を搭載し、この状態で加熱してリフロー処理を施したのち冷却すると、図３（ｃ）に示されるように、Ａｕ−Ｓｎ合金はんだ接合層４を介してと基板１と素子３が接合する（特許文献１または２など参照）。
特開２００３−１０５４６２ 特開２００３−２６０５８８
When an element and a substrate are bonded using this Au-Sn alloy solder paste, the bonding portion is Au-Sn alloy solder, so that the thermal conductivity is good and the bonding reliability is high. It can be supplied and batch heat treated, and the flux covers the Au-Sn solder alloy surface during reflow, so there is little oxide film. There are merits such that the entire surface of the element can be bonded since the bonding area can be expanded, and that it is not necessary to apply an excessive load during bonding.

A method of joining the substrate and the element using this Au—Sn alloy solder paste will be described with reference to the side view of FIG. In order to join the substrate and the device using the Au—Sn alloy solder paste, the Au—Sn alloy solder paste 2 is mounted or applied to the substrate 1 as shown in FIG. Next, as shown in FIG. 3B, the element 3 is mounted immediately above the Au—Sn alloy solder paste 2, heated in this state, subjected to reflow treatment, and then cooled. ), The substrate 1 and the element 3 are bonded via the Au—Sn alloy solder bonding layer 4 (see Patent Document 1 or 2).
JP 2003-105462 A JP 2003-260588 A


前述のように、Ａｕ−Ｓｎ合金はんだペーストは最も使いやすい接合材であるが、Ａｕ−Ｓｎ合金はんだペーストには前述のように有機物からなるフラックスを含んでおり、図３（ｂ）に示されるようにＡｕ−Ｓｎ合金はんだペースト２の上に素子３を搭載し、この状態で加熱してリフロー処理を施すと、Ａｕ−Ｓｎ合金はんだペースト２が溶融する際にフラックスからガスが発生し、この時Ａｕ−Ｓｎ合金はんだペースト２の真上に素子３が被さっているために、溶融中に発生したガスが逃げ場を失って閉じ込められ、Ａｕ−Ｓｎ合金はんだ接合層４の中にボイド５が生成することがある。Ａｕ−Ｓｎ合金はんだ接合層４の中にボイド５が生成すると素子３と基板１との接合面積が少なくなり、接合面積が少なくなると素子３に発生した熱の放熱性が悪くなるので好ましくない。
As described above, the Au—Sn alloy solder paste is the most easy-to-use bonding material. However, the Au—Sn alloy solder paste contains the organic flux as described above, and is shown in FIG. When the element 3 is mounted on the Au—Sn alloy solder paste 2 and heated in this state and subjected to reflow treatment, gas is generated from the flux when the Au—Sn alloy solder paste 2 is melted. Since the element 3 is covered directly on the Au—Sn alloy solder paste 2, the gas generated during melting loses the escape field and is trapped, and a void 5 is generated in the Au—Sn alloy solder bonding layer 4. There are things to do. If voids 5 are generated in the Au—Sn alloy solder bonding layer 4, the bonding area between the element 3 and the substrate 1 decreases, and if the bonding area decreases, the heat dissipation of the heat generated in the element 3 deteriorates, which is not preferable.

本発明者らは、これら課題を解決すべく研究を行った。その結果、
（イ）Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布し、さらにＡｕ−Ｓｎ合金はんだペーストから離して素子を基板の上に載置し、このＡｕ−Ｓｎ合金はんだペーストおよび素子を乗せた基板を非酸化性雰囲気中でリフロー処理すると、リフロー処理中に、まず、Ａｕ−Ｓｎ合金はんだペーストが溶融してＡｕ−Ｓｎ合金はんだペーストに含まれるフラックスの分解ガスが放出され、さらにリフロー処理を続けるとＡｕ−Ｓｎ合金はんだペーストに含まれるＡｕ−Ｓｎ合金はんだ粉末が溶融してＡｕ−Ｓｎ合金はんだ粉末の表面の酸化膜とフラックスとが反応して生成したガスが放出されてガスが十分に抜けた溶融Ａｕ−Ｓｎ合金はんだが生成し、このガスが十分に抜けた溶融Ａｕ−Ｓｎ合金はんだは基板の表面を伝って濡れ広がり、濡れ広がった溶融Ａｕ−Ｓｎ合金はんだが素子に達すると、溶融したＡｕ−Ｓｎ合金はんだが素子の下に潜り込み、溶融Ａｕ−Ｓｎ合金はんだが素子の下に潜り込むと、溶融Ａｕ−Ｓｎ合金はんだのセルフアライメント効果により素子が溶融Ａｕ−Ｓｎ合金はんだの中央に向かって引き戻され、ガスが十分に抜けた溶融Ａｕ−Ｓｎ合金はんだのほぼ中央に素子が乗った状態となり、かかる状態で冷却すると、基板と素子との間のＡｕ−Ｓｎ合金はんだ接合層の中にボイドが発生することなく接合することができる、
（ロ）基板の上に素子をＡｕ−Ｓｎ合金はんだペーストに隣接するまで近づけて載置しても同様の効果が得られる、などの知見が得られたのである。 The present inventors have conducted research to solve these problems. as a result,
(A) A substrate on which an Au—Sn alloy solder paste is mounted or applied to a substrate, the device is placed on the substrate apart from the Au—Sn alloy solder paste, and the Au—Sn alloy solder paste and the device are placed on the substrate. When the reflow treatment is performed in a non-oxidizing atmosphere, first, during the reflow treatment, the Au—Sn alloy solder paste is melted to release the flux decomposition gas contained in the Au—Sn alloy solder paste, and the reflow treatment is continued. And the Au—Sn alloy solder powder contained in the Au—Sn alloy solder paste is melted and the gas generated by the reaction between the oxide film on the surface of the Au—Sn alloy solder powder and the flux is released, and the gas is sufficiently released. The molten Au—Sn alloy solder is generated, and the molten Au—Sn alloy solder from which the gas has sufficiently escaped is spread along the surface of the substrate. When the molten Au—Sn alloy solder that has spread out reaches the element, the molten Au—Sn alloy solder enters under the element, and when the molten Au—Sn alloy solder enters under the element, the molten Au—Sn alloy solder The element is pulled back toward the center of the molten Au—Sn alloy solder due to the self-alignment effect, and the element is placed almost at the center of the molten Au—Sn alloy solder from which the gas has sufficiently escaped. Bonding can be performed without generating voids in the Au-Sn alloy solder bonding layer between the substrate and the element.
(B) The knowledge that the same effect can be obtained even when the element is placed close to the Au—Sn alloy solder paste on the substrate is obtained.

この発明は、かかる知見に基づいて成されたものであって、素子を基板に載置し、さらにＡｕ−Ｓｎ合金はんだペーストを前記素子から離してまたは該素子に隣接して基板に搭載または塗布し、前記素子を載置しかつＡｕ−Ｓｎ合金はんだペーストを搭載または塗布した基板を非酸化性雰囲気中でリフロー処理し、溶融Ａｕ−Ｓｎ合金はんだが濡れ広がって前記素子の下に潜り込み、該素子が溶融Ａｕ−Ｓｎ合金はんだの中央に向かって引き戻された後、前記素子の全体が溶融Ａｕ−Ｓｎ合金はんだに乗った状態で冷却するＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法、に特徴を有するものである。 This invention, which was made on the basis of this finding, placing the element on the substrate, further mounted or coated Au-Sn alloy solder paste to the substrate adjacent to and release or the element from the element The substrate on which the element is mounted and the Au-Sn alloy solder paste is mounted or applied is reflowed in a non-oxidizing atmosphere, and the molten Au-Sn alloy solder spreads out and sinks under the element, After the element is pulled back toward the center of the molten Au—Sn alloy solder, the substrate is bonded to the element using an Au—Sn alloy solder paste that cools in a state where the entire element is mounted on the molten Au—Sn alloy solder. Characteristic of the method.

この発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を図面に基づいて具体的に説明する。図１はこの発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を説明するための側面説明図である。   A method for joining a substrate and an element using the Au—Sn alloy solder paste of the present invention will be specifically described with reference to the drawings. FIG. 1 is an explanatory side view for explaining a method of joining a substrate and an element using the Au—Sn alloy solder paste of the present invention.

図１（ａ）に示されるように、Ａｕ−Ｓｎ合金はんだペースト２を基板１に搭載または塗布し、さらに素子３を基板１の上にＡｕ−Ｓｎ合金はんだペースト２から離して載置する。この基板１の表面には最表面層としてＡｕめっき層を形成しておくことが好ましい。 このＡｕ−Ｓｎ合金はんだペースト２および素子３を乗せた基板１を非酸化性雰囲気中でリフロー処理すると、リフロー処理中に図１（ｂ）に示されるように、まず、Ａｕ−Ｓｎ合金はんだペースト２が溶融してＡｕ−Ｓｎ合金はんだペーストに含まれるフラックスの分解ガス６が放出され、さらにリフロー処理を続けるとＡｕ−Ｓｎ合金はんだペースト２に含まれるＡｕ−Ｓｎ合金はんだ粉末（図示せず）が溶融してＡｕ−Ｓｎ合金はんだ粉末の表面の酸化膜とフラックスとが反応して生成したガス６が放出されて、図１（ｃ）に示されるように、ガス６が十分に抜けた溶融Ａｕ−Ｓｎ合金はんだ４’が生成する。このガス６が十分に抜けた溶融Ａｕ−Ｓｎ合金はんだ４’は基板１の表面を伝って濡れ広がり、濡れ広がった溶融Ａｕ−Ｓｎ合金はんだ４’が素子３に達すると、図１（ｃ）に示されるように、溶融Ａｕ−Ｓｎ合金はんだ４’が素子３の下に潜り込み、溶融Ａｕ−Ｓｎ合金はんだ４’が素子３の下に潜り込むと同時に溶融Ａｕ−Ｓｎ合金はんだ４’のセルフアライメント効果により素子３が溶融Ａｕ−Ｓｎ合金はんだ４’の中央に向かって引き戻され（すなわち、図１（ｃ）のＡ方向に引き戻され）、ガスが十分に抜けた溶融Ａｕ−Ｓｎ合金はんだ４’のほぼ中央に素子３が乗った状態（素子３の全体が溶融Ａｕ−Ｓｎ合金はんだ４’上に乗った状態）となり、かかる状態で冷却すると、図１（ｄ）に示されるように、基板１と素子３との間のＡｕ−Ｓｎ合金はんだ接合層４の中にボイドが発生することなく接合することができる。
As shown in FIG. 1A, an Au—Sn alloy solder paste 2 is mounted on or applied to a substrate 1, and the element 3 is placed on the substrate 1 separately from the Au—Sn alloy solder paste 2. An Au plating layer is preferably formed on the surface of the substrate 1 as the outermost surface layer. When the substrate 1 on which the Au—Sn alloy solder paste 2 and the element 3 are placed is reflowed in a non-oxidizing atmosphere, first, as shown in FIG. 2 melts and the flux decomposition gas 6 contained in the Au—Sn alloy solder paste is released, and when the reflow process is continued, the Au—Sn alloy solder powder contained in the Au—Sn alloy solder paste 2 (not shown) Is melted and the oxide film on the surface of the Au—Sn alloy solder powder reacts with the flux to release the generated gas 6, and as shown in FIG. Au-Sn alloy solder 4 'is generated. The molten Au—Sn alloy solder 4 ′ from which the gas 6 has sufficiently escaped is wet and spread along the surface of the substrate 1, and when the molten Au—Sn alloy solder 4 ′ that has spread wet reaches the element 3, FIG. As shown in FIG. 4, the molten Au—Sn alloy solder 4 ′ sinks under the element 3, and the molten Au—Sn alloy solder 4 ′ sinks under the element 3, and at the same time, the self-alignment of the molten Au—Sn alloy solder 4 ′. Due to the effect, the element 3 is pulled back toward the center of the molten Au—Sn alloy solder 4 ′ (that is, pulled back in the direction A in FIG. 1C), and the molten Au—Sn alloy solder 4 ′ from which the gas has sufficiently escaped. As shown in FIG. 1D, when the element 3 is placed almost at the center (the whole element 3 is on the molten Au—Sn alloy solder 4 ′) and cooled in such a state. Au-S between 1 and element 3 It can be joined without voids are generated in the alloy solder bonding layer 4.


図２に示されるように、基板１の上に素子３とＡｕ−Ｓｎ合金はんだペースト２が隣接するまで近づけて載置しても同様の効果が得られる。
As shown in FIG. 2, the same effect can be obtained even if the element 3 and the Au—Sn alloy solder paste 2 are placed close to each other on the substrate 1 until they are adjacent to each other.

この発明のＡｕ−Ｓｎ合金はんだペーストを用いた接合方法によると、基板１と素子３の間の接合部にボイドの発生が少なくなって素子に発生した熱が放熱し易くなり、産業上優れた効果をもたらすものである。   According to the bonding method using the Au—Sn alloy solder paste of the present invention, the generation of voids is reduced at the bonding portion between the substrate 1 and the element 3, and the heat generated in the element is easily radiated, which is industrially excellent. It has an effect.

Ｓｎ：２２質量％を含有し、残部がＡｕからなる成分組成を有しかつ５〜１６μｍの粒径を有する粉末が８０％以上含まれるＡｕ−Ｓｎ合金はんだ粉末を用意し、このＡｕ−Ｓｎ合金はんだ粉末を市販のＲＭＡタイプのロジン系フラックスに、ロジン系フラックス：７質量％を含有し残部がＡｕ−Ｓｎ合金はんだ粉末の配合組成となるように配合し混練してＡｕ−Ｓｎ合金はんだペーストを作製した。このＡｕ−Ｓｎ合金はんだペーストは三菱マテリアル株式会社製金錫合金ペーストとして市販されているものである。

さらに、基板として厚さ：１００μｍのＣｕ板に厚さ：５μｍのＮｉめっきを施し、さらにその上に厚さ：１μｍのＡｕめっきを施した基板を用意した。
さらにＬＥＤ素子の代替として、縦：５００μｍ、横：５００μｍ、厚さ：３００μｍの角銅板を用意し、この角銅板に厚さ：５μｍのＮｉめっきを施し、さらにその上に厚さ：０．５μｍのＡｕめっきを施した代替ＬＥＤ素子を用意した。
An Au—Sn alloy solder powder containing Sn: 22% by mass, with the balance being composed of Au, and containing 80% or more of a powder having a particle size of 5 to 16 μm is prepared. This Au—Sn alloy Solder powder is mixed with a commercially available RMA type rosin-based flux, rosin-based flux: 7% by mass, with the balance being the composition of Au-Sn alloy solder powder, and kneaded to prepare an Au-Sn alloy solder paste. Produced. This Au-Sn alloy solder paste is commercially available as a gold-tin alloy paste manufactured by Mitsubishi Materials Corporation.

Further, a substrate was prepared by applying Ni plating with a thickness of 5 μm to a Cu plate with a thickness of 100 μm as a substrate, and further applying Au plating with a thickness of 1 μm thereon.
Furthermore, as an alternative to the LED element, a square copper plate having a length of 500 μm, a width of 500 μm, and a thickness of 300 μm is prepared, Ni plating of a thickness of 5 μm is applied to the square copper plate, and a thickness of 0.5 μm is further formed thereon. An alternative LED element with Au plating was prepared.

実施例１〜３
先に用意した基板の上に、先に用意したＡｕ−Ｓｎ合金はんだペーストをピン転写法により０．５ｍｇ塗布し、さらに塗布したＡｕ−Ｓｎ合金はんだペーストから 表１に示される距離となるように離して代替ＬＥＤ素子を基板の上に載置した。

かかるＡｕ−Ｓｎ合金はんだペーストを塗布しさらに代替ＬＥＤ素子を載置した基板を窒素雰囲気中の熱対流型炉に装入して２００℃に６０秒間保持したのち、さらに３１０℃、３０秒間保持することによりリフロー処理を施し、ついで冷却することにより基板と代替ＬＥＤ素子の間にＡｕ−Ｓｎ合金はんだ接合層を有するはんだ接合試験片を作製した。
Examples 1-3
Apply 0.5 mg of the previously prepared Au—Sn alloy solder paste on the previously prepared substrate by the pin transfer method, and further the distance shown in Table 1 from the applied Au—Sn alloy solder paste. Separated and placed the alternative LED element on the substrate.

The substrate on which the Au—Sn alloy solder paste is applied and the alternative LED element is mounted is placed in a thermal convection furnace in a nitrogen atmosphere and held at 200 ° C. for 60 seconds, and then held at 310 ° C. for 30 seconds. The solder joint test piece which has an Au-Sn alloy solder joint layer between the board | substrate and the alternative LED element was produced by giving a reflow process by this, and then cooling.

このはんだ接合試験片を透過Ｘ線装置（ＴｏｓｈｉｂａＩＴ＆ＣｏｎｔｒｏｌＳｙｓｔｅｍ‘ｓＴＯＳＭＩＣＲＯＮ−６０９０ＦＰ）を用いてＸ線写真を撮り、画像処理(２値化)処理して接合面積％を求め、その結果を表１に示した。
An X-ray photograph of this solder joint test piece was taken using a transmission X-ray apparatus (ToshibaIT & Control System's TOSMICRON-6090FP), image processing (binarization) processing was performed to determine the joint area%, and the results are shown in Table 1. .

従来例１
先に用意した基板の上に、先に用意したＡｕ−Ｓｎ合金はんだペーストをピン転写法により０．５ｍｇ塗布し、この塗布したＡｕ−Ｓｎ合金はんだペーストの真上に代替ＬＥＤ素子を前記Ａｕ−Ｓｎ合金はんだペーストが覆われるようにして載置し、かかるＡｕ−Ｓｎ合金はんだペーストの上に代替ＬＥＤ素子を被せるように載置した基板を窒素雰囲気中の熱対流型炉に装入して２００℃に６０秒間保持したのち、さらに３１０℃、３０秒間保持することによりリフロー処理を施し、ついで冷却することにより基板と代替ＬＥＤ素子の間にＡｕ−Ｓｎ合金はんだ接合層を有するはんだ接合試験片を作製した。 Conventional Example 1
On the previously prepared substrate, 0.5 mg of the previously prepared Au—Sn alloy solder paste is applied by a pin transfer method, and an alternative LED element is placed directly above the applied Au—Sn alloy solder paste. The Sn alloy solder paste was placed so as to be covered, and the substrate placed so as to cover the alternative LED element on the Au—Sn alloy solder paste was placed in a thermal convection type furnace in a nitrogen atmosphere and 200. A solder joint test piece having an Au—Sn alloy solder joint layer between the substrate and the alternative LED element is obtained by holding a temperature of 60 ° C. for 60 seconds, and then performing a reflow treatment by holding at 310 ° C. for 30 seconds and then cooling. Produced.

このはんだ接合試験片を透過Ｘ線装置（ＴｏｓｈｉｂａＩＴ＆ＣｏｎｔｒｏｌＳｙｓｔｅｍ‘ｓＴＯＳＭＩＣＲＯＮ−６０９０ＦＰ）を用いてＸ線写真を撮り、画像処理(２値化)処理して接合面積％を求め、その結果を表１に示した。   An X-ray photograph was taken of this solder joint test piece using a transmission X-ray apparatus (ToshibaIT & Control System's TOSMICRON-6090FP), image processing (binarization) processing was performed to determine the joint area%, and the results are shown in Table 1. .

Figure 0004747280
Figure 0004747280

実施例１〜３および従来例１に示される結果から、実施例１〜３による接合面積は従来例１に比べて格段に大きいことから、実施例１〜３の本発明方法によると、基板と素子との間に形成されているＡｕ−Ｓｎ合金はんだ接合層に発生するボイドは従来例１に比べて格段に少ないことが分かり、Ａｕ−Ｓｎ合金はんだ接合層に発生するボイドが少ないこの発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法は特に熱がこもることが好ましくないＬＥＤ素子などの接合に優れた効果を有することが分かる。   From the results shown in Examples 1 to 3 and Conventional Example 1, the bonding area according to Examples 1 to 3 is much larger than that of Conventional Example 1. Therefore, according to the method of the present invention of Examples 1 to 3, the substrate and It can be seen that the voids generated in the Au—Sn alloy solder joint layer formed between the elements are remarkably fewer than those in the conventional example 1, and the voids generated in the Au—Sn alloy solder joint layer are small. It can be seen that the bonding method between the substrate and the device using the Au—Sn alloy solder paste has an excellent effect on the bonding of an LED device or the like in which heat is not particularly preferred.

この発明の方法により基板と素子を接合する工程を説明するための側面説明図である。It is side surface explanatory drawing for demonstrating the process of joining a board | substrate and an element by the method of this invention. この発明の方法により基板と素子を接合する工程を説明するための側面説明図である。It is side surface explanatory drawing for demonstrating the process of joining a board | substrate and an element by the method of this invention. 従来の方法により基板と素子を接合する工程を説明するための側面説明図である。It is side surface explanatory drawing for demonstrating the process of joining a board | substrate and an element with the conventional method.

符号の説明Explanation of symbols

１：基板、２：Ａｕ−Ｓｎ合金はんだペースト、３：素子、４：Ａｕ−Ｓｎ合金はんだ接合層、４´：溶融Ａｕ−Ｓｎ合金はんだ、５：ボイド、６：ガス。
1: substrate, 2: Au—Sn alloy solder paste, 3: element, 4: Au—Sn alloy solder bonding layer, 4 ′: molten Au—Sn alloy solder, 5: void, 6: gas.

Claims (4)

素子を基板に載置し、さらにＡｕ−Ｓｎ合金はんだペーストを前記素子から離してまたは該素子に隣接して基板に搭載または塗布し、前記素子を載置しかつＡｕ−Ｓｎ合金はんだペーストを搭載または塗布した基板を非酸化性雰囲気中でリフロー処理し、溶融Ａｕ−Ｓｎ合金はんだが濡れ広がって前記素子の下に潜り込み、該素子が溶融Ａｕ−Ｓｎ合金はんだの中央に向かって引き戻された後、前記素子の全体が溶融Ａｕ−Ｓｎ合金はんだに乗った状態で冷却することを特徴とするＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法。 Placing the device on the substrate, mounted or applied to the substrate further adjacent the Au-Sn alloy solder paste with or the element away from the device, equipped with a mounting vital Au-Sn alloy solder paste the element Alternatively, after the coated substrate is reflowed in a non-oxidizing atmosphere, the molten Au—Sn alloy solder wets and spreads under the element, and the element is pulled back toward the center of the molten Au—Sn alloy solder. A method for joining a substrate and an element using an Au-Sn alloy solder paste , wherein the entire element is cooled in a state of being on a molten Au-Sn alloy solder. 前記素子は発光ダイオード素子であることを特徴とする請求項１記載のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法。 2. The method for bonding a substrate and an element using an Au—Sn alloy solder paste according to claim 1, wherein the element is a light emitting diode element. 前記Ａｕ−Ｓｎ合金はんだペーストは、Ｓｎ：１５〜２５質量％を含有し、残りがＡｕおよび不可避不純物からなる組成を有するＡｕ−Ｓｎ合金粉末とフラックスとを混合して得られたＡｕ−Ｓｎ合金はんだペーストであることを特徴とする請求項１記載のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法。The Au—Sn alloy solder paste contains Sn: 15 to 25% by mass, and the remainder is Au—Sn alloy obtained by mixing an Au—Sn alloy powder having a composition composed of Au and inevitable impurities and a flux. The method for joining a substrate and an element using the Au-Sn alloy solder paste according to claim 1, wherein the solder paste is a solder paste. 前記基板は表面に金メッキされた基板であることを特徴とする請求項１記載のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法。 2. The method for bonding a substrate and an element using an Au-Sn alloy solder paste according to claim 1, wherein the substrate is a substrate whose surface is gold-plated.
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