JP4592936B2 - Copper foil for electronic circuit and method for forming electronic circuit - Google Patents
Copper foil for electronic circuit and method for forming electronic circuit Download PDFInfo
- Publication number
- JP4592936B2 JP4592936B2 JP2000369753A JP2000369753A JP4592936B2 JP 4592936 B2 JP4592936 B2 JP 4592936B2 JP 2000369753 A JP2000369753 A JP 2000369753A JP 2000369753 A JP2000369753 A JP 2000369753A JP 4592936 B2 JP4592936 B2 JP 4592936B2
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- etching
- circuit
- copper
- cobalt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- ing And Chemical Polishing (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【0001】
【発明の属する技術分野】
本発明は、エッチングにより回路形成を行う電子回路用銅箔及び電子回路の形成方法に関する。
【0002】
【従来の技術】
電子・電気機器に印刷回路用銅箔が広く使用されているが、この印刷回路用銅箔は、一般に合成樹脂ボードやフイルム等の基材に接着剤を介して、あるいは接着剤を用いずに高温高圧下で接着して銅張り積層板を製造し、その後、目的とする回路を形成するためにレジスト塗布及び露光工程により回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を経、またさらに各種の素子が半田付けされてエレクトロデバイス用の印刷回路が形成されている。
【0003】
このような印刷回路に使用する銅箔は、その製造方法の種類の違いにより電解銅箔及び圧延銅箔に大別されるが、いずれも印刷回路板の種類や品質要求に応じて使用されている。
これらの銅箔は、樹脂基材と接着される面と非接着面があり、それぞれ特殊な表面処理(トリート処理)が施されている。また、多層プリント配線板の内層に使用する銅箔のように両面に樹脂との接着機能をもつようにされる(ダブルトリート処理)場合もある。
電解銅箔は一般に回転ドラムに銅を電着させ、それを連続的に剥がして銅箔を製造しているが、この製造時点で回転ドラムに接触する面は光沢面で、その反対側の面は多数の凹凸を有している(粗面)。しかし、このような粗面でも樹脂基板との接着性を一層向上させるために、0.2〜3μm程度の銅粒子を付着させるのが一般的である。
さらに、このような凹凸を増強した上に銅粒子の脱落を防止するために薄いめっき層を形成する場合もある。これらの一連の工程を粗化処理と呼んでいる。このような粗化処理は、電解銅箔に限らず圧延銅箔でも要求されることであり、同様な粗化処理が圧延銅箔においても実施されている。
【0004】
以上のような銅箔を使用してホットプレス法や連続法により銅張り積層板が製造される。この積層板は、例えばホットプレス法を例にとると、エポキシ樹脂の合成、紙基材へのフェノール樹脂の含浸、乾燥を行ってプリプレグを製造し、さらにこのプリプレグと銅箔を組合せプレス機により熱圧成形を行う等の工程を経て製造されている。
このようにして製造された銅張り積層板は、目的とする回路を形成するためにレジスト塗布及び露光工程により回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を経るが、ここで大きな問題が発生した。
【0005】
それは、図2に示すようにエッチング後の銅箔回路の銅部分2が末広がりにエッチングされる(ダレを発生する)ことである。図2において符号3はレジスト、符号4は樹脂基板を示す。エッチングが十分でなく、このようなダレが発生した場合には、樹脂基板近傍で銅回路が短絡し不良品となる場合もある。
このような末広がりのエッチング不良を防止するために、図3に示すようにエッチング時間を延長してエッチングをより高める方法を採用した。
しかし、この場合は図3の符号5に示すように、銅回路の側面が極端に狭くなり、回路設計上目的とする均一な線幅(回路幅)が得られず、特にその部分(細線化された部分)で発熱し、場合によっては断線するという問題が発生した。
最近では電子回路のファインパターン化が要求されているが、このようなエッチング不良による問題がより強く現れ、回路形成上大きな問題となっている。
【0006】
【発明が解決しようとする課題】
本発明は、銅張り積層板の銅箔をエッチングにより回路形成を行うに際し、エッチングによるダレを防止し、目的とする回路幅の均一な回路を形成できる電子回路用銅箔及びそのための電子回路の形成方法を課題とする。
【0007】
【課題を解決するための手段】
本発明者らは、銅箔の厚み方向のエッチング速度を制御することにより、ダレのない回路幅の均一な回路を形成できるとの知見を得た。
本発明はこの知見に基づいて、
1 エッチングにより回路形成を行う電子回路用銅箔において、エッチング面側に銅よりエッチングレートの遅い金属又は合金層を形成したことを特徴とする電子回路用銅箔
2 銅張り積層板であることを特徴とする上記1記載の電子回路用銅箔
3 銅よりエッチングレートの遅い金属又は合金層がコバルト、ニッケル又はこれらの合金層であることを特徴とする上記1又は2記載の電子回路用銅箔
4 100〜10000μg/dm2の金属又は合金層を形成することを特徴とする上記1〜3記載の電子回路用銅箔
5 銅箔のエッチング側面の傾斜角度が、80〜95度の範囲にあることを特徴とする上記1〜4のそれぞれに記載の電子回路用銅箔
6 銅箔のエッチング側面の傾斜角度が、85〜90度の範囲にあることを特徴とする上記1〜4のそれぞれに記載の電子回路用銅箔
を提供する。
【0008】
さらに、また
7 銅張り積層板の銅箔をエッチングし電子回路を形成する方法において、銅箔のエッチング面側に銅よりエッチングレートの遅い金属又は合金層を形成した後、塩化第二銅水溶液を用いて該銅箔をエッチングし、回路を形成することを特徴とする電子回路の形成方法
8 銅よりエッチングレートの遅い金属又は合金層がコバルト、ニッケル又はこれらの合金層であることを特徴とする上記7記載の電子回路の形成方法
9 100〜10000μg/dm2の金属又は合金層を形成することを特徴とする上記7又は8記載の電子回路の形成方法
10 銅箔のエッチング側面の傾斜角度が、80〜95度の範囲にあることを特徴とする上記7〜9のそれぞれに記載の電子回路の形成方法
11 銅箔のエッチング側面の傾斜角度が、85〜90度の範囲にあることを特徴とする上記7〜9のそれぞれに記載の電子回路の形成方法
を提供するものである。
【0009】
【発明の実施の形態】
本発明は、エッチングにより回路形成を行う電子回路用銅箔のエッチング面側に、銅よりエッチングレートの遅い金属又は合金層層を形成し、銅張り積層板とする。この銅箔は、電解銅箔及び圧延銅箔のいずれにも適用できる。また、粗化面(M面)又は光沢面(S面)にも同様に適用できる。
圧延銅箔の中には高純度銅箔又は強度を向上させた合金銅箔も存在するが、本件発明はこれらの銅箔の全てを包含する。
銅よりエッチングレートの遅い金属又は合金層を形成する材料としては、コバルト、ニッケル又はこれらの合金が使用できるが、特にコバルト、ニッケル又はこれらの合金が好適である。合金層としては、Co−P、Ni−P、Co−Ni、Co−Zn、Ni−Znが使用できる。
【0010】
コバルト又はニッケル等のエッチングを抑制する金属又は合金は、図1の符号1示すように銅箔1上のレジスト部分3に近い位置にあり、レジスト3側の銅箔1のエッチング速度は、このコバルト、ニッケル等の層7により抑制され、逆にコバルト、ニッケル等の層から遠ざかるに従いエッチングは通常の速度で進行する。
これによって、銅回路の側面6のレジスト3側から樹脂基板4側に向かってほぼ垂直にエッチングが進行し、矩形の銅箔回路が形成される。
【0011】
コバルト又はニッケル等の銅よりエッチングレートの遅い金属又は合金層の厚さは、100〜10000μg/dm2とするのが良い。100μg/dm2未満であると、銅箔の厚み方向のエッチング速度を効果的に制御することができず、ダレのない回路幅の均一な回路を形成することが難しくなる。また、10000μg/dm2を超えると、レジスト側のエッチングが抑制され過ぎて銅箔回路のエッチング部がいびつになるので好ましくない。
【0012】
下記に好適なめっき条件の例を示す。
(コバルトめっき)
Co:1〜20g/L
pH:1〜4
温度:常温〜60°C
電流密度Dk:1〜15A/dm2
時間:1〜10秒
(ニッケルめっき)
Ni:1〜20g/L
pH:1〜4
温度:常温〜60°C
電流密度Dk:1〜15A/dm2
時間:1〜10秒
(Co−Ni合金めっき)
Co:1〜20g/L
Ni:1〜20g/L
温度:常温〜60°C
電流密度Dk:1〜15A/dm2
時間:1〜10秒
【0013】
銅張り積層板の銅箔のエッチングに際しては、銅箔のエッチング面側に銅よりエッチングレートの遅い金属又は合金層層を形成した後、塩化第二銅水溶液を用いて該銅箔をエッチングする。
上記の条件でエッチングすることにより、銅箔回路のエッチング側面と樹脂基板との間の傾斜角度が80〜95度の範囲にすることができる。特に望ましい傾斜角度は85〜90度の範囲である。これによって、ダレのない矩形のエッチング回路が形成できる。
【0014】
【実施例及び比較例】
次に、本発明の実施例について説明する。なお、本実施例はあくまで1例であり、この例に制限されるものではない。すなわち、本発明の技術思想の範囲内で、実施例以外の態様あるいは変形を全て包含するものである。
【0015】
(実施例1)
12μm電解銅箔の光沢(S)面に、コバルトめっきを施した。
めっき条件は次の通りである。
Co:10g/L
pH:2.5
温度:50°C
電流密度Dk:5A/dm2
時間:2秒
このコバルトめっき層の厚さは2500μg/dm2であった。
このコバルトめっき層を設けた銅箔をエッチング側とし、樹脂基板に接着して銅張り積層板とした。その後、レジスト塗布及び露光工程により10本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を実施した。
エッチング液は塩化第二銅水溶液を用いた。エッチング条件は次の通りである。
水溶液組成:CuCl2、CuO、HCl(3.5M/L)
S.G.(比重):1.26
温度:50°C
搬送スピード:0.77m/min(槽長770mm)
上面回路幅:0.222mm
これによって、図1に示すように銅回路の側面6のレジスト3側から樹脂基板4側に向かってほぼ垂直にエッチングが進行し、矩形の銅箔回路が形成された。
次に、エッチングした銅箔の傾斜角度を測定した(なお、この測定値は、エッチング回路10の平均値である)。その結果左傾斜角91.8度であり、右傾斜角89.4°であり、ほぼ矩形の銅箔回路が形成され、極めて良好なエッチング回路が得られた。
【0016】
(実施例2)
12μm電解銅箔の粗化(M)面に、ニッケルめっきを施した。
めっき条件は次の通りである。
Ni:10g/L
pH:2.5
温度:50°C
電流密度Dk:5A/dm2
時間:8秒
このコバルトめっき層の厚さは6600μg/dm2であった。
このコバルトめっき層を設けた銅箔をエッチング側として樹脂基板に接着し、銅張り積層板とした。その後、レジスト塗布及び露光工程により10本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を実施した。
エッチング液は塩化第二銅水溶液を用いた。エッチング条件は次の通りである。
水溶液組成:CuCl2、CuO、HCl(3.5M/L)
S.G.(比重):1.26
温度:50°C
搬送スピード:0.77m/min(槽長770mm)
上面回路幅:0.232mm
これによって、図1に示すように銅回路の側面6のレジスト3側から樹脂基板4側に向かってほぼ垂直にエッチングが進行し、矩形の銅箔回路が形成された。
次に、エッチングした銅箔の傾斜角度を測定した(なお、この測定値は、エッチング回路10の平均値である)。その結果左傾斜角81.5度であり、右傾斜角82.5°であり、図1に示すような、ほぼ矩形の銅箔回路が形成され、良好なエッチング回路が得られた。
【0017】
(比較例1)
12μm電解銅箔の光沢(S)面に、コバルトめっきを施した。
めっき条件は次の通りである。
Co:10g/L
pH:2.5
温度:50°C
電流密度Dk:5A/dm2
時間:14秒
このコバルトめっき層の厚さは13000μg/dm2であった。
このコバルトめっき層を設けた銅箔をエッチング面側として樹脂基板に接着し、エッチング側とし、銅張り積層板とした。その後、レジスト塗布及び露光工程により10本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を実施した。
エッチング液は塩化第二銅水溶液を用いた。エッチング条件は次の通りである。
水溶液組成:CuCl2、CuO、HCl(3.5M/L)
S.G.(比重):1.26
温度:50°C
搬送スピード:0.77m/min(槽長770mm)
上面回路幅:0.220mm
次に、エッチングした銅箔の傾斜角度を測定した(なお、この測定値は、エッチング回路10の平均値である)。その結果左傾斜角101.3度であり、右傾斜角108.0°であり、図3に示すような、レジスト側に比べて樹脂基板側が過度にエッチングされ、逆台形状の銅箔回路が形成され、エッチング不良の回路が形成された。
【0018】
(比較例2)
12μm電解銅箔を粗化(M)面側をエッチング面として、樹脂基板に接着して銅張り積層板とした後、レジスト塗布及び露光工程により10本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を実施した。
エッチング液は塩化第二銅水溶液を用いた。エッチング条件は次の通りである。
水溶液組成:CuCl2、CuO、HCl(3.5M/L)
S.G.(比重):1.26
温度:50°C
搬送スピード:0.77m/min(槽長770mm)
上面回路幅:0.233mm
次に、エッチングした銅箔の傾斜角度を測定した(なお、この測定値は、エッチング回路10の平均値である)。その結果、左傾斜角73.5度であり、右傾斜角76.3°であり、図2に示すような、ダレが大きく台形状の銅箔回路が形成され、エッチング不良であった。
【0019】
以上の結果を表1に示す。
表1から明らかなように、100〜10000μg/dm2の範囲にあるコバルトめっき及びニッケルめっきは、ほぼ矩形の銅箔回路が形成され、極めて良好なエッチング回路が得られた。特にコバルトめっき層は少量でも優れたエッチング性が得られた。
これに対して、めっき層を設けていないものは、ダレが大きく台形状の銅箔回路が形成され、エッチング不良であった。また、逆にめっき層が多すぎると、レジスト側に比べて樹脂基板側が過度にエッチングされ、逆台形状の銅箔回路が形成されて、エッチング不良の回路が形成された。
以上の実施例及び比較例以外に、多くの実験を繰り返し行ったところ、100〜10000μg/dm2の金属又は合金層を形成することが望ましいことが分かった。
実施例では、コバルト層及びニッケル層を形成した場合について説明したが、これらの合金層でも同様な効果があることを確認した。しかし、合金めっきに比べ,コバルトめっき及びニッケルめっきの単独層はめっき液及びめっき条件の管理が容易なので、めっき処理操作上より効果的である。
【0020】
【表1】
【0021】
【発明の効果】
本発明は、銅張り積層板の銅箔をエッチングにより回路形成を行うに際し、銅箔の厚み方向のエッチング速度を制御することにより、ダレのない回路幅の均一な回路を形成できるという優れた効果を有する。
【図面の簡単な説明】
【図1】本発明の実施例で得られた良好な矩形の銅箔回路が形成された様子を示す説明図である。
【図2】比較例2に示すようなダレが大きく、台形状の不良な銅箔回路が形成された様子を示す説明図である。
【図3】エッチング速度を高めた例であり、エッチングが強すぎて銅箔回路が細くなり、不良な回路が形成された様子を示す説明図である。
【符号の説明】
1 銅箔
2 ダレが発生した銅箔エッチング面
3 レジスト
4 樹脂基板
5 過度にエッチングされた銅箔エッチング面
6 基板に対してほぼ垂直である銅箔エッチング面
7 コバルト又はニッケル等の金属又は合金層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a copper foil for electronic circuits for forming a circuit by etching and a method for forming an electronic circuit.
[0002]
[Prior art]
Copper foil for printed circuits is widely used in electronic and electrical equipment, but this copper foil for printed circuits is generally used with a base material such as a synthetic resin board or film with an adhesive or without an adhesive. A copper-clad laminate is produced by bonding under high temperature and high pressure, and then a circuit is printed by a resist coating and exposure process to form the desired circuit, followed by an etching process that removes unnecessary portions of the copper foil. Furthermore, various elements are soldered to form a printed circuit for an electro device.
[0003]
Copper foils used in such printed circuits are broadly divided into electrolytic copper foils and rolled copper foils depending on the type of manufacturing method, both of which are used according to the types of printed circuit boards and quality requirements. Yes.
These copper foils have a surface to be bonded to the resin base material and a non-bonded surface, and are each subjected to a special surface treatment (treating treatment). In some cases, the copper foil used for the inner layer of the multilayer printed wiring board has a function of adhering to the resin on both sides (double treatment).
In general, electrolytic copper foil is produced by electrodepositing copper onto a rotating drum and continuously peeling it to produce a copper foil. At this time, the surface that contacts the rotating drum is a glossy surface and the opposite surface. Has many irregularities (rough surface). However, in order to further improve the adhesion to the resin substrate even on such a rough surface, it is common to deposit copper particles of about 0.2 to 3 μm.
Furthermore, a thin plating layer may be formed in order to prevent such copper particles from falling off while enhancing such unevenness. A series of these steps is called roughening treatment. Such a roughening treatment is required not only for the electrolytic copper foil but also for the rolled copper foil, and the same roughening treatment is also carried out for the rolled copper foil.
[0004]
Using the copper foil as described above, a copper-clad laminate is produced by a hot press method or a continuous method. For example, taking the hot press method as an example, this laminated plate is produced by synthesize epoxy resin, impregnate paper substrate with phenol resin, and dry it to produce a prepreg, and further combine this prepreg and copper foil with a combination press. It is manufactured through processes such as hot pressing.
The copper-clad laminate thus manufactured is printed with a resist coating and exposure process to form a desired circuit, and further undergoes an etching process to remove unnecessary portions of the copper foil. A big problem occurred.
[0005]
That is, as shown in FIG. 2, the
In order to prevent such a widening etching failure, a method of increasing the etching time by extending the etching time as shown in FIG. 3 was adopted.
However, in this case, as shown by reference numeral 5 in FIG. 3, the side surface of the copper circuit becomes extremely narrow, and a uniform line width (circuit width) intended for circuit design cannot be obtained. Generated heat), and in some cases, there was a problem of disconnection.
Recently, there is a demand for fine patterning of electronic circuits. However, problems caused by such defective etching appear more strongly, which is a serious problem in circuit formation.
[0006]
[Problems to be solved by the invention]
The present invention provides a copper foil for an electronic circuit capable of preventing sagging due to etching and forming a circuit having a uniform circuit width when a circuit is formed by etching a copper foil of a copper-clad laminate, and an electronic circuit for the same The forming method is an issue.
[0007]
[Means for Solving the Problems]
The present inventors have obtained the knowledge that a uniform circuit having a sagging circuit width can be formed by controlling the etching rate in the thickness direction of the copper foil.
The present invention is based on this finding,
1. A copper foil for electronic circuits that forms a circuit by etching, wherein a metal or alloy layer having a slower etching rate than copper is formed on the etched surface side. 3. The copper foil for electronic circuits according to 1 or 2 above, wherein the metal or alloy layer having a slower etching rate than copper is cobalt, nickel or an alloy layer thereof. (4) The copper foil for electronic circuits as described in (1) to (3) above, wherein a metal or alloy layer of 100 to 10,000 μg / dm 2 is formed, and the inclination angle of the etching side surface of the copper foil is in the range of 80 to 95 degrees. The copper foil for
[0008]
Furthermore, in the method of forming an electronic circuit by etching a copper foil of a copper-clad laminate, a metal or alloy layer having a slower etching rate than copper is formed on the etched surface side of the copper foil, and then an aqueous cupric chloride solution is added. A method of forming an electronic circuit, wherein the copper foil is etched to form a circuit, wherein the metal or alloy layer having a slower etching rate than copper is cobalt, nickel or an alloy layer thereof. 9. The electronic circuit forming method according to 7 above, wherein the metal or alloy layer of 100 to 10000 μg / dm 2 is formed. 10. The electronic circuit forming method according to 7 or 8 above, wherein the inclination angle of the etching side surface of the copper foil is The method of forming an electronic circuit according to each of 7 to 9 above, wherein the inclination angle of the etching side surface of the copper foil is 85 to 85 degrees. Characterized in that in the range of 0 ° is to provide a method for forming an electronic circuit according to each of the above 7-9.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, a metal or alloy layer layer having an etching rate slower than that of copper is formed on the etching surface side of a copper foil for electronic circuits where a circuit is formed by etching to obtain a copper-clad laminate. This copper foil can be applied to both electrolytic copper foil and rolled copper foil. Further, the present invention can be similarly applied to a roughened surface (M surface) or a glossy surface (S surface).
Among the rolled copper foils, there are high-purity copper foils or alloy copper foils with improved strength, but the present invention encompasses all these copper foils.
As a material for forming a metal or alloy layer having a slower etching rate than copper, cobalt, nickel, or an alloy thereof can be used, but cobalt, nickel, or an alloy thereof is particularly preferable. As the alloy layer, Co—P, Ni—P, Co—Ni, Co—Zn, or Ni—Zn can be used.
[0010]
The metal or alloy that suppresses etching such as cobalt or nickel is located near the
As a result, etching proceeds substantially perpendicularly from the resist 3 side of the
[0011]
The thickness of the metal or alloy layer whose etching rate is slower than that of copper such as cobalt or nickel is preferably 100 to 10,000 μg / dm 2 . If it is less than 100 μg / dm 2 , the etching rate in the thickness direction of the copper foil cannot be controlled effectively, and it becomes difficult to form a uniform circuit with no circuit sagging. On the other hand, if it exceeds 10,000 μg / dm 2 , etching on the resist side is excessively suppressed and the etched portion of the copper foil circuit becomes distorted.
[0012]
Examples of suitable plating conditions are shown below.
(Cobalt plating)
Co: 1-20 g / L
pH: 1-4
Temperature: normal temperature to 60 ° C
Current density Dk: 1 to 15 A / dm 2
Time: 1-10 seconds (nickel plating)
Ni: 1 to 20 g / L
pH: 1-4
Temperature: normal temperature to 60 ° C
Current density Dk: 1 to 15 A / dm 2
Time: 1-10 seconds (Co-Ni alloy plating)
Co: 1-20 g / L
Ni: 1 to 20 g / L
Temperature: normal temperature to 60 ° C
Current density Dk: 1 to 15 A / dm 2
Time: 1-10 seconds [0013]
In etching the copper foil of the copper-clad laminate, a metal or alloy layer layer having a slower etching rate than copper is formed on the etching surface side of the copper foil, and then the copper foil is etched using a cupric chloride aqueous solution.
By etching under the above conditions, the inclination angle between the etching side surface of the copper foil circuit and the resin substrate can be in the range of 80 to 95 degrees. A particularly desirable inclination angle is in the range of 85 to 90 degrees. Thereby, a rectangular etching circuit without sagging can be formed.
[0014]
[Examples and Comparative Examples]
Next, examples of the present invention will be described. In addition, a present Example is an example to the last, and is not restrict | limited to this example. That is, all aspects or modifications other than the embodiments are included within the scope of the technical idea of the present invention.
[0015]
Example 1
Cobalt plating was performed on the gloss (S) surface of the 12 μm electrolytic copper foil.
The plating conditions are as follows.
Co: 10 g / L
pH: 2.5
Temperature: 50 ° C
Current density Dk: 5 A / dm 2
Time: 2 seconds The thickness of this cobalt plating layer was 2500 μg / dm 2 .
The copper foil provided with this cobalt plating layer was used as the etching side, and was bonded to a resin substrate to obtain a copper-clad laminate. Then, 10 circuits were printed by the resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed.
An aqueous solution of cupric chloride was used as the etching solution. Etching conditions are as follows.
Aqueous solution composition: CuCl 2 , CuO, HCl (3.5 M / L)
S. G. (Specific gravity): 1.26
Temperature: 50 ° C
Conveying speed: 0.77m / min (tank length 770mm)
Top circuit width: 0.222 mm
As a result, as shown in FIG. 1, the etching progressed almost vertically from the resist 3 side to the
Next, the tilt angle of the etched copper foil was measured (note that this measured value is an average value of the etching circuit 10). As a result, the left inclination angle was 91.8 degrees, the right inclination angle was 89.4 °, and a substantially rectangular copper foil circuit was formed, and an extremely good etching circuit was obtained.
[0016]
(Example 2)
Nickel plating was applied to the roughened (M) surface of the 12 μm electrolytic copper foil.
The plating conditions are as follows.
Ni: 10 g / L
pH: 2.5
Temperature: 50 ° C
Current density Dk: 5 A / dm 2
Time: 8 seconds The thickness of this cobalt plating layer was 6600 μg / dm 2 .
The copper foil provided with this cobalt plating layer was bonded to the resin substrate as the etching side to obtain a copper-clad laminate. Then, 10 circuits were printed by the resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed.
An aqueous solution of cupric chloride was used as the etching solution. Etching conditions are as follows.
Aqueous solution composition: CuCl 2 , CuO, HCl (3.5 M / L)
S. G. (Specific gravity): 1.26
Temperature: 50 ° C
Conveying speed: 0.77m / min (tank length 770mm)
Top circuit width: 0.232 mm
As a result, as shown in FIG. 1, the etching progressed almost vertically from the resist 3 side to the
Next, the tilt angle of the etched copper foil was measured (note that this measured value is an average value of the etching circuit 10). As a result, the left inclination angle was 81.5 degrees and the right inclination angle was 82.5 degrees. As shown in FIG. 1, a substantially rectangular copper foil circuit was formed, and a good etching circuit was obtained.
[0017]
(Comparative Example 1)
Cobalt plating was performed on the gloss (S) surface of the 12 μm electrolytic copper foil.
The plating conditions are as follows.
Co: 10 g / L
pH: 2.5
Temperature: 50 ° C
Current density Dk: 5 A / dm 2
Time: 14 seconds The thickness of this cobalt plating layer was 13000 μg / dm 2 .
The copper foil provided with the cobalt plating layer was adhered to the resin substrate as the etching surface side, and the etching side was used as a copper-clad laminate. Then, 10 circuits were printed by the resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed.
An aqueous solution of cupric chloride was used as the etching solution. Etching conditions are as follows.
Aqueous solution composition: CuCl 2 , CuO, HCl (3.5 M / L)
S. G. (Specific gravity): 1.26
Temperature: 50 ° C
Conveying speed: 0.77m / min (tank length 770mm)
Top circuit width: 0.220 mm
Next, the tilt angle of the etched copper foil was measured (note that this measured value is an average value of the etching circuit 10). As a result, the left tilt angle is 101.3 degrees, the right tilt angle is 108.0 °, and the resin substrate side is excessively etched compared to the resist side as shown in FIG. As a result, a circuit with poor etching was formed.
[0018]
(Comparative Example 2)
After roughening (M) surface of 12μm electrolytic copper foil as an etching surface, it is bonded to a resin substrate to form a copper-clad laminate, and then 10 circuits are printed by resist coating and exposure processes, and no copper foil is required. An etching process for removing the portion was performed.
An aqueous solution of cupric chloride was used as the etching solution. Etching conditions are as follows.
Aqueous solution composition: CuCl 2 , CuO, HCl (3.5 M / L)
S. G. (Specific gravity): 1.26
Temperature: 50 ° C
Conveying speed: 0.77m / min (tank length 770mm)
Top circuit width: 0.233 mm
Next, the tilt angle of the etched copper foil was measured (note that this measured value is an average value of the etching circuit 10). As a result, the left tilt angle was 73.5 degrees, the right tilt angle was 76.3 °, a trapezoidal copper foil circuit having a large sag as shown in FIG. 2 was formed, and the etching was defective.
[0019]
The results are shown in Table 1.
As is apparent from Table 1, cobalt plating and nickel plating in the range of 100 to 10000 μg / dm 2 formed a substantially rectangular copper foil circuit, and an extremely good etching circuit was obtained. In particular, excellent etching properties were obtained even with a small amount of the cobalt plating layer.
On the other hand, when the plating layer was not provided, the sagging was large and a trapezoidal copper foil circuit was formed, resulting in poor etching. On the other hand, when there are too many plating layers, the resin substrate side is excessively etched as compared with the resist side, an inverted trapezoidal copper foil circuit is formed, and a circuit with poor etching is formed.
When many experiments were repeated in addition to the above examples and comparative examples, it was found that it is desirable to form a metal or alloy layer of 100 to 10000 μg / dm 2 .
In the examples, the case where the cobalt layer and the nickel layer are formed has been described, but it was confirmed that these alloy layers have the same effect. However, compared to alloy plating, a single layer of cobalt plating and nickel plating is more effective in plating processing operations because it is easier to manage the plating solution and plating conditions.
[0020]
[Table 1]
[0021]
【The invention's effect】
The present invention, when performing circuit formation by etching the copper foil of the copper-clad laminate, by controlling the etching rate in the thickness direction of the copper foil, it is possible to form a uniform circuit with a uniform circuit width without sagging Have
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a state in which a good rectangular copper foil circuit obtained in an example of the present invention is formed.
FIG. 2 is an explanatory diagram showing a state in which a copper foil circuit having a large sagging and a bad trapezoidal shape as shown in Comparative Example 2 is formed.
FIG. 3 is an example in which an etching rate is increased, and is an explanatory view showing a state in which a defective circuit is formed because etching is too strong and a copper foil circuit is thinned.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000369753A JP4592936B2 (en) | 2000-12-05 | 2000-12-05 | Copper foil for electronic circuit and method for forming electronic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000369753A JP4592936B2 (en) | 2000-12-05 | 2000-12-05 | Copper foil for electronic circuit and method for forming electronic circuit |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010131709A Division JP5043154B2 (en) | 2010-06-09 | 2010-06-09 | Copper foil for electronic circuit and method for forming electronic circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2002176242A JP2002176242A (en) | 2002-06-21 |
JP2002176242A5 JP2002176242A5 (en) | 2009-08-27 |
JP4592936B2 true JP4592936B2 (en) | 2010-12-08 |
Family
ID=18839747
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000369753A Expired - Lifetime JP4592936B2 (en) | 2000-12-05 | 2000-12-05 | Copper foil for electronic circuit and method for forming electronic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4592936B2 (en) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003051673A (en) * | 2001-08-06 | 2003-02-21 | Mitsui Mining & Smelting Co Ltd | Printed wiring board copper foil and copper-plated laminated board using the same |
JP4941204B2 (en) * | 2007-09-27 | 2012-05-30 | 日立電線株式会社 | Copper foil for printed wiring board and surface treatment method thereof |
US8357307B2 (en) | 2008-12-26 | 2013-01-22 | Jx Nippon Mining & Metals Corporation | Method of forming electronic circuit |
MY152533A (en) * | 2008-12-26 | 2014-10-15 | Jx Nippon Mining & Metals Corp | Rolled copper foil or electrolytic copper foil for electronic circuit, and method of forming electronic circuit using same |
MY148764A (en) | 2008-12-26 | 2013-05-31 | Jx Nippon Mining & Metals Corp | Rolled copper foil or electrolytic copper foil for electronic circuit, and method of forming electronic circuit using same |
JP4955105B2 (en) | 2008-12-26 | 2012-06-20 | Jx日鉱日石金属株式会社 | Rolled copper foil or electrolytic copper foil for electronic circuit and method for forming electronic circuit using these |
WO2010087268A1 (en) | 2009-01-29 | 2010-08-05 | 日鉱金属株式会社 | Rolled copper foil or electrolytic copper foil for electronic circuit, and method for forming electronic circuit using same |
WO2010147059A1 (en) * | 2009-06-18 | 2010-12-23 | Jx日鉱日石金属株式会社 | Electronic circuit, method for forming same, and copper-clad laminate for electronic circuit formation |
US20120318568A1 (en) | 2010-01-15 | 2012-12-20 | Jx Nippon Mining & Metals Corporation | Electronic circuit, method for forming same, and copper clad laminate for forming electronic circuit |
JP5367613B2 (en) * | 2010-02-12 | 2013-12-11 | Jx日鉱日石金属株式会社 | Copper foil for printed wiring boards |
JP5406099B2 (en) * | 2010-03-30 | 2014-02-05 | Jx日鉱日石金属株式会社 | Copper foil and laminate for printed wiring board with excellent etching properties |
JP5232823B2 (en) * | 2010-03-30 | 2013-07-10 | Jx日鉱日石金属株式会社 | Copper foil for printed wiring board excellent in etching property and laminate using the same |
JP5702942B2 (en) * | 2010-03-30 | 2015-04-15 | Jx日鉱日石金属株式会社 | Copper foil for printed wiring board excellent in etching property and laminate using the same |
WO2011121803A1 (en) * | 2010-03-30 | 2011-10-06 | Jx日鉱日石金属株式会社 | Copper foil for printed wiring board having excellent thermal discoloration resistance and etching properties, and laminate using same |
JP5312412B2 (en) | 2010-08-06 | 2013-10-09 | 三洋電機株式会社 | Content playback device |
US20130256006A1 (en) | 2010-11-12 | 2013-10-03 | Jx Nippon Mining & Metals Corporation | Method for Forming Circuit on Flexible Laminate Substrate |
JP5558437B2 (en) * | 2011-08-24 | 2014-07-23 | Jx日鉱日石金属株式会社 | Copper foil for printed wiring board and laminated board using the same |
TWI576024B (en) * | 2011-09-30 | 2017-03-21 | Jx Nippon Mining & Metals Corp | Printed wiring board with copper foil and the use of its laminated board |
JP6111017B2 (en) | 2012-02-03 | 2017-04-05 | Jx金属株式会社 | Copper foil for printed wiring board, laminate using the same, printed wiring board, and electronic component |
WO2014136763A1 (en) * | 2013-03-05 | 2014-09-12 | 三井金属鉱業株式会社 | Copper foil for laser processing, carrier-foil-supported copper foil for laser processing, copper-clad laminate, and process for producing printed wiring board |
WO2016093799A1 (en) | 2014-12-09 | 2016-06-16 | Intel Corporation | Microelectronic substrates having copper alloy conductive route structures |
TWI593548B (en) | 2015-01-09 | 2017-08-01 | Jx Nippon Mining & Metals Corp | Attached to the metal substrate |
CN105018985B (en) * | 2015-08-10 | 2018-07-31 | 灵宝华鑫铜箔有限责任公司 | A kind of process of surface treatment reducing electrolytic copper foil side etching phenomenon |
JP7183582B2 (en) * | 2018-06-19 | 2022-12-06 | 凸版印刷株式会社 | glass wiring board |
CN109788654A (en) * | 2018-12-17 | 2019-05-21 | 盐城维信电子有限公司 | A kind of production method for the flexible circuit board improving etching factor |
WO2022201563A1 (en) | 2021-03-25 | 2022-09-29 | ナミックス株式会社 | Laminate for wiring board |
JPWO2022202921A1 (en) | 2021-03-25 | 2022-09-29 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0681172A (en) * | 1992-09-01 | 1994-03-22 | Hitachi Cable Ltd | Formation of fine pattern |
JPH07297544A (en) * | 1994-04-21 | 1995-11-10 | Hitachi Chem Co Ltd | Manufacture of printed wiring board |
JP2000269619A (en) * | 1999-03-16 | 2000-09-29 | Reiko Co Ltd | Data communication antenna circuit board and film for manufacturing the same |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04284690A (en) * | 1991-03-13 | 1992-10-09 | Furukawa Saakitsuto Foil Kk | Copper foil for inner layer circuit of multilayer printed circuit board and manufacture thereof |
-
2000
- 2000-12-05 JP JP2000369753A patent/JP4592936B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0681172A (en) * | 1992-09-01 | 1994-03-22 | Hitachi Cable Ltd | Formation of fine pattern |
JPH07297544A (en) * | 1994-04-21 | 1995-11-10 | Hitachi Chem Co Ltd | Manufacture of printed wiring board |
JP2000269619A (en) * | 1999-03-16 | 2000-09-29 | Reiko Co Ltd | Data communication antenna circuit board and film for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JP2002176242A (en) | 2002-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4592936B2 (en) | Copper foil for electronic circuit and method for forming electronic circuit | |
JP6111017B2 (en) | Copper foil for printed wiring board, laminate using the same, printed wiring board, and electronic component | |
JP2005161840A (en) | Ultra-thin copper foil with carrier and printed circuit | |
JP2002506121A (en) | Electrolytic copper foil with improved glossy surface | |
WO2010074054A1 (en) | Method for forming electronic circuit | |
JP5738964B2 (en) | Electronic circuit, method for forming the same, and copper-clad laminate for forming electronic circuit | |
JP2011171621A (en) | Copper foil with resistor layer and copper clad laminate including the same, and method of manufacturing the copper clad laminate | |
WO2014046256A1 (en) | Metallic foil having carrier | |
JP5043154B2 (en) | Copper foil for electronic circuit and method for forming electronic circuit | |
KR20130023519A (en) | Flexible cupper clad laminated film for semi-additive and manufacturing method the same | |
JP5156784B2 (en) | Copper foil for printed wiring board and laminate using the same | |
JP5542715B2 (en) | Copper foil for printed wiring board, laminate and printed wiring board | |
JP5506497B2 (en) | Copper foil for printed wiring board for forming circuit with excellent electric transmission characteristics and laminate using the same | |
JP5816045B2 (en) | Copper foil for printed wiring board excellent in productivity and laminated board using the same | |
JP2012146933A (en) | Method of forming circuit board for printed wiring board | |
JP2011210993A (en) | Copper foil for printed wiring board and layered body which have superior etching property | |
JP5524671B2 (en) | Copper foil and laminate for printed wiring board with excellent etching properties | |
JPH08290524A (en) | Copper clad laminate | |
JP5079883B2 (en) | Copper foil for printed wiring board excellent in heat discoloration resistance and etching property, and laminate using the same | |
JP2013028823A (en) | Laminate and printed wiring board using the same | |
JP2011210998A (en) | Copper foil for printed wiring board and layered body which have superior heating discoloration resistance and etching property | |
JP2005203621A (en) | Metal composite sheet for printed wiring board and printed wiring board using it | |
JP2011210991A (en) | Copper foil for printed wiring board and layered body which have superior etching property | |
JP2011253854A (en) | Formation method of circuit board for printed wiring board | |
JP2011210986A (en) | Copper foil for printed wiring board and layered body which have superior heating discoloration resistance and etching property |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071116 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090709 |
|
A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20090709 |
|
A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20090811 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090818 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091117 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100115 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100115 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100316 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100609 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20100628 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100727 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100804 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100804 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100813 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100914 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100915 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130924 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4592936 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130924 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |