JP5156784B2 - Copper foil for printed wiring board and laminate using the same - Google Patents

Copper foil for printed wiring board and laminate using the same Download PDF

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JP5156784B2
JP5156784B2 JP2010077964A JP2010077964A JP5156784B2 JP 5156784 B2 JP5156784 B2 JP 5156784B2 JP 2010077964 A JP2010077964 A JP 2010077964A JP 2010077964 A JP2010077964 A JP 2010077964A JP 5156784 B2 JP5156784 B2 JP 5156784B2
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copper foil
copper
printed wiring
etching
coating layer
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JP2011210996A (en
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秀樹 古澤
美里 中願寺
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JX Nippon Mining and Metals Corp
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JX Nippon Mining and Metals Corp
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Priority to JP2010077964A priority Critical patent/JP5156784B2/en
Priority to TW100110724A priority patent/TWI423742B/en
Priority to CN201180016688.7A priority patent/CN102812786B/en
Priority to PCT/JP2011/057892 priority patent/WO2011122643A1/en
Priority to KR1020127027718A priority patent/KR101375426B1/en
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C30/00—Coating with metallic material characterised only by the composition of the metallic material, i.e. not characterised by the coating process
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils

Description

本発明は、プリント配線板用の銅箔及びそれを用いた積層体に関し、特にフレキシブルプリント配線板用の銅箔及びそれを用いた積層体に関する。   The present invention relates to a copper foil for a printed wiring board and a laminate using the same, and more particularly to a copper foil for a flexible printed wiring board and a laminate using the same.

プリント配線板はここ半世紀に亘って大きな進展を遂げ、今日ではほぼすべての電子機器に使用されるまでに至っている。近年の電子機器の小型化、高性能化ニーズの増大に伴い搭載部品の高密度実装化や信号の高周波化が進展し、プリント配線板に対して導体パターンの微細化（ファインピッチ化）や高周波対応等が求められている。   Printed wiring boards have made great progress over the last half century and are now used in almost all electronic devices. In recent years, with the increasing needs for miniaturization and higher performance of electronic devices, higher density mounting of components and higher frequency of signals have progressed, and conductor patterns have become finer (fine pitch) and higher frequency than printed circuit boards. Response is required.

プリント配線板は銅箔に絶縁基板を接着させて積層体とした後に、エッチングにより銅箔面に導体パターンを形成するという工程を経て製造されるのが一般的である。そのため、プリント配線板用の銅箔には良好なエッチング性が要求される。   In general, a printed wiring board is manufactured through a process in which an insulating substrate is bonded to a copper foil to form a laminate, and then a conductor pattern is formed on the copper foil surface by etching. Therefore, good etching properties are required for the copper foil for printed wiring boards.

銅箔は、樹脂との非接着面に表面処理を施さないと、エッチング後の銅箔回路の銅部分が、銅箔の表面から下に向かって、すなわち樹脂層に向かって、末広がりにエッチングされる（ダレを発生する）。通常は、回路側面の角度が小さい「ダレ」となり、特に大きな「ダレ」が発生した場合には、樹脂基板近傍で銅回路が短絡し、不良品となる場合もある。ここで、図４に、銅回路形成時に「ダレ」を生じて樹脂基板近傍で銅回路が短絡した例を示す回路表面の拡大写真を示す。   If the copper foil is not subjected to surface treatment on the non-adhesive surface with the resin, the copper portion of the copper foil circuit after etching is etched away from the surface of the copper foil, that is, toward the resin layer. (Sagging). Normally, the angle on the side of the circuit is “sagging”, and when a particularly large “sagging” occurs, the copper circuit may short-circuit near the resin substrate, resulting in a defective product. Here, FIG. 4 shows an enlarged photograph of the circuit surface showing an example in which “sagging” occurs during copper circuit formation and the copper circuit is short-circuited in the vicinity of the resin substrate.

このような「ダレ」は極力小さくすることが必要であるが、このような末広がりのエッチング不良を防止するために、エッチング時間を延長して、エッチングをより多くして、この「ダレ」を減少させることも考えられる。しかし、この場合は、すでに所定の幅寸法に至っている箇所があると、そこがさらにエッチングされることになるので、その銅箔部分の回路幅がそれだけ狭くなり、回路設計上目的とする均一な線幅（回路幅）が得られず、特にその部分（細線化された部分）で発熱し、場合によっては断線するという問題が発生する。電子回路のファインパターン化がさらに進行する中で、現在もなお、このようなエッチング不良による問題がより強く現れ、回路形成上で、大きな問題となっている。   Such “sag” needs to be reduced as much as possible, but in order to prevent such widening etching failure, the etching time is extended, the etching is increased, and this “sag” is reduced. It is possible to make it. However, in this case, if there is a portion that has already reached the predetermined width dimension, it will be further etched, so that the circuit width of the copper foil portion will be reduced accordingly, and the circuit design will be a uniform target. The line width (circuit width) cannot be obtained, and heat is generated particularly in that portion (thinned portion), and in some cases, there is a problem of disconnection. As the fine patterning of electronic circuits further progresses, the problem due to such etching failure still appears more strongly and still becomes a big problem in circuit formation.

これらを改善する方法として、エッチング面側の銅箔に銅よりもエッチング速度が遅い金属又は合金層を形成した表面処理が特許文献１に開示されている。この場合の金属又は合金としては、Ｎｉ、Ｃｏ及びこれらの合金である。回路設計に際しては、レジスト塗布側、すなわち銅箔の表面からエッチング液が浸透するので、レジスト直下にエッチング速度が遅い金属又は合金層があれば、その近傍の銅箔部分のエッチングが抑制され、他の銅箔部分のエッチングが進行するので、「ダレ」が減少し、より均一な幅の回路が形成できるという効果をもたらすという、従来技術と比較して急峻な回路形成が可能となり、大きな進歩があったと言える。   As a method for improving these, Patent Document 1 discloses a surface treatment in which a metal or alloy layer having an etching rate slower than that of copper is formed on a copper foil on the etching surface side. In this case, the metal or alloy includes Ni, Co, and alloys thereof. In circuit design, the etching solution penetrates from the resist coating side, that is, from the surface of the copper foil, so if there is a metal or alloy layer with a slow etching rate directly under the resist, the etching of the copper foil portion in the vicinity is suppressed. Since the etching of the copper foil portion of the metal film progresses, the “sag” is reduced, and a circuit with a more uniform width can be formed. This makes it possible to form a sharper circuit compared to the prior art, and a great progress has been made. It can be said that there was.

また、特許文献２では、厚さ１０００〜１００００ÅのＣｕ薄膜を形成し、該Ｃｕ薄膜の上に厚さ１０〜３００Åの銅よりもエッチング速度が遅いＮｉ薄膜を形成している。   Further, in Patent Document 2, a Cu thin film having a thickness of 1000 to 10,000 mm is formed, and an Ni thin film having an etching rate slower than that of copper having a thickness of 10 to 300 mm is formed on the Cu thin film.

特開２００２−１７６２４２号公報JP 2002-176242 A 特開２０００−２６９６１９号公報JP 2000-269619 A

近年、回路の微細化、高密度化がさらに進行し、より急峻に傾斜する側面を有する回路が求められている。しかしながら、特許文献１に記載される技術ではこれらには対応できない。   In recent years, further miniaturization and higher density of circuits have progressed, and there is a demand for circuits having side surfaces that are more steeply inclined. However, the technique described in Patent Document 1 cannot cope with these.

また、特許文献１に記載される表面処理層はソフトエッチングにより除去する必要があること、さらには樹脂との非接着面表面処理銅箔は、積層体に加工される工程で、樹脂の貼付け等の高温処理が施される。これは表面処理層の酸化を引き起こし、結果として銅箔のエッチング性は劣化する。   Moreover, it is necessary to remove the surface treatment layer described in Patent Document 1 by soft etching, and furthermore, the non-adhesive surface-treated copper foil with the resin is a process of processing into a laminate, and the application of the resin, etc. High temperature treatment is applied. This causes oxidation of the surface treatment layer, and as a result, the etching property of the copper foil deteriorates.

前者については、エッチング除去の時間をなるべく短縮し、きれいに除去するためには、表面処理層の厚さを極力薄くすることが必要であること、また後者の場合には、熱を受けるために、下地の銅層が酸化され（変色するので、通称「ヤケ」と言われている。）、レジストの塗布性（均一性、密着性）の不良やエッチング時の界面酸化物の過剰エッチングなどにより、パターンエッチングでのエッチング性、ショート、回路パターンの幅の制御性などの不良が発生するという問題があるので、改良が必要か又は他の材料に置換することが要求されている。   As for the former, it is necessary to reduce the thickness of the surface treatment layer as much as possible in order to shorten the etching removal time as much as possible, and to remove it cleanly. In the latter case, in order to receive heat, The underlying copper layer is oxidized (discolored, so it is commonly called “yake”), due to poor resist coatability (uniformity, adhesion), excessive etching of interfacial oxide during etching, etc. There is a problem that defects such as etching property in pattern etching, short circuit, and controllability of the width of the circuit pattern occur, so that improvement is required or replacement with other materials is required.

さらに、特許文献１及び２に記載される表面処理層はＮｉやＣｏを用いて形成されているが、ＮｉやＣｏはその磁性により電子機器に悪影響を及ぼすおそれがある。   Furthermore, although the surface treatment layer described in Patent Documents 1 and 2 is formed using Ni or Co, Ni or Co may adversely affect electronic devices due to its magnetism.

そこで、本発明は、回路パターン形成の際のエッチング性が良好でファインピッチ化に適し、磁性が良好に抑制されたプリント配線板用銅箔及びそれを用いた積層体を提供することを課題とする。   Therefore, the present invention has an object to provide a copper foil for a printed wiring board, which has good etching properties when forming a circuit pattern, is suitable for fine pitch, and has excellent magnetism, and a laminate using the same. To do.

本発明者らは、鋭意検討の結果、銅箔の樹脂との非接着面側に白金、パラジウム、及び、金のいずれか１種以上を含む被覆層を、所定の金属付着量で設けた場合には、回路側面の傾斜角が８０°以上となるような回路を形勢できることを見出した。これにより、近年の回路の微細化、高密度化に十分対応しうる回路を形成することができる。   As a result of intensive studies, the present inventors have provided a coating layer containing any one or more of platinum, palladium, and gold at a predetermined metal adhesion amount on the non-adhesive surface side with the resin of the copper foil. Has found that a circuit having an inclination angle of 80 ° or more on the side surface of the circuit can be formed. As a result, it is possible to form a circuit that can sufficiently cope with the recent miniaturization and high density of circuits.

以上の知見を基礎として完成した本発明は一側面において、銅箔基材と、銅箔基材の表面の少なくとも一部を被覆し、且つ、白金、パラジウム、及び、金のいずれか１種以上を含む被覆層とを備え、被覆層における白金の付着量が１０５０μｇ／ｄｍ2以下、パラジウムの付着量が６００μｇ／ｄｍ2以下、金の付着量が１０００μｇ／ｄｍ2以下であるプリント配線板用銅箔である。 In one aspect, the present invention completed on the basis of the above knowledge covers at least a part of the surface of the copper foil base material and the copper foil base material, and any one or more of platinum, palladium, and gold and a coating layer comprising a deposition amount of platinum 1050μg / dm 2 or less in the coating layer, the adhesion amount of palladium 600 [mu] g / dm 2 or less, the printed wiring board copper deposition amount of gold is 1000 [mu] g / dm 2 or less It is a foil.

本発明に係るプリント配線板用銅箔の一実施形態においては、被覆層における白金の付着量が２０〜４００μｇ／ｄｍ2、パラジウムの付着量が２０〜２５０μｇ／ｄｍ2、金の付着量が２０〜４００μｇ／ｄｍ2である。 In one embodiment of the copper foil for printed wiring boards according to the present invention, the coating amount of platinum in the coating layer is 20 to 400 μg / dm 2 , the deposition amount of palladium is 20 to 250 μg / dm 2 , and the deposition amount of gold is 20 ˜400 μg / dm 2 .

本発明に係るプリント配線板用銅箔の別の一実施形態においては、被覆層における白金の付着量が５０〜３００μｇ／ｄｍ2、パラジウムの付着量が３０〜１８０μｇ／ｄｍ2、金の付着量が５０〜３００μｇ／ｄｍ2である。 In another embodiment of the copper foil for printed wiring boards according to the present invention, the adhesion amount of platinum in the coating layer is 50 to 300 μg / dm 2 , the adhesion amount of palladium is 30 to 180 μg / dm 2 , and the adhesion amount of gold. Is 50 to 300 μg / dm 2 .

本発明に係るプリント配線板用銅箔の更に別の一実施形態においては、プリント配線板はフレキシブルプリント配線板である。   In another embodiment of the copper foil for printed wiring boards according to the present invention, the printed wiring board is a flexible printed wiring board.

本発明は更に別の一側面において、本発明に係る銅箔で構成された圧延銅箔又は電解銅箔を準備する工程と、銅箔の被覆層をエッチング面として銅箔と樹脂基板との積層体を作製する工程と、積層体を塩化第二鉄水溶液又は塩化第二銅水溶液を用いてエッチングし、銅の不必要部分を除去して銅の回路を形成する工程とを含む電子回路の形成方法である。   In yet another aspect of the present invention, a process of preparing a rolled copper foil or an electrolytic copper foil composed of the copper foil according to the present invention, and a lamination of the copper foil and the resin substrate with the coating layer of the copper foil as an etching surface Forming an electronic circuit including a step of forming a body and a step of etching the laminate using an aqueous ferric chloride solution or an aqueous cupric chloride solution to remove unnecessary portions of copper to form a copper circuit Is the method.

本発明は更に別の一側面において、本発明に係る銅箔と樹脂基板との積層体である。   In another aspect of the present invention, there is provided a laminate of the copper foil and the resin substrate according to the present invention.

本発明は更に別の一側面において、銅層と樹脂基板との積層体であって、銅層の表面の少なくとも一部を被覆する本発明に係る被覆層を備えた積層体である。   In still another aspect, the present invention is a laminate including a copper layer and a resin substrate, the laminate including the coating layer according to the present invention that covers at least a part of the surface of the copper layer.

本発明に係る積層体の一実施形態においては、樹脂基板がポリイミド基板である。   In one embodiment of the laminate according to the present invention, the resin substrate is a polyimide substrate.

本発明は更に別の一側面において、本発明に係る積層体を材料としたプリント配線板である。   In yet another aspect, the present invention is a printed wiring board made of the laminate according to the present invention.

本発明によれば、回路パターン形成の際のエッチング性が良好でファインピッチ化に適し、磁性が良好に抑制されたプリント配線板用銅箔及びそれを用いた積層体を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the etching property in the case of circuit pattern formation is favorable, it is suitable for fine pitch formation, and the copper foil for printed wiring boards by which the magnetism was suppressed favorably, and a laminated body using the same can be provided.

回路パターンの一部の表面写真、当該部分における回路パターンの幅方向の横断面の模式図、及び、該模式図を用いたエッチングファクター（ＥＦ）の計算方法の概略である。It is the outline | summary of the calculation method of the etching factor (EF) using the surface photograph of a part of circuit pattern, the schematic diagram of the cross section of the width direction of the circuit pattern in the said part, and this schematic diagram. 実施例２７により形成された回路およびその断面を示す写真である。42 is a photograph showing a circuit formed according to Example 27 and a cross section thereof. 比較例６により形成された回路を示す写真である。10 is a photograph showing a circuit formed by Comparative Example 6. 銅回路形成時に「ダレ」を生じて樹脂基板近傍で銅回路が短絡した例を示す回路表面の拡大写真である。It is an enlarged photograph of the circuit surface which shows the example which produced "sagging" at the time of copper circuit formation, and the copper circuit short-circuited in the resin substrate vicinity.

（銅箔基材）
本発明に用いることのできる銅箔基材の形態に特に制限はないが、典型的には圧延銅箔や電解銅箔の形態で用いることができる。一般的には、電解銅箔は硫酸銅めっき浴からチタンやステンレスのドラム上に銅を電解析出して製造され、圧延銅箔は圧延ロールによる塑性加工と熱処理を繰り返して製造される。屈曲性が要求される用途には圧延銅箔を適用することが多い。
銅箔基材の材料としてはプリント配線板の導体パターンとして通常使用されるタフピッチ銅や無酸素銅といった高純度の銅の他、例えばＳｎ入り銅、Ａｇ入り銅、Ｃｒ、Ｚｒ又はＭｇ等を添加した銅合金、Ｎｉ及びＳｉ等を添加したコルソン系銅合金のような銅合金も使用可能である。なお、本明細書において用語「銅箔」を単独で用いたときには銅合金箔も含むものとする。 (Copper foil base material)
Although there is no restriction | limiting in particular in the form of the copper foil base material which can be used for this invention, Typically, it can use with the form of rolled copper foil or electrolytic copper foil. In general, the electrolytic copper foil is produced by electrolytic deposition of copper from a copper sulfate plating bath onto a drum of titanium or stainless steel, and the rolled copper foil is produced by repeating plastic working and heat treatment with a rolling roll. Rolled copper foil is often used for applications that require flexibility.
In addition to high-purity copper such as tough pitch copper and oxygen-free copper, which are usually used as conductor patterns for printed wiring boards, for example, Sn-containing copper, Ag-containing copper, Cr, Zr or Mg are added as the copper foil base material. It is also possible to use a copper alloy such as a copper alloy, a Corson copper alloy to which Ni, Si and the like are added. In addition, when the term “copper foil” is used alone in this specification, a copper alloy foil is also included.

本発明に用いることのできる銅箔基材の厚さについても特に制限はなく、プリント配線板用に適した厚さに適宜調節すればよい。例えば、５〜１００μｍ程度とすることができる。但し、ファインパターン形成を目的とする場合には３０μｍ以下、好ましくは２０μｍ以下であり、典型的には５〜２０μｍ程度である。   There is no restriction | limiting in particular also about the thickness of the copper foil base material which can be used for this invention, What is necessary is just to adjust to the thickness suitable for printed wiring boards suitably. For example, it can be set to about 5 to 100 μm. However, for the purpose of forming a fine pattern, it is 30 μm or less, preferably 20 μm or less, and typically about 5 to 20 μm.

本発明に使用する銅箔基材は、特に限定されないが、例えば、粗化処理をしないものを用いても良い。従来は特殊めっきで表面にμｍオーダーの凹凸を付けて表面粗化処理を施し、物理的なアンカー効果によって樹脂との接着性を持たせるケースが一般的であるが、一方でファインピッチや高周波電気特性は平滑な箔が良いとされ、粗化箔では不利な方向に働くことがある。また、粗化処理をしないものであると、粗化処理工程が省略されるので、経済性・生産性向上の効果がある。   Although the copper foil base material used for this invention is not specifically limited, For example, you may use what does not perform a roughening process. Conventionally, the surface is generally roughened by special plating with irregularities on the order of μm, and the physical anchor effect provides adhesion to the resin. A smooth foil is considered to have good characteristics, and a roughened foil may work in a disadvantageous direction. Moreover, since the roughening process process is abbreviate | omitted if it does not perform a roughening process, there exists an effect of economical efficiency and productivity improvement.

（被覆層の構成）
銅箔基材の絶縁基板との接着面の反対側（回路形成予定面側）の表面の少なくとも一部には、被覆層が形成されている。被覆層は、白金、パラジウム、及び、金のいずれか１種以上を含んでいる。被覆層が白金で構成されている場合は、白金の付着量が１０５０μｇ／ｄｍ2以下であり、２０〜４００μｇ／ｄｍ2であるのがより好ましく、５０〜３００μｇ／ｄｍ2であるのが更により好ましい。被覆層がパラジウムで構成されている場合は、パラジウムの付着量が６００μｇ／ｄｍ2以下であり、２０〜２５０μｇ／ｄｍ2であるのがより好ましく、３０〜１８０μｇ／ｄｍ2であるのが更により好ましい。被覆層が金で構成されている場合は、金の付着量が１０００μｇ／ｄｍ2以下であり、２０〜４００μｇ／ｄｍ2であるのがより好ましく、５０〜３００μｇ／ｄｍ2であるのが更により好ましい。被覆層の白金の付着量が１０５０μｇ／ｄｍ2、被覆層のパラジウムの付着量が６００μｇ／ｄｍ2、及び、被覆層の金の付着量が１０００μｇ／ｄｍ2を超えると、それぞれ初期エッチング性に悪影響を及ぼす。 (Configuration of coating layer)
A coating layer is formed on at least a part of the surface of the copper foil base opposite to the surface to be bonded to the insulating substrate (circuit formation planned surface side). The coating layer contains at least one of platinum, palladium, and gold. If the coating layer is composed of platinum, the amount of deposition of platinum is at 1050μg / dm 2 or less, more preferably from 20~400μg / dm 2, further that a 50~300μg / dm 2 from preferable. When the coating layer is made of palladium, the adhesion amount of palladium is 600 μg / dm 2 or less, more preferably 20 to 250 μg / dm 2 , and even more preferably 30 to 180 μg / dm 2. preferable. When the coating layer is made of gold, the adhesion amount of gold is 1000 μg / dm 2 or less, more preferably 20 to 400 μg / dm 2 , and even more preferably 50 to 300 μg / dm 2. preferable. Adhesion amount of platinum coating layer 1050μg / dm 2, the coating layer coating weight of 600 [mu] g / dm 2 of palladium, and, when the amount of deposition of the gold of the coating layer is more than 1000 [mu] g / dm 2, adverse effect on the initial etching of respectively Effect.

（銅箔の製造方法）
本発明に係るプリント配線板用銅箔は、スパッタリング法により形成することができる。すなわち、スパッタリング法によって銅箔基材の表面の少なくとも一部を、被覆層により被覆する。具体的には、スパッタリング法によって、銅箔のエッチング面側に銅よりもエッチングレートの低い白金族金属、金、及び、銀からなる群から選択される１種からなる被覆層を形成する。被覆層は、スパッタリング法に限らず、例えば、電気めっき、無電解めっき等の湿式めっき法で形成してもよい。 (Manufacturing method of copper foil)
The copper foil for printed wiring boards according to the present invention can be formed by a sputtering method. That is, at least a part of the surface of the copper foil base material is coated with the coating layer by a sputtering method. Specifically, a coating layer made of one selected from the group consisting of a platinum group metal, gold, and silver having an etching rate lower than that of copper is formed on the etching surface side of the copper foil by sputtering. The coating layer is not limited to the sputtering method, and may be formed by, for example, a wet plating method such as electroplating or electroless plating.

（プリント配線板の製造方法）
本発明に係る銅箔を用いてプリント配線板（ＰＷＢ）を常法に従って製造することができる。以下に、プリント配線板の製造方法の例を示す。 (Printed wiring board manufacturing method)
A printed wiring board (PWB) can be manufactured according to a conventional method using the copper foil according to the present invention. Below, the example of the manufacturing method of a printed wiring board is shown.

まず、銅箔と絶縁基板とを貼り合わせて積層体を製造する。銅箔が積層される絶縁基板はプリント配線板に適用可能な特性を有するものであれば特に制限を受けないが、例えば、リジッドＰＷＢ用に紙基材フェノール樹脂、紙基材エポキシ樹脂、合成繊維布基材エポキシ樹脂、ガラス布・紙複合基材エポキシ樹脂、ガラス布・ガラス不織布複合基材エポキシ樹脂及びガラス布基材エポキシ樹脂等を使用し、ＦＰＣ用にポリエステルフィルムやポリイミドフィルム等を使用する事ができる。   First, a laminated body is manufactured by bonding a copper foil and an insulating substrate. The insulating substrate on which the copper foil is laminated is not particularly limited as long as it has characteristics applicable to a printed wiring board. For example, paper base phenolic resin, paper base epoxy resin, synthetic fiber for rigid PWB Use cloth base epoxy resin, glass cloth / paper composite base epoxy resin, glass cloth / glass non-woven composite base epoxy resin, glass cloth base epoxy resin, etc., use polyester film, polyimide film, etc. for FPC I can do things.

貼り合わせの方法は、リジッドＰＷＢ用の場合、ガラス布などの基材に樹脂を含浸させ、樹脂を半硬化状態まで硬化させたプリプレグを用意する。銅箔を被覆層の反対側の面からプリプレグに重ねて加熱加圧させることにより行うことができる。   In the case of the rigid PWB, a prepreg is prepared by impregnating a base material such as a glass cloth with a resin and curing the resin to a semi-cured state. It can be carried out by superposing a copper foil on the prepreg from the opposite surface of the coating layer and heating and pressing.

フレキシブルプリント配線板（ＦＰＣ）用の場合、ポリイミドフィルム又はポリエステルフィルムと銅箔とをエポキシ系やアクリル系の接着剤を使って接着することができる（３層構造）。また、接着剤を使用しない方法（２層構造）としては、ポリイミドの前駆体であるポリイミドワニス（ポリアミック酸ワニス）を銅箔に塗布し、加熱することでイミド化するキャスティング法や、ポリイミドフィルム上に熱可塑性のポリイミドを塗布し、その上に銅箔を重ね合わせ、加熱加圧するラミネート法が挙げられる。キャスティング法においては、ポリイミドワニスを塗布する前に熱可塑性ポリイミド等のアンカーコート材を予め塗布しておくことも有効である。   In the case of a flexible printed wiring board (FPC), a polyimide film or a polyester film and a copper foil can be bonded using an epoxy or acrylic adhesive (three-layer structure). In addition, as a method without using an adhesive (two-layer structure), a polyimide varnish (polyamic acid varnish), which is a polyimide precursor, is applied to a copper foil and heated to form an imidization or on a polyimide film. There is a laminating method in which a thermoplastic polyimide is applied to the substrate, a copper foil is overlaid thereon, and heated and pressed. In the casting method, it is also effective to apply an anchor coating material such as thermoplastic polyimide in advance before applying the polyimide varnish.

本発明に係る積層体は各種のプリント配線板（ＰＷＢ）に使用可能であり、特に制限されるものではないが、例えば、導体パターンの層数の観点からは片面ＰＷＢ、両面ＰＷＢ、多層ＰＷＢ（３層以上）に適用可能であり、絶縁基板材料の種類の観点からはリジッドＰＷＢ、フレキシブルＰＷＢ（ＦＰＣ）、リジッド・フレックスＰＷＢに適用可能である。また、本発明に係る積層体は、銅箔を樹脂に貼り付けてなる上述のような銅張積層板に限定されず、樹脂上にスパッタリング、めっきで銅層を形成したメタライジング材であってもよい。   The laminate according to the present invention can be used for various printed wiring boards (PWB) and is not particularly limited. For example, from the viewpoint of the number of layers of the conductor pattern, the single-sided PWB, double-sided PWB, and multilayer PWB ( It is applicable to rigid PWB, flexible PWB (FPC), and rigid flex PWB from the viewpoint of the type of insulating substrate material. Further, the laminate according to the present invention is not limited to the above-described copper-clad laminate obtained by attaching a copper foil to a resin, and is a metalizing material in which a copper layer is formed on the resin by sputtering or plating. Also good.

上述のように作製した積層体の銅箔上に形成された被覆層表面にレジストを塗布し、マスクによりパターンを露光し、現像することによりレジストパターンを形成したものをエッチング液に浸漬する。このとき、エッチングを抑制する白金族金属、金、及び、銀からなる群から選択される１種からなる被覆層は、銅箔上のレジスト部分に近い位置にあり、レジスト側の銅箔のエッチングは、この被覆層近傍がエッチングされていく速度よりも速い速度で、被覆層から離れた部位の銅のエッチングが進行することにより、銅の回路パターンのエッチングがほぼ垂直に進行する。これにより銅の不必要部分を除去されて、次いでエッチングレジストを剥離・除去して回路パターンを露出することができる。
積層体に回路パターンを形成するために用いるエッチング液に対しては、被覆層のエッチング速度は、銅よりも十分に小さいためエッチングファクターを改善する効果を有する。エッチング液は、塩化第二銅水溶液、又は、塩化第二鉄水溶液等を用いることができるが、特に塩化第二鉄水溶液が有効である。微細回路はエッチングに時間が掛かるが、塩化第二鉄水溶液の方が塩化第二銅水溶液よりもエッチング速度が早いためである。また、被覆層を形成する前に、あらかじめ銅箔基材表面に耐熱層を形成しておいてもよい。 A resist is applied to the surface of the coating layer formed on the copper foil of the laminate produced as described above, the pattern is exposed with a mask, and the resist pattern formed by development is immersed in an etching solution. At this time, the coating layer composed of one type selected from the group consisting of platinum group metal, gold, and silver that suppresses etching is located near the resist portion on the copper foil, and etching of the copper foil on the resist side In this case, the etching of the copper circuit pattern proceeds substantially vertically by the etching of the copper away from the coating layer at a rate faster than the rate at which the vicinity of the coating layer is etched. Thus, unnecessary portions of copper can be removed, and then the etching resist can be peeled and removed to expose the circuit pattern.
With respect to the etching solution used for forming the circuit pattern on the laminate, the etching rate of the coating layer is sufficiently smaller than that of copper, so that the etching factor is improved. As the etching solution, an aqueous solution of cupric chloride, an aqueous solution of ferric chloride, or the like can be used, but an aqueous solution of ferric chloride is particularly effective. This is because the fine circuit takes time to etch, but the ferric chloride aqueous solution has a higher etching rate than the cupric chloride aqueous solution. In addition, a heat-resistant layer may be formed in advance on the surface of the copper foil base before forming the coating layer.

以下、本発明の実施例を示すが、これらは本発明をより良く理解するために提供するものであり、本発明が限定されることを意図するものではない。   EXAMPLES Examples of the present invention will be described below, but these are provided for better understanding of the present invention and are not intended to limit the present invention.

（例１：実施例１〜３３）
（銅箔への被覆層の形成）
実施例１〜２１及び２５〜３０の銅箔基材として、厚さ１２又は１７μｍの圧延銅箔（日鉱金属製Ｃ１１００）を用意した。圧延銅箔の表面粗さ（Rz）は０．７μｍであった。また、実施例２２〜２４の銅箔基材として、厚さ９μｍの無粗化処理の電解銅箔を用意した。電解銅箔の表面粗さ（Rz）は１．５μｍであった。さらに、実施例３１〜３３として、厚さ８μｍのメタライジングＣＣＬ（日鉱金属製マキナス、銅層側Ra０．０１μｍ、タイコート層の金属付着量Ｎｉ１７８０μｇ/ｄｍ2、Ｃｒ３６０μｇ/ｄｍ2）を用意した。 (Example 1: Examples 1-33)
(Formation of coating layer on copper foil)
As copper foil base materials of Examples 1 to 21 and 25 to 30, rolled copper foils (Nikko Metal C1100) having a thickness of 12 or 17 μm were prepared. The surface roughness (Rz) of the rolled copper foil was 0.7 μm. Moreover, as a copper foil base material of Examples 22 to 24, a non-roughening electrolytic copper foil having a thickness of 9 μm was prepared. The surface roughness (Rz) of the electrolytic copper foil was 1.5 μm. Further, as Examples 31 to 33, 8 μm thick metalizing CCL (Nikko Metal Machinus, copper layer side Ra 0.01 μm, tie coat layer metal adhesion amount Ni 1780 μg / dm 2 , Cr 360 μg / dm 2 ) was prepared.

銅箔の表面に付着している薄い酸化膜を逆スパッタにより取り除き、Ａｕ、Ｐｔ及び／又はＰｄのターゲットを以下の装置及び条件でスパッタリングすることにより、被覆層を形成した。被覆層の厚さは成膜時間を調整することにより変化させた。スパッタリングに使用した各種金属の単体は純度が３Ｎのものを用いた。
・装置：バッチ式スパッタリング装置（アルバック社、型式ＭＮＳ−６０００）
・到達真空度：１．０×１０-5Ｐａ
・スパッタリング圧：０．２Ｐａ
・逆スパッタ電力：１００Ｗ
・スパッタリング電力：５０Ｗ
・成膜速度：各ターゲットについて一定時間約０．２μｍ成膜し、３次元測定器で厚さを測定し、単位時間当たりのスパッタレートを算出した。
上記実施例のうち、実施例２８〜３０については、以下のターゲットを用いた。
・ターゲット：Ａｕ−５０質量％Ｐｄ、Ｐｔ−５０質量％Ｐｄ、Ａｕ−５０質量％Ｐｔ The thin oxide film adhering to the surface of the copper foil was removed by reverse sputtering, and a target of Au, Pt and / or Pd was sputtered with the following apparatus and conditions to form a coating layer. The thickness of the coating layer was changed by adjusting the film formation time. The simple substance of the various metals used for sputtering used the thing of purity 3N.
-Equipment: Batch type sputtering equipment (ULVAC, Model MNS-6000)
・ Achieving vacuum: 1.0 × 10 −5 Pa
・ Sputtering pressure: 0.2 Pa
・ Reverse sputtering power: 100W
・ Sputtering power: 50W
Film formation rate: About 0.2 μm of film was formed for each target for a fixed time, the thickness was measured with a three-dimensional measuring device, and the sputtering rate per unit time was calculated.
Among the above examples, the following targets were used for Examples 28 to 30.
Target: Au-50 mass% Pd, Pt-50 mass% Pd, Au-50 mass% Pt

上述の被覆層が形成された表面の反対側の銅箔基材表面に対して、以下の条件であらかじめ銅箔基材表面に付着している薄い酸化膜を逆スパッタにより取り除き、Ｎｉ及びＣｒ単層のターゲットをスパッタリングすることにより、Ｎｉ層及びＣｒ層を順に成膜した。Ｎｉ層及びＣｒ層の厚さは成膜時間を調整することにより変化させた。
・装置：バッチ式スパッタリング装置（アルバック社、型式ＭＮＳ−６０００）
・到達真空度：１．０×１０-5Ｐａ
・スパッタリング圧：０．２Ｐａ
・逆スパッタ電力：１００Ｗ
・ターゲット：
Ｎｉ層用＝Ｎｉ（純度３Ｎ）
Ｃｒ層用＝Ｃｒ（純度３Ｎ）
・スパッタリング電力：５０Ｗ
・成膜速度：各ターゲットについて一定時間約０．２μｍ成膜し、３次元測定器で厚さを測定し、単位時間当たりのスパッタレートを算出した。 The thin oxide film previously attached to the copper foil substrate surface under the following conditions is removed by reverse sputtering on the copper foil substrate surface on the opposite side of the surface on which the coating layer is formed, and Ni and Cr alone are removed. A Ni layer and a Cr layer were sequentially formed by sputtering a layer target. The thicknesses of the Ni layer and the Cr layer were changed by adjusting the film formation time.
-Equipment: Batch type sputtering equipment (ULVAC, Model MNS-6000)
・ Achieving vacuum: 1.0 × 10 −5 Pa
・ Sputtering pressure: 0.2 Pa
・ Reverse sputtering power: 100W
·target:
For Ni layer = Ni (purity 3N)
For Cr layer = Cr (purity 3N)
・ Sputtering power: 50W
Film formation rate: About 0.2 μm of film was formed for each target for a fixed time, the thickness was measured with a three-dimensional measuring device, and the sputtering rate per unit time was calculated.

銅箔基材のＮｉ層及びＣｒ層形成側表面に以下の手順により、ポリイミドフィルムを接着した。
（１）７ｃｍ×７ｃｍの銅箔に対しアプリケーターを用い、宇部興産製Ｕワニス−Ａ（ポリイミドワニス）を乾燥体で２５μｍになるよう塗布。
（２）（１）で得られた樹脂付き銅箔を空気下乾燥機で１３０℃３０分で乾燥。
（３）窒素流量を１０Ｌ／ｍｉｎに設定した高温加熱炉において、３５０℃３０分でイミド化。 A polyimide film was bonded to the Ni layer and Cr layer forming side surface of the copper foil base material by the following procedure.
(1) Using an applicator on a copper foil of 7 cm × 7 cm, Ube Industries-made U varnish-A (polyimide varnish) was applied to a dry body to a thickness of 25 μm.
(2) The resin-coated copper foil obtained in (1) is dried at 130 ° C. for 30 minutes in an air dryer.
(3) Imidization at 350 ° C. for 30 minutes in a high-temperature heating furnace with a nitrogen flow rate set to 10 L / min.

＜付着量の測定＞
被覆層のＡｕ，Ｐｄ、Ｐｔの付着量測定は、王水で表面処理銅箔サンプルを溶解させ、その溶解液を希釈し、原子吸光分析法で行った。 <Measurement of adhesion amount>
The adhesion amount of Au, Pd, and Pt in the coating layer was measured by atomic absorption spectrometry by dissolving the surface-treated copper foil sample with aqua regia, diluting the solution.

（エッチングによる回路形状）
銅箔の被覆層が形成された面に感光性レジスト塗布及び露光工程により１０本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を以下の条件で実施した。 (Circuit shape by etching)
Ten circuits were printed by a photosensitive resist coating and exposure process on the surface on which the coating layer of copper foil was formed, and an etching process for removing unnecessary portions of the copper foil was performed under the following conditions.

＜エッチング条件＞
・塩化第二鉄水溶液：（３７ｗｔ％、ボーメ度：４０°）
・液温：５０°Ｃ
・スプレー圧：０．２５ＭＰａ
（５０μｍピッチ回路形成）
・レジストＬ／Ｓ＝３３μｍ／１７μｍ
・仕上がり回路ボトム（底部）幅：２５μｍ
・エッチング時間：１０〜１３０秒
（３０μｍピッチ回路形成）
・レジストＬ／Ｓ＝２５μｍ／５μｍ
・仕上がり回路ボトム（底部）幅：１５μｍ
・エッチング時間：３０〜７０秒
・エッチング終点の確認：時間を変えてエッチングを数水準行い、光学顕微鏡で回路間に銅が残存しなくなるのを確認し、これをエッチング時間とした。
エッチング後、４５℃のＮａＯＨ水溶液（１００ｇ／Ｌ）に１分間浸漬させてレジストを剥離した。 <Etching conditions>
-Ferric chloride aqueous solution: (37 wt%, Baume degree: 40 °)
・ Liquid temperature: 50 ° C
・ Spray pressure: 0.25 MPa
(50 μm pitch circuit formation)
・ Resist L / S = 33μm / 17μm
-Finished circuit bottom (bottom) width: 25 μm
Etching time: 10 to 130 seconds (30 μm pitch circuit formation)
・ Resist L / S = 25μm / 5μm
-Finished circuit bottom (bottom) width: 15 μm
-Etching time: 30 to 70 seconds-Confirmation of etching end point: Etching was carried out at several levels by changing the time, and it was confirmed by an optical microscope that no copper remained between the circuits.
After the etching, the resist was peeled off by being immersed in an aqueous NaOH solution (100 g / L) at 45 ° C. for 1 minute.

＜エッチングファクターの測定条件＞
エッチングファクターは、末広がりにエッチングされた場合（ダレが発生した場合）、回路が垂直にエッチングされたと仮定した場合の、銅箔上面からの垂線と樹脂基板との交点からのダレの長さの距離をａとした場合において、このａと銅箔の厚さｂとの比：ｂ／ａを示すものであり、この数値が大きいほど、傾斜角は大きくなり、エッチング残渣が残らず、ダレが小さくなることを意味する。図１に、回路パターンの一部の表面写真と、当該部分における回路パターンの幅方向の横断面の模式図と、該模式図を用いたエッチングファクターの計算方法の概略とを示す。このａは回路上方からのＳＥＭ観察により測定し、エッチングファクター（ＥＦ＝ｂ／ａ）を算出した。このエッチングファクターを用いることにより、エッチング性の良否を簡単に判定できる。さらに、傾斜角θは上記手順で測定したａ及び銅箔の厚さｂを用いてアークタンジェントを計算することにより算出した。これらの測定範囲は回路長６００μｍで、１２点のエッチングファクター、その標準偏差及び傾斜角θの平均値を結果として採用した。 <Etching factor measurement conditions>
The etching factor is the distance of the length of sagging from the intersection of the vertical line from the upper surface of the copper foil and the resin substrate, assuming that the circuit is etched vertically when sagging at the end (when sagging occurs) Is a ratio of a to the thickness b of the copper foil: b / a, and the larger the value, the larger the inclination angle, and the etching residue does not remain and the sagging is small. It means to become. FIG. 1 shows a surface photograph of a part of a circuit pattern, a schematic diagram of a cross section in the width direction of the circuit pattern at the part, and an outline of a method for calculating an etching factor using the schematic diagram. This a was measured by SEM observation from above the circuit, and the etching factor (EF = b / a) was calculated. By using this etching factor, it is possible to easily determine whether the etching property is good or bad. Furthermore, the inclination angle θ was calculated by calculating the arc tangent using a and the thickness b of the copper foil measured in the above procedure. The measurement range was a circuit length of 600 μm, and an etching factor of 12 points, its standard deviation, and an average value of the inclination angle θ were adopted as a result.

（例２：比較例１〜３：ブランク材）
１２μｍ厚、１７μｍ厚及び９μｍ厚の圧延銅箔を準備し、それぞれ例１と同じ手順でポリイミドフィルムを接着した。次に反対面に感光性レジスト塗布及び露光工程により１０本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を例１の条件で実施した。 (Example 2: Comparative Examples 1-3: Blank material)
Rolled copper foils having a thickness of 12 μm, 17 μm, and 9 μm were prepared, and polyimide films were bonded in the same procedure as in Example 1. Next, 10 circuits were printed on the opposite surface by a photosensitive resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed under the conditions of Example 1.

（例３：比較例４〜６）
１２μｍ厚の圧延銅箔を準備し、例１と同じ手順でポリイミドフィルムを接着した。次に、銅箔表面に例１と同様にＡｕ、Ｐｄ及び／又はＰｔの各層をスパッタリングで形成し、エッチングで回路を形成した。
例１〜３の各測定結果を表１〜４に示す。 (Example 3: Comparative Examples 4 to 6)
A rolled copper foil having a thickness of 12 μm was prepared, and a polyimide film was bonded in the same procedure as in Example 1. Next, each layer of Au, Pd and / or Pt was formed on the copper foil surface by sputtering in the same manner as in Example 1, and a circuit was formed by etching.
Each measurement result of Examples 1-3 is shown in Tables 1-4.

なお、図２（ｂ）に示すように、回路の断面形状は、正確には斜辺が直線である台形ではない。表２及び４において実施例及び比較例の回路の傾斜角が記載されているが、これはあくまで図１に示した定義式によって算出した値である。   As shown in FIG. 2B, the cross-sectional shape of the circuit is not exactly a trapezoid whose hypotenuse is a straight line. In Tables 2 and 4, the inclination angles of the circuits of the example and the comparative example are described, but this is a value calculated by the definition formula shown in FIG.

（評価）
（実施例１〜３３）
実施例１〜３３ではいずれもエッチングファクターが大きく且つバラツキもなく、矩形方に近い断面の回路を形成することができた。
図２に、実施例２７により形成された回路の写真およびその断面写真を示す。 (Evaluation)
(Examples 1-33)
In each of Examples 1 to 33, the etching factor was large and there was no variation, and a circuit having a cross section close to a rectangular shape could be formed.
FIG. 2 shows a photograph of a circuit formed in Example 27 and a cross-sectional photograph thereof.

（比較例１〜６）
比較例１〜３は、それぞれ銅箔表面が未処理であるブランク材であり、矩形方の断面の回路を形成することができなかった。
比較例４〜６では、白金の付着量が１０５０μｇ／ｄｍ2超、パラジウムの付着量が６００μｇ／ｄｍ2超、又は、金の付着量が１０００μｇ／ｄｍ2超であるために、矩形方の断面の回路を形成することができなかった。ここで、例として、図３に、比較例６により形成された回路の写真を示す。 (Comparative Examples 1-6)
Comparative Examples 1 to 3 were blank materials each having an untreated copper foil surface, and a circuit having a rectangular cross section could not be formed.
In Comparative Example 4-6, the adhesion amount of platinum 1050μg / dm 2 greater, palladium adhesion amount 600 [mu] g / dm 2, or greater, for the amount of deposition of the gold is 1000 [mu] g / dm 2 greater than the cross section of the rectangular side The circuit could not be formed. Here, as an example, FIG. 3 shows a photograph of a circuit formed in Comparative Example 6.

Claims (9)

銅箔基材と、該銅箔基材の表面の少なくとも一部を被覆し、且つ、白金、パラジウム、及び、金のいずれか１種以上を含む被覆層とを備え、
前記被覆層における白金の付着量が１０５０μｇ／ｄｍ2以下、パラジウムの付着量が６００μｇ／ｄｍ2以下、金の付着量が１０００μｇ／ｄｍ2以下であるプリント配線板用銅箔。 A copper foil base material, and a coating layer that covers at least a part of the surface of the copper foil base material and includes any one or more of platinum, palladium, and gold;
The adhesion amount of platinum in the coating layer is 1050μg / dm 2 or less, the adhesion amount of palladium 600 [mu] g / dm 2 or less, gold copper foil for printed wiring boards deposition amount is 1000 [mu] g / dm 2 following. 前記被覆層における白金の付着量が２０〜４００μｇ／ｄｍ2、パラジウムの付着量が２０〜２５０μｇ／ｄｍ2、金の付着量が２０〜４００μｇ／ｄｍ2である請求項１に記載のプリント配線板用銅箔。 2. The printed wiring board according to claim 1, wherein an adhesion amount of platinum in the coating layer is 20 to 400 μg / dm 2 , an adhesion amount of palladium is 20 to 250 μg / dm 2 , and an adhesion amount of gold is 20 to 400 μg / dm 2. Copper foil. 前記被覆層における白金の付着量が５０〜３００μｇ／ｄｍ2、パラジウムの付着量が３０〜１８０μｇ／ｄｍ2、金の付着量が５０〜３００μｇ／ｄｍ2である請求項２に記載のプリント配線板用銅箔。 3. The printed wiring board according to claim 2 , wherein an adhesion amount of platinum in the coating layer is 50 to 300 μg / dm 2 , an adhesion amount of palladium is 30 to 180 μg / dm 2 , and an adhesion amount of gold is 50 to 300 μg / dm 2. Copper foil. プリント配線板はフレキシブルプリント配線板である請求項１〜３のいずれかに記載のプリント配線板用銅箔。   A printed wiring board is a flexible printed wiring board, The copper foil for printed wiring boards in any one of Claims 1-3. 請求項１〜４のいずれかに記載の銅箔で構成された圧延銅箔又は電解銅箔を準備する工程と、
前記銅箔の被覆層をエッチング面として該銅箔と樹脂基板との積層体を作製する工程と、
前記積層体を塩化第二鉄水溶液又は塩化第二銅水溶液を用いてエッチングし、銅の不必要部分を除去して銅の回路を形成する工程と、
を含む電子回路の形成方法。 A step of preparing a rolled copper foil or an electrolytic copper foil composed of the copper foil according to claim 1;
A step of producing a laminate of the copper foil and the resin substrate using the coating layer of the copper foil as an etching surface;
Etching the laminate with an aqueous ferric chloride solution or an aqueous cupric chloride solution to remove unnecessary portions of copper to form a copper circuit;
A method of forming an electronic circuit comprising: 請求項１〜４のいずれかに記載の銅箔と樹脂基板との積層体。   The laminated body of the copper foil and resin substrate in any one of Claims 1-4. 銅層と樹脂基板との積層体であって、
前記銅層の表面の少なくとも一部を被覆する請求項１〜４のいずれかに記載の被覆層を備えた積層体。 A laminate of a copper layer and a resin substrate,
The laminated body provided with the coating layer in any one of Claims 1-4 which coat | covers at least one part of the surface of the said copper layer. 前記樹脂基板がポリイミド基板である請求項６又は７に記載の積層体。   The laminate according to claim 6 or 7, wherein the resin substrate is a polyimide substrate. 請求項６〜８のいずれかに記載の積層体を材料としたプリント配線板。   The printed wiring board which used the laminated body in any one of Claims 6-8 as a material.
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US5338619A (en) * 1991-05-16 1994-08-16 Fukuda Metal Foil And Powder Co., Ltd. Copper foil for printed circuits and method of producing same
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