JP4580890B2 - 薄膜トランジスタ、平板表示装置用アレイ基板、薄膜トランジスタの製造方法、及び平板表示装置用アレイ基板の製造方法 - Google Patents
薄膜トランジスタ、平板表示装置用アレイ基板、薄膜トランジスタの製造方法、及び平板表示装置用アレイ基板の製造方法 Download PDFInfo
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Description
また、本発明に係る平板表示装置用アレイ基板は、基板上に位置して、中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーと、前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層と、前記固定層上に位置するゲート絶縁膜と、前記ゲート絶縁膜上に位置するゲート電極と、前記固定層から露出した前記絶縁層が除去されて、前記シリコンナノワイヤーの両側部の前記コアが露出され、前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部に位置する第1ソース電極及び第1ドレイン電極と、前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極と、前記第2ドレイン電極に連結される画素電極とを含むものである。
また、本発明に係る薄膜トランジスタの製造方法は、中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーを基板上に配置する段階と、前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層を形成する段階と、前記固定層上にゲート絶縁膜を形成する段階と、前記ゲート絶縁膜上にゲート電極を形成する段階と、前記固定層から露出した前記絶縁層を除去して、前記シリコンナノワイヤーの両側部に位置する前記コアを露出する段階と、前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部にソース電極及びドレイン電極を形成する段階とを含むものである。
また、本発明に係る平板表示装置用アレイ基板の製造方法は、中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーを基板上に配置する段階と、前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層を形成する段階と、前記固定層上にゲート絶縁膜を形成する段階と、前記ゲート絶縁膜上にゲート電極を形成する段階と、前記固定層から露出した前記絶縁層を除去して、前記シリコンナノワイヤーの両側部に位置する前記コアを露出する段階と、前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部に第1ソース電極及び第1ドレイン電極を形成する段階と、前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極を形成する段階と、前記第2ドレイン電極に連結される画素電極を形成する段階とを含むものである。
また、本発明に係る薄膜トランジスタの製造方法は、中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーを含む溶媒を基板上にコーティングする段階と、前記基板から前記溶媒を除去する段階と、前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層を形成する段階と、前記固定層上にゲート絶縁膜及びゲート電極を連続的に形成する段階と、前記固定層から露出した前記絶縁層を除去して、前記シリコンナノワイヤーの両側部に位置する前記コアを露出する段階と、前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部にソース電極及びドレイン電極を形成する段階とを含むものである。
さらに、本発明に係る平板表示装置用アレイ基板の製造方法は、中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーを含む溶媒を基板上にコーティングする段階と、前記基板から前記溶媒を除去する段階と、前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層を形成する段階と、前記固定層上にゲート絶縁膜及びゲート電極を連続的に形成する段階と、前記固定層から露出した前記絶縁層を除去して、前記シリコンナノワイヤーの両側部に位置する前記コアを露出する段階と、前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部に第1ソース電極及び第1ドレイン電極を形成する段階と、前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極を形成する段階と、前記第2ドレイン電極に連結される画素電極を形成する段階とを含むものである。
本発明の実施の形態1は、アクティブ層としてシリコンナノワイヤーを含み、ソース電極及びドレイン電極は、ゲート電極と同一工程によって同一物質で構成される。
以下、本発明の実施の形態2は、シリコンナノワイヤーを基板上にスプレー方式によって形成する特徴を含む。
Claims (25)
- 基板上に位置して、中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーと、
前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層と、
前記固定層上に位置するゲート絶縁膜と、
前記ゲート絶縁膜上に位置するゲート電極と、
前記固定層から露出した前記絶縁層が除去されて、前記シリコンナノワイヤーの両側部の前記コアが露出され、前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部に位置するソース電極及びドレイン電極と
を含む薄膜トランジスタ。 - 前記コアと前記絶縁層は、同軸構造を有する請求項1に記載の薄膜トランジスタ。
- 前記シリコンナノワイヤーは、棒状である請求項1に記載の薄膜トランジスタ。
- 前記シリコンナノワイヤーは、多数のシリコンナノワイヤーで構成される請求項1に記載の薄膜トランジスタ。
- 前記ゲート電極は、前記ソース電極及び前記ドレイン電極と同一物質で構成される請求項1に記載の薄膜トランジスタ。
- 前記固定層は、有機絶縁物質で構成される請求項1に記載の薄膜トランジスタ。
- 前記有機絶縁物質は、ベンゾシクロブテン(BCB)とアクリル系樹脂を含む請求項6に記載の薄膜トランジスタ。
- 基板上に位置して、中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーと、
前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層と、
前記固定層上に位置するゲート絶縁膜と、
前記ゲート絶縁膜上に位置するゲート電極と、
前記固定層から露出した前記絶縁層が除去されて、前記シリコンナノワイヤーの両側部の前記コアが露出され、前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部に位置する第1ソース電極及び第1ドレイン電極と、
前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極と、
前記第2ドレイン電極に連結される画素電極と
を含む平板表示装置用アレイ基板。 - 前記第1ソース電極と前記第2ソース電極間、前記第1ドレイン電極と前記第2ドレイン電極間に位置して、前記第1ソース電極及び前記第1ドレイン電極の一部領域を露出させる第1コンタクトホールと第2コンタクトホールを有する絶縁膜をさらに含む請求項8に記載の平板表示装置用アレイ基板。
- 前記第2ソース電極は、前記第1コンタクトホールを通じて前記第1ソース電極に連結され、
前記第2ドレイン電極は、前記第2コンタクトホールを通じて前記第1ドレイン電極に連結される
請求項9に記載の平板表示装置用アレイ基板。 - 前記第2ドレイン電極と前記画素電極間、前記第2ドレイン電極と前記画素電極間に位置し、前記第2ドレイン電極の一部領域を露出するドレインコンタクトホールを有する保護層をさらに含む請求項8に記載の平板表示装置用アレイ基板。
- 前記画素電極は、前記ドレインコンタクトホールを通じて前記第2ドレイン電極に連結される請求項11に記載の平板表示装置用アレイ基板。
- 中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーを基板上に配置する段階と、
前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層を形成する段階と、
前記固定層上にゲート絶縁膜を形成する段階と、
前記ゲート絶縁膜上にゲート電極を形成する段階と、
前記固定層から露出した前記絶縁層を除去して、前記シリコンナノワイヤーの両側部に位置する前記コアを露出する段階と、
前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部にソース電極及びドレイン電極を形成する段階と
を含む薄膜トランジスタの製造方法。 - 前記シリコンナノワイヤーは、スプレー方式によって前記基板上に配置される請求項13に記載の薄膜トランジスタの製造方法。
- 前記ゲート電極は、前記ソース電極及び前記ドレイン電極と同一工程によって形成される請求項13に記載の薄膜トランジスタの製造方法。
- 中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーを基板上に配置する段階と、
前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層を形成する段階と、
前記固定層上にゲート絶縁膜を形成する段階と、
前記ゲート絶縁膜上にゲート電極を形成する段階と、
前記固定層から露出した前記絶縁層を除去して、前記シリコンナノワイヤーの両側部に位置する前記コアを露出する段階と、
前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部に第1ソース電極及び第1ドレイン電極を形成する段階と、
前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極を形成する段階と、
前記第2ドレイン電極に連結される画素電極を形成する段階と
を含む平板表示装置用アレイ基板の製造方法。 - 前記第1ソース電極と前記第2ソース電極間、前記第1ドレイン電極と前記第2ドレイン電極間に位置して、前記第1ソース電極及び前記第1ドレイン電極の一部領域を各々露出する第1コンタクトホールと第2コンタクトホールを有する絶縁膜を形成する段階をさらに含む請求項16に記載の平板表示装置用アレイ基板の製造方法。
- 前記第2ソース電極は、前記第1コンタクトホールを通じて前記第1ソース電極に連結され、
前記第2ドレイン電極は、前記第2コンタクトホールを通じて前記第1ドレイン電極に連結される
請求項17に記載の平板表示装置用アレイ基板の製造方法。 - 前記第2ドレイン電極と前記画素電極間、前記第2ドレイン電極と前記画素電極間に位置して、前記第2ドレイン電極の一部を露出させるドレインコンタクトホールを含む保護層を形成する段階をさらに含む請求項17に記載の平板表示装置用アレイ基板の製造方法。
- 前記画素電極は、前記ドレインコンタクトホールを通じて前記第2ドレイン電極に連結される請求項19に記載の平板表示装置用アレイ基板の製造方法。
- 中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーを含む溶媒を基板上にコーティングする段階と、
前記基板から前記溶媒を除去する段階と、
前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層を形成する段階と、
前記固定層上にゲート絶縁膜及びゲート電極を連続的に形成する段階と、
前記固定層から露出した前記絶縁層を除去して、前記シリコンナノワイヤーの両側部に位置する前記コアを露出する段階と、
前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部にソース電極及びドレイン電極を形成する段階と
を含む薄膜トランジスタの製造方法。 - 前記溶媒は、界面活性剤をさらに含む請求項21に記載の薄膜トランジスタの製造方法。
- 前記溶媒は、ヒーティングによって除去される請求項22に記載の薄膜トランジスタの製造方法。
- 前記ヒーティングは、100℃以下の温度で行われる請求項23に記載の薄膜トランジスタの製造方法。
- 中央部と両側部を有し、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層を含むシリコンナノワイヤーを含む溶媒を基板上にコーティングする段階と、
前記基板から前記溶媒を除去する段階と、
前記シリコンナノワイヤーを基板上に固定して、前記シリコンナノワイヤーの中央部に位置する固定層を形成する段階と、
前記固定層上にゲート絶縁膜及びゲート電極を連続的に形成する段階と、
前記固定層から露出した前記絶縁層を除去して、前記シリコンナノワイヤーの両側部に位置する前記コアを露出する段階と、
前記シリコンナノワイヤーと電気的に連結されるように、前記シリコンナノワイヤーの両側部の露出した各々の前記コアの上部に第1ソース電極及び第1ドレイン電極を形成する段階と、
前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極を形成する段階と、
前記第2ドレイン電極に連結される画素電極を形成する段階と
を含む平板表示装置用アレイ基板の製造方法。
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US20130228750A1 (en) | 2013-09-05 |
US8426869B2 (en) | 2013-04-23 |
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CN1845341A (zh) | 2006-10-11 |
CN100472813C (zh) | 2009-03-25 |
US7704806B2 (en) | 2010-04-27 |
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