JP4552934B2 - 電子部品の実装方法 - Google Patents
電子部品の実装方法 Download PDFInfo
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- JP4552934B2 JP4552934B2 JP2006510559A JP2006510559A JP4552934B2 JP 4552934 B2 JP4552934 B2 JP 4552934B2 JP 2006510559 A JP2006510559 A JP 2006510559A JP 2006510559 A JP2006510559 A JP 2006510559A JP 4552934 B2 JP4552934 B2 JP 4552934B2
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- melting point
- point metal
- electrode
- alloy
- electronic component
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Description
前記回路電極及び/又は前記素子電極上に、合金を形成できる少なくとも2種類以上の金属を2層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより、低融点金属層をあらかじめ形成した後、前記回路電極及び前記素子電極を対向させて、少なくとも低融点金属層が溶融する温度で加熱加圧し、前記低融点金属層を、前記回路電極及び前記素子電極中へ固液拡散させることによって、前記回路電極と前記素子電極とを接合すると共に、接合される前記回路電極と前記素子電極との間にあらかじめ形成される、前記低融点金属層の合計厚さが0.1〜1μmであることを特徴とする。
また、本発明においては、前記回路電極及び/又は前記素子電極上に、合金を形成できる少なくとも2種類以上の金属を2層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより、低融点金属層が予め形成されるようになっている。これにより、合金層における合金組成や供給量のバラツキがなくなるので、低温での安定した拡散接合が可能となり、信頼性の高い接合部を得ることができる。
更に、本発明においては、前記積層した金属層を前記少なくとも2種類以上の金属の各融点のうち最も低い融点以下の温度で予備加熱することが好ましい。
また、本発明においては、SnとInとを2層以上に積層し、該積層した金属層を110〜125℃の温度で予備加熱することが好ましい。
ai=χi (1)
ここで、ai、χiはそれぞれi成分の活量及びモル分率である。i成分の合金状態における蒸気圧をpiとし、i成分の純粋状態における蒸気圧をpi(0)とすれば、定義により、ai=pi/pi(0)である。
ai=γiχi (2)
合金のi成分に対する部分モル自由エネルギー変化ΔGiは、以下の(3)式で与えられるので、(2)式を用いて、(4)式のように変形できる。
ΔGi=RTlnai (3)
ΔGi=RTlnγi+RTlnχi (4)
ここで、Rは気体定数、Tは絶対温度である。また、組成Xにおける自由エネルギーΔGiは、以下の(5)式で表すことができる。
ΔGi=X(1−X)(Aij+(1−2X)Bij+CijX(1−X)) (5)
ここで、例えば、SnInの共晶合金の場合、上記のように、Inの組成はX=52、Snの組成はX=48である。
ΔGi=−1604.62J/mol (6)
が得られる。同様に、SnとCuとの反応性を考慮して、(5)式の各係数にAij=−35479、Bij=−19182、Cij=59493、X=0.48を代入すると、
ΔGi=−5340.65J/mol (7)
が得られる。(3)式と(6)式より、In-Cu反応における活量aAを求め、(3)式と(7)式より、Sn-Cu反応における活量aBを求めると、以下の(8)(9)式となる。ただし、R=8.314[J・mol−1・K−1]、T=700K(427℃)である。
aA=exp(ΔGi/RT)=0.835 (8)
aB=exp(ΔGi/RT)=0.632 (9)
次に、真空蒸着における各成分の線束を考えると、2元合金が蒸発しているとき、ある瞬間における表面組成をχA、χBとすれば、蒸発線束比JA/JBは、以下の(10)、(11)式で表される。
JA/JB=(aApA/aBpB)(MB/MA)1/2
=(γAχApA/γBχBpB)(MB/MA)1/2=Z(χA/χB) (10)
Z=(γApA/γBpB)(MB/MA)1/2 (11)
この(10)、(11)式のZの値が1となるときが、蒸発成分比が元の合金の組成(Inの組成:χA=52、Snの組成:χB=48)に等しくなる条件である。よって、(10)式において、Inの分子量MA=114.818、Snの分子量MB=118.710、aA=0.835、aB=0.632、Z=1を代入して、
(pA/pB)=Z(χA/χB)(aB/aA)(MA/MB)1/2=0.81 (12)
が得られる。したがって、この(12)式を満たす蒸気圧となるような条件下で蒸着することで、In:Sn=52:48となるような、Cu上へのSnIn共晶合金の成膜が可能となる。
χA=1/(1+(WB/WA)(MA/MB)) (13)
χB=1/(1+(WA/WB)(MB/MA)) (14)
したがって、上記の(13)、(14)式を、(10)、(11)式に代入して、蒸発線束重量比ΓA/ΓBは、以下の(15)式で表される。
ΓA/ΓB=(γAχApA/γBχBpB)(MA/MB)1/2
=(γApA/γBpB)(MB/MA)1/2(WA/WB) (15)
(13)、(14)式において、Inの分子量MA=114.818、Snの分子量MB=118.710、Inの重量%WA=0.52、Snの重量%WB=0.48を代入すると、χA=0.528、χB=0.472を得る。
(γApA/γBpB)=(ΓA/ΓB)(MB/MA)1/2(χB/χA)=0.98 (16)
が得られる。したがって、この(16)式を満たす活量係数及び蒸気圧となるような条件下で蒸着することで、In:Sn=52:48となるような、Cu上へのSnIn共晶合金の成膜が可能となる。
図1に示す方法を用いて電子部品を回路基板上に実装した。
蒸着による低融点金属層の形成において、上記の(16)式における蒸気圧比と活量係数比の積(γApA/γBpB)=0.98となるように制御しながら成膜を行った以外は参考例1と同様の条件で、半導体チップと回路基板との接合を行った。
図1に示す方法を用いて電子部品を回路基板上に実装した。
図1に示す方法を用いて電子部品を回路基板上に実装した。
低融点金属層として、1対のCu電極上に、それぞれ1μm及び1μm、合計厚さ2μmのIn層を蒸着により形成した以外は、実施例2と同様の条件で接合し、参考例3の接合部を得た。この接合部について、接合部端からのInの排出の状況を観察したところ、接合部端には10〜20μm程度のInの排出が観られた。
Claims (10)
- 回路基板上に形成された金属からなる回路電極と、電子部品上に形成された金属からなる素子電極とを接合して、前記電子部品を前記回路基板上に実装する方法において、
前記回路電極及び/又は前記素子電極上に、合金を形成できる少なくとも2種類以上の金属を2層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより、低融点金属層をあらかじめ形成した後、前記回路電極及び前記素子電極を対向させて、少なくとも低融点金属層が溶融する温度で加熱加圧し、前記低融点金属層を、前記回路電極及び前記素子電極中へ固液拡散させることによって、前記回路電極と前記素子電極とを接合すると共に、接合される前記回路電極と前記素子電極との間にあらかじめ形成される、前記低融点金属層の合計厚さが0.1〜1μmであることを特徴とする電子部品の実装方法。 - 前記低融点金属層が、SnIn又はSnBiである請求項1に記載の電子部品の実装方法。
- 前記低融点金属層が、SnInの共晶合金である請求項2に記載の電子部品の実装方法。
- 前記接合時の加熱温度が、前記低融点金属層の融点より0〜100℃高い温度である請求項2又は3に記載の電子部品の実装方法。
- 前記回路電極及び前記素子電極の材質が、Cu、Ni、Au、Alより選択される一種又はそれらの合金である請求項1〜4のいずれか1つに記載の電子部品の実装方法。
- 前記回路電極及び前記素子電極表面の表面粗さRaが0.4〜10μmの粗面であって、前記接合時に前記粗面同士が塑性変形して接合可能となるように加圧する請求項1〜5のいずれか1つに記載の電子部品の実装方法。
- 前記加熱加圧は、前記低融点金属層が、前記回路電極及び前記素子電極中に完全に固液拡散して、低融点金属の濃度勾配を有するが全体として単一の合金層となるまで行なう請求項1〜6のいずれか1つに記載の電子部品の実装方法。
- 前記低融点金属層の合金は融点が220℃以下の合金である請求項1〜7のいずれか1つに記載の電子部品の実装方法。
- 前記積層した金属層を前記少なくとも2種類以上の金属の各融点のうち最も低い融点以下の温度で予備加熱する請求項1〜7のいずれか1つに記載の電子部品の実装方法。
- SnとInとを2層以上に積層し、該積層した金属層を110〜125℃の温度で予備加熱する請求項9に記載の電子部品の実装方法。
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JP4136845B2 (ja) * | 2002-08-30 | 2008-08-20 | 富士電機ホールディングス株式会社 | 半導体モジュールの製造方法 |
JP2007234841A (ja) * | 2006-02-28 | 2007-09-13 | Kyocera Corp | 配線基板、実装部品、電子装置、配線基板の製造方法および電子装置の製造方法 |
KR101011199B1 (ko) * | 2007-11-01 | 2011-01-26 | 파나소닉 주식회사 | 실장 구조체 |
JP4454658B2 (ja) * | 2007-12-04 | 2010-04-21 | パナソニック株式会社 | 電子部品製造方法 |
US7811932B2 (en) * | 2007-12-28 | 2010-10-12 | Freescale Semiconductor, Inc. | 3-D semiconductor die structure with containing feature and method |
US8441123B1 (en) * | 2009-08-13 | 2013-05-14 | Amkor Technology, Inc. | Semiconductor device with metal dam and fabricating method |
JP2011061073A (ja) * | 2009-09-11 | 2011-03-24 | Toshiba Corp | 半導体装置の製造方法及び半導体製造装置 |
TWI399974B (zh) * | 2010-03-12 | 2013-06-21 | Primax Electronics Ltd | 攝像模組之組裝方法 |
JP5273073B2 (ja) * | 2010-03-15 | 2013-08-28 | オムロン株式会社 | 電極構造及び当該電極構造を備えたマイクロデバイス用パッケージ |
DE112013007187B4 (de) | 2013-09-13 | 2023-08-10 | Ev Group E. Thallner Gmbh | Verfahren zum Aufbringen einer Bondschicht |
US9865565B2 (en) | 2015-12-08 | 2018-01-09 | Amkor Technology, Inc. | Transient interface gradient bonding for metal bonds |
US10037957B2 (en) | 2016-11-14 | 2018-07-31 | Amkor Technology, Inc. | Semiconductor device and method of manufacturing thereof |
JP6613336B2 (ja) * | 2018-05-02 | 2019-11-27 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | ボンディング層を施与する方法 |
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- 2004-03-02 WO PCT/JP2004/002534 patent/WO2005086221A1/ja active Application Filing
- 2004-03-02 US US10/591,724 patent/US20070152025A1/en not_active Abandoned
- 2004-03-02 JP JP2006510559A patent/JP4552934B2/ja not_active Expired - Fee Related
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JPH083732A (ja) * | 1994-06-16 | 1996-01-09 | Seiko Instr Inc | 金色装飾品の製造方法 |
JP2001274201A (ja) * | 2000-03-27 | 2001-10-05 | Toshiba Corp | 電子デバイス及びその製造方法 |
JP2001274195A (ja) * | 2000-03-28 | 2001-10-05 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002289768A (ja) * | 2000-07-17 | 2002-10-04 | Rohm Co Ltd | 半導体装置およびその製法 |
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JP4136845B2 (ja) * | 2002-08-30 | 2008-08-20 | 富士電機ホールディングス株式会社 | 半導体モジュールの製造方法 |
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EP1734570A1 (en) | 2006-12-20 |
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US20070152025A1 (en) | 2007-07-05 |
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