JP4464189B2 - ノイズキャンセル回路 - Google Patents
ノイズキャンセル回路 Download PDFInfo
- Publication number
- JP4464189B2 JP4464189B2 JP2004133614A JP2004133614A JP4464189B2 JP 4464189 B2 JP4464189 B2 JP 4464189B2 JP 2004133614 A JP2004133614 A JP 2004133614A JP 2004133614 A JP2004133614 A JP 2004133614A JP 4464189 B2 JP4464189 B2 JP 4464189B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- noise
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Description
20、21 出力バッファ
22 キャンセルデータ生成回路
23 パラレル/シリアル変換回路
24 コンデンサ
25 パラレルデータ信号
26 クロック信号
27、35 ノード
28、29 出力端子
31、33 Dフリップフロップ回路
32 一致回路
34 排他論理和回路
Claims (6)
- クロック信号に同期したタイミングで変化しうる第1の2値信号を出力する第1の回路と、
前記タイミングにおいて前記第1の2値信号が変化しない場合には第2の2値信号を変化させて出力し、前記タイミングにおいて前記第1の2値信号が変化する場合には前記第2の2値信号を変化させずに出力する第2の回路と、
前記第1の回路に供給される入力信号と前記クロック信号とから前記第2の回路の入力信号を生成して前記第2の回路に供給するキャンセルデータ生成回路と、
を備え、
前記第1の回路と前記第2の回路とにおけるそれぞれの出力回路は、同一に構成され、互いの電源及びグランドが共通であることを特徴とするノイズキャンセル回路。 - 前記第1の回路と前記第2の回路との電源に対しノイズ吸収用のコンデンサを備えることを特徴とする請求項1記載のノイズキャンセル回路。
- 前記第1の回路と前記第2の回路とにおけるそれぞれの出力回路には、同一の負荷が接続されることを特徴とする請求項1記載のノイズキャンセル回路。
- 前記第1の回路の出力回路は、平衡型の出力信号を出力する回路であることを特徴とする請求項1〜3のいずれか一に記載のノイズキャンセル回路。
- 前記キャンセルデータ生成回路は、
前記クロック信号の一方のエッジで前記第1の回路の入力信号をラッチする第1のフリップフロップ回路と、
前記一方のエッジで前記キャンセルデータ生成回路の出力信号をラッチする第2のフリップフロップ回路と、
前記第1の回路の入力信号と前記第1のフリップフロップ回路の出力信号とを入力する第1の排他論理和回路と、
前記第1の排他論理和回路の出力の論理反転信号と前記第2のフリップフロップ回路の出力信号とを入力して前記第2の回路に供給する出力信号を出力する第2の排他論理和回路と、
を備えることを特徴とする請求項1記載のノイズキャンセル回路。 - 請求項1〜5のいずれか一に記載のノイズキャンセル回路を複数備えることを特徴とするデータ送受信装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004133614A JP4464189B2 (ja) | 2004-04-28 | 2004-04-28 | ノイズキャンセル回路 |
US11/115,326 US7332930B2 (en) | 2004-04-28 | 2005-04-27 | Noise canceller circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004133614A JP4464189B2 (ja) | 2004-04-28 | 2004-04-28 | ノイズキャンセル回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005318264A JP2005318264A (ja) | 2005-11-10 |
JP4464189B2 true JP4464189B2 (ja) | 2010-05-19 |
Family
ID=35186447
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004133614A Expired - Fee Related JP4464189B2 (ja) | 2004-04-28 | 2004-04-28 | ノイズキャンセル回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7332930B2 (ja) |
JP (1) | JP4464189B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10630292B1 (en) | 2017-06-29 | 2020-04-21 | Panasonic Intellectual Property Management Co., Ltd. | Noise cancelling circuit and data transmission circuit |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7548174B2 (en) * | 2007-10-04 | 2009-06-16 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | System and method for equalizing transition density in an integrated circuit |
JP6134536B2 (ja) | 2012-02-28 | 2017-05-24 | 株式会社メガチップス | 出力装置 |
CN106797354B (zh) * | 2014-10-16 | 2020-06-09 | 索尼公司 | 发射器和通信*** |
JP7027322B2 (ja) | 2016-10-19 | 2022-03-01 | ソニーセミコンダクタソリューションズ株式会社 | 信号処理装置、信号処理方法、並びにプログラム |
JP2018082328A (ja) | 2016-11-17 | 2018-05-24 | 東芝メモリ株式会社 | データ送信装置 |
FR3101215B1 (fr) * | 2019-09-23 | 2022-06-17 | Macom Tech Solutions Holdings Inc | Flux de données complémentaire pour réduction du bruit |
US11409691B2 (en) | 2020-12-19 | 2022-08-09 | Macom Technology Solutions Holdings, Inc. | High speed on die shared bus for multi-channel communication |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3012276B2 (ja) | 1990-04-09 | 2000-02-21 | 沖電気工業株式会社 | 出力回路 |
EP0793380A2 (en) * | 1996-02-29 | 1997-09-03 | Kabushiki Kaisha Toshiba | A noise cancelling circuit for pixel signals and an image pickup device using the noise cancelling circuit |
JP3080038B2 (ja) | 1997-07-07 | 2000-08-21 | 日本電気株式会社 | 半導体集積回路 |
JP3927294B2 (ja) * | 1997-10-03 | 2007-06-06 | 株式会社ルネサステクノロジ | 半導体装置 |
US6573756B2 (en) * | 2001-07-31 | 2003-06-03 | Intel Corporation | Active noise-canceling scheme for dynamic circuits |
-
2004
- 2004-04-28 JP JP2004133614A patent/JP4464189B2/ja not_active Expired - Fee Related
-
2005
- 2005-04-27 US US11/115,326 patent/US7332930B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10630292B1 (en) | 2017-06-29 | 2020-04-21 | Panasonic Intellectual Property Management Co., Ltd. | Noise cancelling circuit and data transmission circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2005318264A (ja) | 2005-11-10 |
US7332930B2 (en) | 2008-02-19 |
US20050242841A1 (en) | 2005-11-03 |
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