JP4424020B2 - 半導体装置の実装構造および実装方法 - Google Patents
半導体装置の実装構造および実装方法 Download PDFInfo
- Publication number
- JP4424020B2 JP4424020B2 JP2004069930A JP2004069930A JP4424020B2 JP 4424020 B2 JP4424020 B2 JP 4424020B2 JP 2004069930 A JP2004069930 A JP 2004069930A JP 2004069930 A JP2004069930 A JP 2004069930A JP 4424020 B2 JP4424020 B2 JP 4424020B2
- Authority
- JP
- Japan
- Prior art keywords
- connection pad
- semiconductor device
- solder
- circuit board
- solder ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
図1はこの発明の第1実施形態としての半導体装置を回路基板上に実装した状態の断面図を示し、図2は図1に示す回路基板の一部の平面図を示し、図3は図2のIII−IIIに沿う部分に相当する断面図を示す。半導体装置1は、一般的にCSPと呼ばれるもので、シリコン等からなる半導体基板2を備えている。
図8はこの発明の第2実施形態における回路基板の一部の平面図を示し、図9は図8のIX−IX線に沿う部分に相当する断面図を示し、図10は図8のX−X線に沿う部分に相当する断面図を示す。この第2実施形態において、上記第1実施形態の場合と異なる点は、回路基板13の上面に、接続パッド14の側縁および配線15の接続パッド近傍部15aの配線幅方向の両側縁から離間した位置に縁部を有する開口部17が形成されたソルダーレジスト層16を設けた点である。この場合も、ソルダーレジスト層16の開口部17内は半田ボール12によって完全に埋められている。
2 半導体基板
3 接続パッド
9 再配線
10 柱状電極
11 封止膜
12 半田ボール
13 回路基板
14 接続パッド
15 配線
16 ソルダーレジスト層
17 開口部
Claims (6)
- 外部接続用電極を有する半導体装置を、接続パッドを有する回路基板上に、前記外部接続用電極の表面に設けられた半田ボールを前記接続パッドに接合して、フェースダウン実装した半導体装置の実装構造において、前記回路基板上に、前記接続パッドの側縁から離間した位置に縁部を有する、前記接続パッドより大きな開口部が形成された絶縁膜が設けられ、前記絶縁膜の開口部内が前記半田ボールによって充填されており、前記半田ボールは、その断面の直径が、前記外部接続用電極の表面付近において、前記外部接続用電極の表面から離れるにしたがって漸次大きくなっていることを特徴とする半導体装置の実装構造。
- 請求項1に記載の発明において、前記回路基板上に、前記接続パッドの側縁および前記接続パッドに接続された配線の前記接続パッドの近傍における部分の配線幅方向の両側縁から離間した位置に縁部を有する開口部が形成された絶縁膜が設けられ、前記絶縁膜の開口部内が前記半田ボールによって充填されていることを特徴とする半導体装置の実装構造。
- 請求項2に記載の発明において、前記絶縁膜はソルダーレジストからなることを特徴とする半導体装置の実装構造。
- 請求項2に記載の発明において、前記接続パッドは平面円形状であることを特徴とする半導体装置の実装構造。
- 外部接続用電極を有する半導体装置を、接続パッドを有する回路基板上に、前記外部接続用電極の表面に設けられた半田ボールを前記接続パッドに接合して、フェースダウン実装した半導体装置の実装方法において、前記回路基板上に、前記接続パッドの側縁から離間した位置に縁部を有する、前記接続パッドより大きな開口部を有するソルダーレジスト層を形成し、前記半導体装置の外部接続用電極の表面に設けられた半田ボールを前記回路基板の接続パッド上に搭載して、リフローにより前記半田ボールを前記接続パッドに接合し、前記半田ボールによって前記ソルダーレジスト層の開口部内を埋めることを特徴とする半導体装置の実装方法。
- 請求項5に記載の発明において、前記ソルダーレジスト層を、前記回路基板上に、前記接続パッドの側縁および前記接続パッドに接続された配線の前記接続パッドの近傍における部分の配線幅方向の両側縁から離間した位置に縁部を有する開口部を有するように形成することを特徴とする半導体装置の実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004069930A JP4424020B2 (ja) | 2003-11-10 | 2004-03-12 | 半導体装置の実装構造および実装方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003379548 | 2003-11-10 | ||
JP2004069930A JP4424020B2 (ja) | 2003-11-10 | 2004-03-12 | 半導体装置の実装構造および実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005167176A JP2005167176A (ja) | 2005-06-23 |
JP4424020B2 true JP4424020B2 (ja) | 2010-03-03 |
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JP2004069930A Expired - Fee Related JP4424020B2 (ja) | 2003-11-10 | 2004-03-12 | 半導体装置の実装構造および実装方法 |
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Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100743233B1 (ko) | 2005-07-18 | 2007-07-27 | 엘지전자 주식회사 | 인쇄회로기판의 패드 및 그 제조방법 |
KR101370245B1 (ko) | 2006-05-23 | 2014-03-05 | 린텍 가부시키가이샤 | 점접착제 조성물, 점접착 시트 및 반도체장치의 제조방법 |
KR20080047990A (ko) | 2006-11-27 | 2008-05-30 | 린텍 가부시키가이샤 | 점접착제 조성물, 점접착 시트 및 반도체 장치의 제조방법 |
KR101208028B1 (ko) * | 2009-06-22 | 2012-12-04 | 한국전자통신연구원 | 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지 |
JP2011066040A (ja) * | 2009-09-15 | 2011-03-31 | Casio Computer Co Ltd | 半導体装置の実装構造 |
JP6036513B2 (ja) * | 2013-04-19 | 2016-11-30 | 株式会社デンソー | 車両用電子機器 |
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2004
- 2004-03-12 JP JP2004069930A patent/JP4424020B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2005167176A (ja) | 2005-06-23 |
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