JP4423454B2 - 信号発生装置 - Google Patents
信号発生装置 Download PDFInfo
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- JP4423454B2 JP4423454B2 JP2005245788A JP2005245788A JP4423454B2 JP 4423454 B2 JP4423454 B2 JP 4423454B2 JP 2005245788 A JP2005245788 A JP 2005245788A JP 2005245788 A JP2005245788 A JP 2005245788A JP 4423454 B2 JP4423454 B2 JP 4423454B2
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- JP
- Japan
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- signal
- phase shift
- clock
- phase
- output
- Prior art date
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- 230000010363 phase shift Effects 0.000 claims description 61
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 33
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 15
- 229920005994 diacetyl cellulose Polymers 0.000 description 9
- 230000008859 change Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000002194 synthesizing effect Effects 0.000 description 6
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 4
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 4
- 238000003786 synthesis reaction Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
14 クロック発振回路
16 アンド・ゲート
18 フリップ・フロップ
20 第1チャンネル
22 第2チャンネル
24 位相比較回路
26 第1クロック位相シフト回路
28 第2クロック位相シフト回路
29 スイッチ
30 スイッチ
31 第1乗算器
32 90度位相シフタ
33 第2乗算器
34 加算器
35 分周回路
36 分周回路
38 メモリ
39 プログラマブル・ロジック・デバイス
40 並直列変換回路
41 デジタル・アナログ変換回路
42 インターリーブ・デジタル・アナログ変換回路
44 インターリーブ・デジタル・アナログ変換回路
46 合成回路
48 フリップ・フロップ
50 マルチプレクサ
52 デューティー変更回路
54 アンド・ゲート
Claims (4)
- クロックを受けて複数の位相シフト・クロックを生成する位相シフト手段と、
複数の上記位相シフト・クロックを夫々受け、該位相シフト・クロックを分周した読み出しクロックに従って並列データを読み出し、上記位相シフト・クロックに従って並直列変換して出力信号を発生する複数の信号発生手段と、
上記複数の信号発生手段の上記読み出しクロック間の位相差に応じた位相差信号を生成する位相比較手段と、
上記位相差信号に応じて上記位相シフト手段が生成する上記位相シフト・クロックの位相シフトを制御することにより、上記複数の信号発生手段の上記出力信号間の位相を所望の関係に制御する制御手段とを具える信号発生装置。 - 複数の上記信号発生手段の上記出力信号を合成して出力する合成手段を更に具え、
複数の上記信号発生手段は、上記並列データを上記位相シフト・クロックに従って並直列変換し、デジタル・アナログ変換することによって、上記位相シフト・クロックの周期中の所望区間で所望レベルを有し、他の区間で基準レベルである出力信号を発生し、
上記制御手段は、複数の上記信号発生手段の上記出力信号の上記所望レベルを互いに重複しない位相関係に制御することを特徴とする請求項1記載の信号発生装置。 - 複数の上記信号発生手段の上記出力信号を合成して出力する合成手段を更に具え、
上記制御手段は、上記複数の信号発生手段夫々に供給される上記位相シフト・クロックの位相を互いにずらす制御を行なうことにより、上記複数の信号発生手段の上記出力信号の位相を互いにずらすことを特徴とする請求項1記載の信号発生装置。 - クロックを受けて複数の位相シフト・クロックを生成する位相シフト手段と、
複数の上記位相シフト・クロックを夫々受け、該位相シフト・クロックの周期中の所望区間で所望レベルを有し、他の区間で基準レベルであるアナログの出力信号を記憶されている波形データから上記位相シフト・クロックに従って夫々発生する複数の信号発生手段と、
複数の上記信号発生手段の上記出力信号の上記所望レベルが互いに重複しない位相関係に上記出力信号の位相を制御する制御手段と、
複数の上記信号発生手段の上記出力信号を合成して出力する合成手段とを具え、
上記制御手段は、上記位相シフト手段が生成する上記位相シフト・クロック間の位相を制御することにより、複数の上記信号発生手段の上記出力信号の上記所望レベルを互いに重複しない位相関係に制御することを特徴とする信号発生装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005245788A JP4423454B2 (ja) | 2005-08-26 | 2005-08-26 | 信号発生装置 |
US11/509,265 US7562246B2 (en) | 2005-08-26 | 2006-08-24 | Phase controllable multichannel signal generator |
US12/472,244 US7941686B2 (en) | 2005-08-26 | 2009-05-26 | Phase controllable multichannel signal generator having interleaved digital to analog converters |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005245788A JP4423454B2 (ja) | 2005-08-26 | 2005-08-26 | 信号発生装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007060497A JP2007060497A (ja) | 2007-03-08 |
JP4423454B2 true JP4423454B2 (ja) | 2010-03-03 |
Family
ID=37803249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005245788A Active JP4423454B2 (ja) | 2005-08-26 | 2005-08-26 | 信号発生装置 |
Country Status (2)
Country | Link |
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US (2) | US7562246B2 (ja) |
JP (1) | JP4423454B2 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008224313A (ja) | 2007-03-09 | 2008-09-25 | Yokogawa Electric Corp | 干渉計及び復調器 |
US8610474B2 (en) | 2009-10-15 | 2013-12-17 | Rambus Inc. | Signal distribution networks and related methods |
US9100167B2 (en) * | 2012-11-30 | 2015-08-04 | Broadcom Corporation | Multilane SERDES clock and data skew alignment for multi-standard support |
JP2015046715A (ja) * | 2013-08-27 | 2015-03-12 | 富士通株式会社 | 通信回路及び情報処理装置 |
CN103984809B (zh) * | 2014-04-30 | 2017-04-19 | 浙江大学 | 一种星间时差补偿方法和装置 |
US9503102B2 (en) * | 2014-08-29 | 2016-11-22 | Tektronix, Inc. | Synchronization for multiple arbitrary waveform generators |
CN107800429B (zh) * | 2016-08-31 | 2022-09-30 | 北京普源精电科技有限公司 | 一种具有外触发同步功能的信号发生器及信号产生方法 |
EP3300256B1 (en) * | 2016-09-27 | 2021-06-02 | Rohde & Schwarz GmbH & Co. KG | Method for controlling digital-to-analogue converters and rf transmit circuit arrangement |
US9847787B1 (en) * | 2016-10-31 | 2017-12-19 | Tektronix, Inc. | Independent digital-to-analog converter synchronization |
US9973203B1 (en) * | 2017-06-07 | 2018-05-15 | MACOM Connectivity Solutions, LLC. | High frequency Digital-to-Analog conversion by interleaving without return-to-zero |
US9954547B1 (en) | 2017-08-03 | 2018-04-24 | Macom Connectivity Solutions, Llc | High frequency digital-to-analog conversion by time-interleaving without return-to-zero |
US10516412B1 (en) * | 2018-09-21 | 2019-12-24 | Qualcomm Incorporated | Image calibration for time-interleaved digital-to-analog converter |
US11469876B1 (en) * | 2020-09-25 | 2022-10-11 | Raytheon Company | Trigger to data synchronization of gigahertz digital-to-analog converters |
US11791832B2 (en) * | 2022-01-18 | 2023-10-17 | Nxp B.V. | Timing calibration technique for radio frequency digital-to-analog converter |
US11990911B2 (en) | 2022-03-15 | 2024-05-21 | Qualcomm Incorporated | Clock driver for time-interleaved digital-to-analog converter |
CN115296969B (zh) * | 2022-07-28 | 2023-06-16 | 湖南迈克森伟电子科技有限公司 | 发射码元相位调整方法和*** |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5554945A (en) | 1994-02-15 | 1996-09-10 | Rambus, Inc. | Voltage controlled phase shifter with unlimited range |
US5668982A (en) * | 1995-11-30 | 1997-09-16 | National Semiconductor Corporation | System and method for using a half-clock module to implement computer timing control circuitry |
US6111445A (en) | 1998-01-30 | 2000-08-29 | Rambus Inc. | Phase interpolator with noise immunity |
US6111455A (en) * | 1998-12-30 | 2000-08-29 | International Business Machines Corporation | Method for controlling delays in silicon on insulator circuits |
US6356224B1 (en) | 1999-10-21 | 2002-03-12 | Credence Systems Corporation | Arbitrary waveform generator having programmably configurable architecture |
US6351508B1 (en) * | 1999-11-17 | 2002-02-26 | Transwitch Corporation | Phase/frequency detector for dejitter applications |
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2005
- 2005-08-26 JP JP2005245788A patent/JP4423454B2/ja active Active
-
2006
- 2006-08-24 US US11/509,265 patent/US7562246B2/en active Active
-
2009
- 2009-05-26 US US12/472,244 patent/US7941686B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7562246B2 (en) | 2009-07-14 |
US20090231005A1 (en) | 2009-09-17 |
US20070046349A1 (en) | 2007-03-01 |
US7941686B2 (en) | 2011-05-10 |
JP2007060497A (ja) | 2007-03-08 |
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