JP4406329B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP4406329B2
JP4406329B2 JP2004206632A JP2004206632A JP4406329B2 JP 4406329 B2 JP4406329 B2 JP 4406329B2 JP 2004206632 A JP2004206632 A JP 2004206632A JP 2004206632 A JP2004206632 A JP 2004206632A JP 4406329 B2 JP4406329 B2 JP 4406329B2
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Prior art keywords
protective tape
main surface
semiconductor
semiconductor wafer
semiconductor chip
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JP2004206632A
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JP2006032504A (ja
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恵 山村
哲也 梶
俊秀 神名
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Toshiba Corp
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Toshiba Corp
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Priority to JP2004206632A priority Critical patent/JP4406329B2/ja
Priority to US11/180,636 priority patent/US7274091B2/en
Publication of JP2006032504A publication Critical patent/JP2006032504A/ja
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Description

本発明は、半導体装置の製造方法に係り、特に、薄く加工された半導体チップの裏面に金属膜が設けられた半導体装置の製造方法に関する。
近年、ＩＣカード、ＩＣタグ等に代表されるような薄型パッケージ、或いは半導体チップを積層するＭＣＰ（Multi chip package）に半導体チップを実装することが要求されており、裏面に金属膜を設けた半導体チップにおいても、チップ厚を薄く加工することを要求されている。一方、半導体素子の微細化、高集積化とともに半導体ウエーハ径の大口径化が進み、裏面研磨を含め半導体ウエーハの厚さを薄くし、ダイシングにより半導体チップを個別に分離する半導体裏面処理工程では、半導体ウエーハの厚さを１００μｍ以下に薄くすると、作業及び運搬時でのウエーハ割れや欠けが発生し易い（例えば、特許文献１参照。）。この特許文献１では、薄く加工された半導体ウエーハの裏面に金属電極膜を蒸着する処理工程から、ダイシングする工程の間は、保護テープを貼り付けた状態で、薄く加工された半導体ウエーハを作業及び運搬ができるのでウエーハ割れや欠けの発生を抑制することができる。
ところが、大口径半導体ウエーハの厚さが数十μmから９０μmの場合、作業及び運搬する時に半導体ウエーハに作用する局所的な力により、半導体ウエーハに局所クラックや割れが発生するという問題点がある。また、薄く加工された半導体ウエーハや半導体チップの裏面に金属膜を設ける場合、裏面と金属膜との接合強度を大きくすることが困難であるという問題点がある。更に、薄く加工された半導体ウエーハの裏面に金属膜を形成したウエーハを、例えば、ブレードダイシングでフルカットし半導体チップにする場合、半導体チップの抗折強度が小さくなり、この半導体チップを樹脂封止した樹脂封止半導体装置の信頼性を向上させるのが困難になるという問題点がある。
特開平１０−９２７７８号公報（頁５、図２）
本発明は、薄く加工された半導体チップの裏面に金属膜が設けられ、半導体チップと金属膜が強固に結合された半導体装置の製造方法を提供する。
上記目的を達成するために、本発明の一態様の半導体装置の製造方法は、半導体ウエーハの第１主面に第１の保護テープを貼り付ける工程と、前記第１の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面と相対向する第２主面を研磨して、前記半導体ウエーハの厚さを薄くする工程と、前記半導体ウエーハの第２主面に第２の保護テープを貼り付け、前記第１の保護テープを剥離する工程と、前記第２の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面からダイシングを行い、前記半導体ウエーハを複数の半導体チップに分離する工程と、前記半導体チップの第１主面に第３の保護テープを貼り付け、前記第２の保護テープを剥離する工程と、前記第３の保護テープを貼り付けた状態で、前記半導体チップの第２主面に金属膜を形成する工程とを具備することを特徴とする。
更に、上記目的を達成するために、本発明の一態様の半導体装置の製造方法は、半導体ウエーハの第１主面に第１の保護テープを貼り付ける工程と、前記第１の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面と相対向する第２主面を研磨して、前記半導体ウエーハの厚さを薄くする工程と、前記半導体ウエーハの第２主面に第２の保護テープを貼り付け、前記第１の保護テープを剥離する工程と、前記第２の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面からダイシングを行い、前記半導体ウエーハを複数の半導体チップに分離する工程と、前記半導体チップの第１主面に第３の保護テープを貼り付け、前記第２の保護テープを剥離する工程と、前記第３の保護テープを貼り付けた状態で、前記半導体チップの第１主面と相対向する第２主面にＡｕを含む２元金属膜を形成する工程と、前記第３の保護テープを貼り付けた状態で、前記２元金属膜上にバリア金属膜を積層形成する工程とを具備することを特徴とする。
本発明によれば、薄く加工された半導体チップの裏面に金属膜が設けられ、半導体チップと金属膜が強固に結合された半導体装置の製造方法を提供することができる。
以下本発明の実施例について図面を参照しながら説明する。
まず、本発明の実施例１に係る半導体装置及びその製造方法について、図面を参照して説明する。図１乃至図４は半導体装置の製造工程を示す断面図、図５は薄く加工された半導体チップが樹脂封止された樹脂封止半導体装置を示す断面図である。
まず、図１に示すように、８インチサイズ（２００ｍｍΦ）の半導体ウエーハ、例えば、シリコンウエーハ１の半導体素子形成面（第１主面）２又は表面に、周知の半導体製造プロセスを用いて種々の半導体素子を形成する。次に、半導体素子形成面２に、裏面研磨処理から半導体素子形成面２に設けられた種々の半導体素子を保護する第１の保護テープ３ａを貼り付ける。
続いて、半導体ウエーハ１を真空吸着保持して回転する真空吸着テーブル５と、真空吸着テーブル５に対向して水平移動しながら回転される研削砥石６を備える半導体ウエーハ裏面研削装置２０を用いて、半導体ウエーハ１の半導体素子形成面２と相対向する裏面（第２主面）４を研磨する。この裏面研磨として、まず、第１の保護テープ３ａが貼り付けられた半導体ウエーハ１の半導体素子形成面２を真空吸着テーブル５に装着・真空吸着する。次に、メッシュの粗い研削砥石６を用いて裏面研磨する。続いて、メッシュの細かい、例えば、＃３０００の研削砥石６を用いて裏面研磨し、メッシュの粗い研削砥石６による裏面研磨で発生した微少な破砕層を除去する。この結果、半導体ウエーハ１の裏面４は、ミクロンオーダ乃至それ以下のマクロラフネスとしての面粗さ（Ｒａ）が、例えば、０．０１μｍ以下の鏡面に加工される。
ここで、半導体ウエーハ１の厚さを、９０μｍ以下、例えば、３０μｍに薄く加工する。なお、裏面研磨で発生した微少な破砕層の除去をメッシュの細かい研削砥石６の代わりに、例えば、フッ素系ガスのプラズマを用いたドライエッチングを用いてもよい。また、面粗さ（Ｒａ）の測定は接触式表面形状測定装置を用いているが、レーザ式非接触型表面粗さ計や非接触式表面形状測定装置などを用いてもよい。
次に、図２に示すように、半導体ウエーハ１の裏面４に第２の保護テープ３ｂを貼り付けて、半導体素子形成面２の第１の保護テープ３ａを剥離する。この工程により、半導体ウエーハ１の裏面４に第２の保護テープ３ｂが転写されることになる。続いて、切断ライン８を中心として、ダイシングソー７を用いて半導体ウエーハ１の半導体素子形成面２から裏面４の第２の保護テープ３ｂの一部に達するフルカットダイシング（フルカットブレードダイシングとも表現する）を行い、薄く加工された半導体ウエーハ１を切断して複数の半導体チップ３０に分離する。ここで、半導体ウエーハ１の切断ライン８の位置調整は、半導体素子形成面２に形成された金属配線層或いは半導体素子形成面２に設けられたダイシングラインのエッジを感知して位置決めしている。ダイシングソー７は、裏面チッピングを抑制できる粒度で、且つカーフ幅（ダイシング溝の幅）が狭いものを用いるのが好ましい。
続いて、図３に示すように、複数の半導体チップ３０の半導体素子形成面２に第３の保護テープ３ｃ貼り付けて、複数の半導体チップ３０の裏面４の第２の保護テープ３ｂを剥離する。次に、真空蒸着法等により複数の半導体チップ３０の裏面４に２元金属であるＡｕＳｎ（金錫）膜９を形成する。このＡｕＳｎ膜９は、半導体チップ３０の裏面４と強固な接合を得る目的で設けられたものである。ここで、ＡｕＳｎ膜９中でのＡｕの割合は、３０〜８０％にするのが好ましい。Ａｕの割合がこの範囲外の場合、半導体チップ３０の裏面４とＡｕＳｎ膜９の接合強度が低下する。また、ＡｕＳｎ膜９の代わりにＡｕＧｅ（金ゲルマニウム）膜やＡｕＳｂ（金アンチモン）膜を用いてもよい。この場合、Ａｕの割合を３０〜８０％にするのが好ましい。
続いて、真空蒸着法等によりＡｕＳｎ膜９上にＮｉ膜１０を形成する。このＮｉ膜１０は、半導体チップ３０が樹脂封止される場合、はんだなどのロウ材とＡｕＳｎ膜９間を分離し、反応を防止するバリア金属として機能する。ここで、Ｎｉ膜１０の代わりに、Ｃｒ（クロム）、Ｗ（タングステン）、又はＴｉ（チタン）を用いてもよい。なお、半導体チップ３０の抗折強度を大きくする場合、ＡｕＳｎ膜９を形成する前に、例えば、フッ素系ガスのプラズマを用いたドライエッチングを行い、半導体チップ３０の切断面の微少なチッピング、微少なカケ、破砕層等を除去するのが好ましい。この場合、半導体チップ３０の裏面４とＡｕＳｎ膜９は強固な接合が得られるので、半導体チップ３０の裏面４の面粗さ（Ｒａ）を０．０１μｍ以上に粗くする必要がない。
そして、図４に示すように、複数の半導体チップ３０の裏面４に第４の保護テープ３ｄ貼り付けて、半導体素子形成面２の第３の保護テープ３ｃを剥離する。次に、薄く加工された半導体チップ３０は、薄型樹脂封止半導体装置を形成する実装工程に払い出される。
薄く加工された半導体チップ３０を周知の半導体製造プロセス技術を用いて、樹脂封止した樹脂封止半導体装置４０では、図５に示すように、Ｃｕ（銅）などからなるベッド３２の表面（第１主面）にロウ材としてはんだ３４が設けられている。なお、はんだ３４としては、ＳｎＢｉ系、ＳｎＡｇＣｕＩｎ系、ＳｎＺｎ系、及びＳｎＰｂ系等の共晶はんだのいずれでもよい。また、はんだ３４の代わりに、はんだバンプ、金バンプ、又はＡｕ膜を用いてもよい。
そして、はんだ３４の表面（第１主面）にＮｉ膜１０が設けられ、Ｎｉ膜１０の表面（第１主面）にＡｕＳｎ膜９が設けられ、ＡｕＳｎ膜９の表面（第１主面）に裏面（第２主面）がＡｕＳｎ膜９と接するように半導体チップ３０が設けられている。半導体チップ３０の表面（第１主面）に設けられた端子３１とリード端子３３は、ボンディングワイヤ３６で電気的に接続されている。そして、ベッド３２、半導体チップ３０、はんだ３４、Ｎｉ膜１０、及びボンディングワイヤ３６は、エポキシ樹脂などからなるモールド樹脂３６で樹脂封止されている。
上述したように、本実施例の半導体装置及びその製造方法では、ベッド３２上のはんだ３４と、裏面４の面粗さ（Ｒａ）が０．０１μｍ以下に形成された半導体チップ３０との間にＮｉ膜１０及びＡｕＳｎ膜９が設けられている。そして、半導体チップ３０をマウント、ボンディング、及び樹脂封止する工程での最高温度、例えば、３００℃により、半導体チップ３０の裏面４とＡｕＳｎ膜９、ＡｕＳｎ膜９とＮｉ膜１０、Ｎｉ膜１０とはんだ３２、及びはんだ３２とベッド３２がそれぞれ強固に接合される。このため、半導体チップ３０はベッド３２に強固に接着され、樹脂封止半導体装置４０の特性及び信頼性を向上することができる。
また、半導体ウエーハ１を薄く加工する半導体裏面処理工程において、処理工程の作業及び運搬時に半導体ウエーハ１及び半導体チップ３０の裏面４、或いは半導体素子形成面２に必ず保護テープを貼り付けている。このため、半導体ウエーハ１又は半導体チップ３０の局所クラックや割れを従来よりも大幅に低減することができる。
更に、半導体チップ３０の裏面４にＡｕＳｎ膜９及びＮｉ膜１０を形成する前にダイシングを行っているので、半導体チップ３０の裏面４の微少なチッピング、や微少なカケ等の発生を抑制することができる。
なお、本実施例では、半導体チップ３０を樹脂封止した樹脂封止半導体装置に適用したが、セラミックパッケージ等を用いて、半導体チップ３０を気密封止した気密封止半導体装置にも適用できる。
次に、本発明の実施例２に係る半導体装置の製造方法について、図面を参照して説明する。図６は半導体装置の製造工程を示す断面図である。本実施例では、半導体チップ表面のダイシング部分に浅い溝を設けたことを特徴としている。
以下、実施例１と同一構成部分には、同一符号を付してその部分の説明を省略し、異なる部分のみ説明する。
まず、実施例１と同様な処理手順により裏面研磨を行った後、図６に示すように、半導体ウエーハ１の半導体素子形成面２にレーザグルービングを行い切断ライン８を中心とした浅い溝１１を形成する。ここで、レーザグルービングには、半導体レーザを用いている。なお、レーザグルービングの代わりにカーフ幅の広いダイシングソー７を用いて浅い溝１１を形成してもよい。
次に、切断ライン８を中心として、浅い溝１１よりもカーフ幅の狭いダイシングソー７を用いて半導体ウエーハ１の半導体素子形成面２から裏面４の第２の保護テープ３ｂの一部に達するフルカットダイシングを行い、薄く加工された半導体ウエーハ１を切断して複数の半導体チップ３０に分離する。ここで、ダイシング時のカーフ幅は浅い溝１１よりも狭く形成される。
複数の半導体チップ３０の半導体素子形成面２に第３の保護テープ３ｃ貼り付けて、複数の半導体チップ３０の裏面４の第２の保護テープ３ｂを剥離する工程以降は実施例１と同様なので説明を省略する。なお、上述した製造方法で製造された半導体チップ３０は、表面の両端に浅い溝１１が設けられ、表面が裏面４よりも後退しているので、蒸着時の金属が飛散することはない。
上述したように、本実施例の半導体装置の製造方法では、半導体ウエーハ１を薄く加工する半導体裏面処理工程において、処理工程の作業及び運搬時に半導体ウエーハ１及び半導体チップ３０の裏面４、或いは半導体素子形成面２に必ず保護テープを貼り付けている。このため、実施例１と同じ効果を有する。
また、半導体ウエーハ１の裏面４よりも表面を後退させた形状でダイシングした後に、半導体チップ３０の裏面４にＡｕＳｎ膜9及びＮｉ膜１０を形成しているので、実施例１よりも半導体チップ３０の表面部分への蒸着時の金属の飛散を大幅に低減することができる。
次に、本発明の実施例３に係る半導体装置の製造方法について、図面を参照して説明する。図７は半導体装置の製造工程を示す断面図である。本実施例では、半導体裏面処理工程の工程数を短縮している。
以下、実施例１と同一構成部分には、同一符号を付してその部分の説明を省略し、異なる部分のみ説明する。
まず、実施例１と同様な処理手順により裏面研磨を行った後、図７に示すように、切断ライン８を中心として、ダイシングソー７を用いて、半導体ウエーハ１の裏面４から半導体ウエーハ１の半導体素子形成面２の第１の保護テープ３ａの一部までカットしたフルカットダイシングを行い、薄く加工された半導体ウエーハ１を切断して複数の半導体チップ３０に分離する。
ここで、半導体ウエーハ１の切断ライン８の位置調整は、赤外顕微鏡１２を用いて半導体ウエーハ１の裏面４から半導体素子形成面２に形成された金属配線層或いは半導体素子形成面２に設けられたダイシングラインのエッジを感知して位置決めしている。なお、赤外顕微鏡１１に用いる赤外線の波長（λ）は、シリコンデバイスの場合１３００〜１６００ｎｍの範囲、例えば、１３６０ｎｍを用いるのが好ましい。そして、ダイシングソー７は、チッピングを抑制できる粒度で、且つカーフ幅が狭いものを用いるのが好ましい。
次に、図示していないが第１の保護テープ３ａを貼り付けた状態で、実施例１と同様にＡｕＳｎ膜９、Ｎｉ膜１０を順次形成する。これ以降は実施例１と同様なので説明を省略する。
上述したように、本実施例の半導体装置の製造方法では、半導体ウエーハ１を薄く加工する半導体裏面処理工程において、処理工程の作業及び運搬時に半導体ウエーハ１の半導体素子形成面２に第１の保護テープ３ａを貼り付けている。このため、実施例１と同じ効果を有する。また、半導体ウエーハ１の半導体素子形成面２に第１の保護テープ３ａを貼り付けたまま、ダイシング、ＡｕＳｎ膜９、及びＮｉ膜１０の形成を連続的に行っているので、実施例１よりも工程数を削減することができる。
次に、本発明の実施例４に係る半導体装置の製造方法について、図面を参照して説明する。図８及び図９は半導体装置の製造工程を示す断面図である。本実施例では半導体チップ裏面をウエットエッチングにより粗くしている。
以下、実施例１と同一構成部分には、同一符号を付してその部分の説明を省略し、異なる部分のみ説明する。
まず、実施例１と同様な処理手順によりメッシュの粗い研削砥石６を用いて裏面研磨を行った後、図８に示すように、半導体ウエーハ１を真空吸着して回転する真空吸着テーブル５と、ＨＦ（フッ化水素酸）／ＨＮＯ３（硝酸）系の薬液を半導体ウエーハ１の裏面４に噴射するノズル１３を備える半導体ウエーハ裏面エッチング装置２１を用いて、半導体ウエーハ１の裏面４の裏面研磨で発生した微少な破砕層を除去する。この結果、半導体ウエーハ１の裏面４は、面粗さ（Ｒａ）が０．０５〜０．４μｍに加工される。なお、ＨＦ／ＨＮＯ３系の薬液にＨ２ＳＯ４（硫酸）を添加してもよい。
次に、実施例１と同様な処理手順により薄く加工された半導体ウエーハ１を切断して複数の半導体チップ３０に分離する。続いて、図９に示すように、複数の半導体チップ３０の半導体素子形成面２に第３の保護テープ３ｃ貼り付けて、複数の半導体チップ３０の裏面４の第２の保護テープ３ｂを剥離する。
そして、真空蒸着法等により半導体チップ３０の裏面４にＶ（バナジウム）／Ｎｉ（ニッケル）／Ａｕ（金）の積層金属膜１４を蒸着形成する。Ｖ／Ｎｉ膜は半導体チップ３０とＡｕとの密着性を向上するために設けられたもので、数μｍ以上の膜厚のＡｕよりも比較的薄い、例えば、１００ｎｍの膜厚である。なお、Ｖ／Ｎｉの代わりにＴｉ、ＴｉＮ、ＷＮ、或いはＷＳｉ等を用いてもよく、Ａｕの代わりにＣｕやＷ等を用いてもよい。また、蒸着の代わりにスパッタで形成してもよい。これ以降は実施例１と同様なので説明を省略する。
上述したように、本実施例の半導体装置の製造方法では、半導体ウエーハ１を薄く加工する半導体裏面処理工程において、処理工程の作業及び運搬時に半導体ウエーハ１及び半導体チップ３０の裏面４、或いは半導体素子形成面２に必ず保護テープを貼り付けている。このため、実施例１と同じ効果を有する。
また、半導体ウエーハ１の裏面４の面粗さ（Ｒａ）を０．０５〜０．４μｍにしているので、半導体ウエーハ１の裏面４と積層金属膜１４間を実施例１と同様に強固に接合することができる。
本発明は、上記実施例に限定されるものではなく、発明の趣旨を逸脱しない範囲で、種々、変更してもよい。
例えば、本実施例では、ダイシングソーを用いてフルカットダイシングを行っているが、レーザを用いてフルカットダイシングを行ってもよい。また、実施例２乃至３で詳述した製造方法で形成された半導体チップを樹脂封止した樹脂封止半導体装置は、実施例１と同様に特性及び信頼性を向上することができる。
本発明は、以下の付記に記載されているような構成が考えられる。
（付記１） ベッドの第１主面に設けられたはんだ膜と、前記はんだ膜の第１主面に設けられたバリア金属膜と、前記バリア金属膜の第１主面に設けられたＡｕを含む２元金属膜と、前記２元金属膜の第１主面に設けられ、第１主面と相対向する第２主面が前記２元金属膜と接する半導体チップと、前記半導体チップの第１主面に設けられた端子とリード端子を電気的に接続するボンディングワイヤと、前記半導体チップを樹脂封止するモールド樹脂とを具備する半導体装置。
（付記２） ベッドの第１主面に設けられたはんだ膜と、前記はんだ膜の第１主面に設けられたバリア金属膜と、前記バリア金属膜の第１主面に設けられたＡｕを含む２元金属膜と、前記２元金属膜の第１主面に設けられ、第１主面と相対向する第２主面が前記２元金属膜と接する半導体チップと、前記半導体チップの第１主面に設けられた端子とリード端子を電気的に接続するボンディングワイヤと、前記半導体チップを気密封止するセラミックパッケージとを具備する半導体装置。
（付記３） 半導体ウエーハの第１主面に第１の保護テープを貼り付ける工程と、前記第１の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面と相対向する第２主面を研磨して、前記半導体ウエーハの厚さを薄くする工程と、前記半導体ウエーハの第２主面に第２の保護テープを貼り付け、前記第１の保護テープを剥離する工程と、前記第２の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面からダイシングを行い、前記半導体ウエーハを複数の半導体チップに分離する工程と、前記半導体チップの第１主面に第３の保護テープを貼り付け、前記第２の保護テープを剥離する工程と、前記第３の保護テープを貼り付けた状態で、前記半導体チップの第１主面と相対向する第２主面及び前記ダイシングによる切断面をドライエッチングする工程と、前記第３の保護テープを貼り付けた状態で、前記半導体チップの第１主面と相対向する第２主面にＡｕを含む２元金属膜を形成する工程と、前記第３の保護テープを貼り付けた状態で、前記２元金属膜の第１主面にバリア金属膜を形成する工程とを具備する半導体装置の製造方法。
本発明の実施例１に係る半導体装置の製造工程を示す断面図。 本発明の実施例１に係る半導体装置の製造工程を示す断面図。 本発明の実施例１に係る半導体装置の製造工程を示す断面図。 本発明の実施例１に係る半導体装置の製造工程を示す断面図。 本発明の実施例１に係る薄く加工された半導体チップが樹脂封止された樹脂封止半導体装置を示す断面図。 本発明の実施例２に係る半導体装置の製造工程を示す断面図。 本発明の実施例３に係る半導体装置の製造方法を示す断面図。 本発明の実施例４に係る半導体装置の製造工程を示す断面図。 本発明の実施例４に係る半導体装置の製造工程を示す断面図。
符号の説明
１ 半導体ウエーハ
２ 半導体素子形成面
３ａ 第１の保護テープ
３ｂ 第２の保護テープ
３ｃ 第３の保護テープ
３ｄ 第４の保護テープ
４ 裏面
５ 真空吸着テーブル
６ 研削砥石
７ ダイシングソー
８ 切断ライン
９ ＡｕＳｎ膜
１０ Ｎｉ膜
１１ 浅い溝
１２ 赤外顕微鏡
１３ ノズル
１４ 積層金属膜
２０ 半導体ウエーハ裏面研削装置
２１ 半導体ウエーハ裏面エッチング装置
３０ 半導体チップ
３１ 端子
３２ ベッド
３３ リード端子
３４ はんだ
３５ ボンディングワイヤ
３６ モールド樹脂
４０ 樹脂封止半導体装

Claims (5)

  1. 半導体ウエーハの第１主面に第１の保護テープを貼り付ける工程と、
    前記第１の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面と相対向する第２主面を研磨して、前記半導体ウエーハの厚さを薄くする工程と、
    前記半導体ウエーハの第２主面に第２の保護テープを貼り付け、前記第１の保護テープを剥離する工程と、
    前記第２の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面からダイシングを行い、前記半導体ウエーハを複数の半導体チップに分離する工程と、
    前記半導体チップの第１主面に第３の保護テープを貼り付け、前記第２の保護テープを剥離する工程と、
    前記第３の保護テープを貼り付けた状態で、前記半導体チップの第２主面に金属膜を形成する工程と
    を具備することを特徴とする半導体装置の製造方法。
  2. 前記半導体ウエーハの厚さを薄くする工程の後、前記第１の保護テープを貼り付けた状態で、前記半導体ウエーハの厚さを薄くする工程により発生した破砕層を除去するよう前記第２主面を加工し該第２主面の面粗さを加工前よりも小さくする工程をさらに具備することを特徴とする請求項１記載の半導体装置の製造方法。
  3. 前記半導体チップの第２主面に金属膜を形成する工程は、前記第３の保護テープを貼り付けた状態で前記半導体チップの第１主面と相対向する第２主面にＡｕを含む２元金属膜を形成する工程と、前記第３の保護テープを貼り付けた状態で前記２元金属膜上にバリア金属膜を積層形成する工程とを具備することを特徴とする請求項２記載の半導体装置の製造方法。
  4. 半導体ウエーハの第１主面に第１の保護テープを貼り付ける工程と、
    前記第１の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面と相対向する第２主面を研磨して、前記半導体ウエーハの厚さを薄くする工程と、
    前記半導体ウエーハの第２主面に第２の保護テープを貼り付け、前記第１の保護テープを剥離する工程と、
    前記第２の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面からダイシングを行い、前記半導体ウエーハを複数の半導体チップに分離する工程と、
    前記半導体チップの第１主面に第３の保護テープを貼り付け、前記第２の保護テープを剥離する工程と、
    前記第３の保護テープを貼り付けた状態で、前記半導体チップの第１主面と相対向する第２主面にＡｕを含む２元金属膜を形成する工程と、
    前記第３の保護テープを貼り付けた状態で、前記２元金属膜上にバリア金属膜を積層形成する工程と
    を具備することを特徴とする半導体装置の製造方法。
  5. 半導体ウエーハの第１主面に第１の保護テープを貼り付ける工程と、
    前記第１の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面と相対向する第２主面を研磨して、前記半導体ウエーハの厚さを薄くする工程と、
    前記第１の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面と相対向する第２主面をウエットエッチングによりエッチングする工程と、
    前記半導体ウエーハの第２主面に第２の保護テープを貼り付け、前記第１の保護テープを剥離する工程と、
    前記第２の保護テープを貼り付けた状態で、前記半導体ウエーハの第１主面からダイシングを行い、前記半導体ウエーハを複数の半導体チップに分離する工程と、
    前記半導体チップの第１主面に第３の保護テープを貼り付け、前記第２の保護テープを剥離する工程と、
    前記第３の保護テープを貼り付けた状態で、前記半導体チップの第２主面に積層金属膜を形成する工程と
    を具備することを特徴とする半導体装置の製造方法。
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