KR100893567B1 - 반도체 패키지 제조 방법 - Google Patents
반도체 패키지 제조 방법 Download PDFInfo
- Publication number
- KR100893567B1 KR100893567B1 KR1020070081647A KR20070081647A KR100893567B1 KR 100893567 B1 KR100893567 B1 KR 100893567B1 KR 1020070081647 A KR1020070081647 A KR 1020070081647A KR 20070081647 A KR20070081647 A KR 20070081647A KR 100893567 B1 KR100893567 B1 KR 100893567B1
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- semiconductor chip
- plating
- solder
- semiconductor package
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (2)
- 삭제
- 웨이퍼의 백면에 기저층(300)인 Ti와 Ni을 순차 도금하여, 개개의 칩으로 소잉하는 단계와;소잉된 개개의 칩(100)의 본딩패드와, 리드프레임의 리드(200)간을 신호 교환 가능하게 와이어(500)로 본딩하는 단계와;상기 반도체 칩(100)과 와이어(500)와 리드(200)를 수지(600)로 몰딩하되, 상기 반도체 칩(100)의 저면 및 리드(200)의 저면이 외부로 노출되도록 몰딩하는 단계와;상기 반도체 칩(100)의 저면 및 리드(200)의 저면에 묻은 수지 찌꺼기를 제거하는 디플러시 단계와;상기 리드(200)의 저면에 솔더(400)를 도금하는 동시에 상기 기저층(300)의 Ni 표면에 그라운드를 위한 솔더(400)를 도금하는 단계;를 포함하여 이루어진 것을 특징으로 하는 반도체 패키지 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070081647A KR100893567B1 (ko) | 2007-08-14 | 2007-08-14 | 반도체 패키지 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070081647A KR100893567B1 (ko) | 2007-08-14 | 2007-08-14 | 반도체 패키지 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20090017135A KR20090017135A (ko) | 2009-02-18 |
KR100893567B1 true KR100893567B1 (ko) | 2009-04-17 |
Family
ID=40686001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070081647A KR100893567B1 (ko) | 2007-08-14 | 2007-08-14 | 반도체 패키지 제조 방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100893567B1 (ko) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001156233A (ja) * | 1999-11-24 | 2001-06-08 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JP2002016181A (ja) * | 2000-04-25 | 2002-01-18 | Torex Semiconductor Ltd | 半導体装置、その製造方法、及び電着フレーム |
US20070176293A1 (en) * | 2004-09-08 | 2007-08-02 | Denso Corporation | Semiconductor device having tin-based solder layer and method for manufacturing the same |
US7274091B2 (en) | 2004-07-14 | 2007-09-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing a semiconductor device |
-
2007
- 2007-08-14 KR KR1020070081647A patent/KR100893567B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001156233A (ja) * | 1999-11-24 | 2001-06-08 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JP2002016181A (ja) * | 2000-04-25 | 2002-01-18 | Torex Semiconductor Ltd | 半導体装置、その製造方法、及び電着フレーム |
US7274091B2 (en) | 2004-07-14 | 2007-09-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing a semiconductor device |
US20070176293A1 (en) * | 2004-09-08 | 2007-08-02 | Denso Corporation | Semiconductor device having tin-based solder layer and method for manufacturing the same |
Also Published As
Publication number | Publication date |
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KR20090017135A (ko) | 2009-02-18 |
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