JP4309369B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4309369B2 JP4309369B2 JP2005099239A JP2005099239A JP4309369B2 JP 4309369 B2 JP4309369 B2 JP 4309369B2 JP 2005099239 A JP2005099239 A JP 2005099239A JP 2005099239 A JP2005099239 A JP 2005099239A JP 4309369 B2 JP4309369 B2 JP 4309369B2
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- 239000004065 semiconductor Substances 0.000 title claims description 124
- 238000009792 diffusion process Methods 0.000 claims description 68
- 230000003071 parasitic effect Effects 0.000 description 28
- 230000010355 oscillation Effects 0.000 description 27
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000000758 substrate Substances 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
隣接する2つのMOSトランジスタでは、前記一対のソース拡散層の内の各一方のソース拡散層が互いに隣接し、該互いに隣接するソース拡散層の間にダミーゲート電極が配設され、該ダミーゲート電極が該互いに隣接するそれぞれのソース拡散層と同電位に維持されていることを特徴とする。
11:半導体基板
12:ゲート電極
12a:ダミーゲート電極
13:拡散層
13a:ソース拡散層
13b:ドレイン拡散層
14,14−1,14−2,14−3:トランジスタ
15:第1絶縁層
16a:ソース側第1コンタクト
16b:ドレイン側第1コンタクト
17a:ソース側第1配線
17b:ドレイン側第1配線
18:第2絶縁層
19a:ソース側第2コンタクト
19b:ドレイン側第2コンタクト
20a:ソース側第2配線
20b:ドレイン側第2配線
21:第3絶縁層
31:PMOS側回路
32:NMOS側回路
33:第3コンタクト
34:第3配線
35:第4コンタクト
36:第4配線
37:外部出力配線
60:リングオシレータ
61,61−1,61−2,61−3:インバータ素子
62:インバータ素子の入力端子
63:配線
64:外部出力線
Claims (10)
- それぞれが、ドレイン拡散層と、該ドレイン拡散層を挟んで配設される一対のソース拡散層と、前記ドレイン拡散層と前記一対のソース拡散層との間にそれぞれ配設される一対のゲート電極とを有する複数のMOSトランジスタが列状に配設される半導体装置であって、
隣接する2つのMOSトランジスタでは、前記一対のソース拡散層の内の各一方のソース拡散層が互いに隣接し、該互いに隣接するソース拡散層の間にダミーゲート電極が配設され、該ダミーゲート電極が該互いに隣接するそれぞれのソース拡散層と同電位に維持されていることを特徴とする半導体装置。 - 前記複数のMOSトランジスタの内で列の端部に配設されるMOSトランジスタには、前記一方のソース拡散層に隣接するダミー拡散層と、該ダミー拡散層と前記一方のソース拡散層との間に配設されるダミーゲート電極とが形成される、請求項1に記載の半導体装置。
- 前記互いに隣接するソース拡散層に共通に接続される上部のソース配線は、前記互いに隣接するソース拡散層の合計幅よりも小さな幅を有し、前記ダミーゲート電極の上部に配設される、請求項1又は2に記載の半導体装置。
- 前記ドレイン拡散層の上部には、前記ソース配線と同層に形成されており、前記ドレイン拡散層よりも狭い幅のドレイン配線が配設される、請求項3に記載の半導体装置。
- 前記ドレイン配線の上部には、前記ドレイン配線に接続され、前記ドレイン拡散層よりも狭い幅の第2のドレイン配線が形成される、請求項4に記載の半導体装置。
- 前記ゲート電極と前記ダミーゲート電極とから成る電極集合に含まれる各電極が、互いに等しい幅を有し、且つ、等間隔に配設されている、請求項1〜5の何れか一に記載の半導体装置。
- 前記ゲート電極とダミーゲート電極とを含む電極集合に含まれる各電極の電極間の間隔と電極幅との比が4.1未満である、請求項1〜6の何れか一に記載の半導体装置。
- 複数列状に配設される複数のMOSトランジスタが複数列にわたって配列されており、第1列のMOSトランジスタがPMOSトランジスタであり、該第1列に隣接する第2列のMOSトランジスタがNMOSトランジスタであり、前記第1列及び第2列にそれぞれ配設され且つ行方向に並ぶ2つのMOSトランジスタがCMOS回路に接続される、請求項1〜7の何れか一に記載の半導体装置。
- 前記PMOSトランジスタのドレイン拡散層と、対応するNMOSトランジスタのドレイン拡散層とが行方向に延びるドレイン配線で接続されており、該ドレイン配線の端部が、前記ドレイン拡散層の行方向の端部よりも内側にある、請求項8に記載の半導体装置。
- 複数行のCMOS回路が、リングオシレータとして接続されている、請求項8又は9に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005099239A JP4309369B2 (ja) | 2005-03-30 | 2005-03-30 | 半導体装置 |
US11/391,286 US8026536B2 (en) | 2005-03-30 | 2006-03-29 | Semiconductor device having a dummy gate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005099239A JP4309369B2 (ja) | 2005-03-30 | 2005-03-30 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006278952A JP2006278952A (ja) | 2006-10-12 |
JP4309369B2 true JP4309369B2 (ja) | 2009-08-05 |
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Family Applications (1)
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---|---|---|---|
JP2005099239A Active JP4309369B2 (ja) | 2005-03-30 | 2005-03-30 | 半導体装置 |
Country Status (2)
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US (1) | US8026536B2 (ja) |
JP (1) | JP4309369B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4586843B2 (ja) * | 2007-11-15 | 2010-11-24 | ソニー株式会社 | 半導体装置 |
US7932563B2 (en) * | 2009-01-30 | 2011-04-26 | Xilinx, Inc. | Techniques for improving transistor-to-transistor stress uniformity |
US9123565B2 (en) | 2012-12-31 | 2015-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Masks formed based on integrated circuit layout design having standard cell that includes extended active region |
US9887209B2 (en) | 2014-05-15 | 2018-02-06 | Qualcomm Incorporated | Standard cell architecture with M1 layer unidirectional routing |
US9607988B2 (en) * | 2015-01-30 | 2017-03-28 | Qualcomm Incorporated | Off-center gate cut |
US9397179B1 (en) * | 2015-02-17 | 2016-07-19 | Samsung Electronics Co., Ltd. | Semiconductor device |
CN107316861B (zh) * | 2016-04-27 | 2020-10-16 | 株式会社村田制作所 | 半导体装置 |
US10692808B2 (en) | 2017-09-18 | 2020-06-23 | Qualcomm Incorporated | High performance cell design in a technology with high density metal routing |
JP7268408B2 (ja) * | 2019-03-06 | 2023-05-08 | ユナイテッド・セミコンダクター・ジャパン株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4851892A (en) * | 1987-09-08 | 1989-07-25 | Motorola, Inc. | Standard cell array having fake gate for isolating devices from supply voltages |
JPH0997885A (ja) * | 1995-09-28 | 1997-04-08 | Denso Corp | ゲートアレイ |
JP2000216263A (ja) | 1999-01-22 | 2000-08-04 | Nec Corp | 電界効果トランジスタを使用する半導体回路 |
JP3758876B2 (ja) * | 1999-02-02 | 2006-03-22 | Necマイクロシステム株式会社 | 半導体装置のレイアウト方法 |
US7170115B2 (en) * | 2000-10-17 | 2007-01-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method of producing the same |
JP2003133417A (ja) * | 2001-10-26 | 2003-05-09 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置及びその設計方法 |
JP3577057B2 (ja) * | 2002-03-29 | 2004-10-13 | 株式会社東芝 | 半導体記憶装置 |
JP4778689B2 (ja) * | 2004-06-16 | 2011-09-21 | パナソニック株式会社 | 標準セル、標準セルライブラリおよび半導体集積回路 |
JP4578878B2 (ja) * | 2004-07-27 | 2010-11-10 | パナソニック株式会社 | 半導体集積回路 |
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2005
- 2005-03-30 JP JP2005099239A patent/JP4309369B2/ja active Active
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2006
- 2006-03-29 US US11/391,286 patent/US8026536B2/en active Active
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US20060220066A1 (en) | 2006-10-05 |
US8026536B2 (en) | 2011-09-27 |
JP2006278952A (ja) | 2006-10-12 |
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