JP4307300B2 - Method for hole-filling plating of base material having fine holes and / or fine grooves - Google Patents
Method for hole-filling plating of base material having fine holes and / or fine grooves Download PDFInfo
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本発明は、微細孔および/または微細溝を有する基材の孔埋めめっき方法に関し、更に詳細には、異なった径や幅あるいは深さの微細な孔や溝を有する半導体デバイス用の基材を電解めっきで短時間に孔埋めすることのできる方法を提供するものである。 The present invention relates to a method for hole-filling plating of a substrate having fine holes and / or fine grooves, and more particularly, to a substrate for a semiconductor device having fine holes and grooves having different diameters, widths or depths. The present invention provides a method capable of filling a hole in a short time by electrolytic plating.
半導体ウエハー面には、微細孔および/または微細溝(以下、「配線溝」という)で配線パターンが形成されるが、従来この配線溝を埋める配線材料としては、アルミニウムまたはアルミニウム合金が用いられていた。 しかしながら、配線パターンの集積度が高くなるにつれて電流密度が増加し、温度上昇やこれに伴う熱応力が生じる。 そして、これらの現象は配線材料として利用されたアルミニウムやアルミニウム合金にストレスマイグレーションやエレクトロマイグレーションによる断線等の問題が無視できなくなっていた。 このような問題を回避する手段としては、配線材料であるアルミニウム等への銅の添加や、高融点金属との積層化が行われているが、十分なものとはいえなかった。 A wiring pattern is formed with fine holes and / or fine grooves (hereinafter referred to as “wiring grooves”) on the semiconductor wafer surface. Conventionally, aluminum or an aluminum alloy is used as a wiring material for filling the wiring grooves. It was. However, as the integration density of the wiring pattern increases, the current density increases, resulting in a temperature rise and accompanying thermal stress. In these phenomena, problems such as stress migration and disconnection due to electromigration cannot be ignored in aluminum and aluminum alloys used as wiring materials. As means for avoiding such a problem, addition of copper to aluminum as a wiring material or lamination with a refractory metal has been performed, but it has not been sufficient.
そこで、通電による発熱を抑制するため、アルミニウムより導電性の良い配線材料を用いて配線溝を埋めることが検討されている。 アルミニウムより比抵抗の低い材料としては、銅や銀が挙げられるが、このうち銀は高価で、強度や耐食性が低く、しかも構成原子が拡散しやすいという欠点を有する材料であるため、新しい配線材料として銅や、銅合金に注目が集まっている。 Therefore, in order to suppress heat generation due to energization, it has been studied to fill the wiring groove with a wiring material having better conductivity than aluminum. Copper and silver are examples of materials having a lower specific resistance than aluminum. Of these, silver is expensive, has low strength and corrosion resistance, and has the disadvantages that constituent atoms are easy to diffuse. Attention has been focused on copper and copper alloys.
従来、半導体ウエハー面に形成された配線溝にアルミニウム等を埋め込むために行われる方法(以下、「ダマシン法」という)としては、スパッタリング成膜とケミカルドライエッチングを組み合わせて用いる方法がとられてきた。 しかし、この方法は、スパッタリング成膜でアスペクト比(深さと直径または幅の比)の高い配線用の微細溝または微細孔への金属の充填、埋込が困難であり、また、銅や銅合金に対するケミカルエッチングも技術的に確立されていないという問題点があり、実用化は困難であると判断されるものである。 Conventionally, as a method (hereinafter referred to as “damascene method”) for embedding aluminum or the like in a wiring groove formed on a semiconductor wafer surface, a method using a combination of sputtering film formation and chemical dry etching has been used. . However, this method is difficult to fill and embed metal in fine grooves or fine holes for wiring with high aspect ratio (ratio of depth to diameter or width) by sputtering film formation, and copper and copper alloys There is also a problem that chemical etching is not technically established, and it is judged that practical use is difficult.
一方、ダマシン法における微細な配線溝への金属の埋込手法としては、CVD法が知られているが、この方法は析出金属層中に有機原料由来の炭素の混入が避けられないという欠点のあるものであった。 On the other hand, a CVD method is known as a method for embedding a metal in a fine wiring trench in the damascene method. However, this method has a disadvantage that carbon derived from an organic raw material cannot be avoided in the deposited metal layer. There was something.
このように、従来のダマシン法は、高集積度を目的として銅または銅合金を利用する場合には適用することができず、別の手法の開発が求められていた。 Thus, the conventional damascene method cannot be applied when copper or a copper alloy is used for the purpose of high integration, and development of another method has been demanded.
最近、銅または銅合金を半導体ウエハー上の微細な配線溝に埋め込む方法(以下、「銅ダマシン法」という)として、めっき法が注目されている。 銅の電気めっき法は、プロセスコストが低く、成膜速度が速いという長所もあるが、その反面、電析中に気泡が発生することがあり、この気泡が電析面に付着したままになった場合には、この部分がボイド(空孔)になってしまうという問題があった。 Recently, a plating method has attracted attention as a method of embedding copper or a copper alloy in a fine wiring groove on a semiconductor wafer (hereinafter referred to as “copper damascene method”). The copper electroplating method has the advantages of low process cost and high film formation speed, but on the other hand, bubbles may be generated during electrodeposition, and these bubbles remain attached to the electrodeposition surface. In such a case, there is a problem that this portion becomes a void.
例えば、通常の定電流でめっきした場合、0.5A/dm2以上では、析出速度ははやいが径や巾が0.3μm以下の孔や溝は、めっきで完全に充填される前に、その入口付近が先に塞がり、孔や溝中にボイド(空孔)が発生する危険が大きい。一方、0.5A/dm2より低い電流にすれば微細孔を充填することはできるが、大きい孔を埋めるのに著しく時間を要し、生産効率上好ましくない。 For example, when plating with a normal constant current, at 0.5 A / dm 2 or more, a hole or groove having a rapid deposition rate but a diameter and width of 0.3 μm or less is not completely filled before plating. There is a high risk that the vicinity of the entrance is closed first and voids (holes) are generated in the holes and grooves. On the other hand, if the current is lower than 0.5 A / dm 2 , the fine holes can be filled, but it takes much time to fill the large holes, which is not preferable in terms of production efficiency.
またパルスめっきも提案されているがDCパルスは、大電流を流すためボイドを生じやすい。PRパルスは条件によってはボイドを防ぐことはできるが、添加剤使用浴では、その条件設定が一定にしづらいばかりか接点切れを起こす危険もあるほか、ボイド側にもめっきがつくためザラを生じやすく、好ましくない。 Although pulse plating has also been proposed, DC pulses tend to cause voids because a large current flows. The PR pulse can prevent voids depending on the conditions, but in the additive bath, it is difficult to set the conditions constant, and there is a risk of contact breakage. It is not preferable.
このような事情から、特別の電気的設備を必要とせず、簡単に、微細な溝あるいは孔に対し、ボイドの発生を防ぎながら効率よく銅めっきを行ない、基材上の配線溝を孔埋めする方法の開発が求められていた。 For this reason, no special electrical equipment is required, and copper plating is efficiently performed while preventing the generation of voids in fine grooves or holes, thereby filling the wiring grooves on the substrate. There was a need to develop a method.
本発明者は、電気めっき条件とボイドの発生の関係について数多くの試験を行い、検討していたところ、最初に低電流でめっきを行い、配線溝の内部まで金属を析出させた後に電流を上げた場合は、孔や溝の入り口付近が塞がりにくく、ボイドもほとんど発生しないことを見出し、本発明を完成した。 The present inventor conducted a number of tests on the relationship between electroplating conditions and the occurrence of voids. After conducting plating at a low current and depositing metal into the wiring trench, the current was increased. In this case, it has been found that the vicinity of the entrance of the hole or groove is not easily blocked, and voids are hardly generated, and the present invention has been completed.
すなわち本発明は、配線溝を有する基材上に、最初に低電流で短時間のめっきを行い、次いで電流を上げ、所定の膜厚までめっきすることを特徴とする配線溝を有する基材の孔埋めめっき方法である。 That is, the present invention provides a substrate having a wiring groove characterized by first performing plating for a short time at a low current on a substrate having a wiring groove, then increasing the current and plating to a predetermined film thickness. This is a hole filling plating method.
本発明方法は1種類の金属めっき液で異なった孔径や溝径の配線溝を簡単に金属めっきで充填できる点に大きなメリットがあり、金属ダマシン法として利用できるものである。 The method of the present invention has a great advantage in that wiring grooves having different hole diameters and groove diameters can be easily filled with metal plating with one kind of metal plating solution, and can be used as a metal damascene method.
本発明方法は、銅や銀等の高電導性金属イオンを含む金属めっき浴を準備し、常法によって配線溝を有する基材を導電化した後、最初に1段目のめっきとして、ごく低電流で短時間めっきし、径の小さい孔や溝の中まで金属を析出させた後に電流を上げ、大きい孔を埋め、所定の膜厚までめっきすることにより実施される。 In the method of the present invention, after preparing a metal plating bath containing highly conductive metal ions such as copper and silver and conducting a substrate having a wiring groove by a conventional method, the first step of plating is extremely low. Plating is performed for a short time with an electric current, and after depositing a metal into a hole or groove having a small diameter, the current is increased, the large hole is filled, and plating is performed to a predetermined film thickness.
本発明方法の対象となる配線溝を有する基材の好ましい例としては、径或いは巾が0.3μm以下の微細孔あるいは微細溝と、それ以上の径や巾の微細孔や微細溝を有する基材である。このような基材の例としては、ロジックLSIシリコンウエハー等が挙げられる。 As a preferable example of a substrate having a wiring groove that is an object of the method of the present invention, a substrate having a fine hole or fine groove having a diameter or width of 0.3 μm or less and a fine hole or fine groove having a diameter or width larger than that is used. It is a material. An example of such a substrate is a logic LSI silicon wafer.
また、高電導性金属イオンを含む金属めっき浴としては、ダマシン法においてアルミニウムに代わりうる電導性の良い金属であれば特に制約はないが、銅や銀のめっき浴が好ましく、経済性の面からは特に銅が好ましい。 In addition, the metal plating bath containing highly conductive metal ions is not particularly limited as long as it is a metal having good conductivity that can be substituted for aluminum in the damascene method, but a copper or silver plating bath is preferable, from the viewpoint of economy. Is particularly preferably copper.
本発明方法において、最初のめっきは、平均陰極電流密度0.03〜0.5A/dm2程度の低電流で、10秒〜10分間程度の時間行うことが好ましい。 また、その後のめっきは、金属めっき浴の一般的な条件範囲で良く、例えば0.5〜10A/dm2程度の電流密度でめっきすることができる。なお、後のめっきは、必ずしも一定の電流条件で行う必要はなく、電流密度を複数段あるいは連続的に上昇させて実施しても差し支えない。 In the method of the present invention, the first plating is preferably performed at a low current of about an average cathode current density of about 0.03 to 0.5 A / dm 2 for a time of about 10 seconds to 10 minutes. Further, subsequent plating may in general terms the scope of the metal plating bath, for example, be plated with 0.5~10A / dm 2 about the current density. The subsequent plating is not necessarily performed under a constant current condition, and may be performed by increasing the current density in a plurality of stages or continuously.
次に実施例を挙げ、本発明を更に詳しく説明するが、本発明はこれら実施例になんら制約されるものではない。 EXAMPLES Next, although an Example is given and this invention is demonstrated in more detail, this invention is not restrict | limited at all by these Examples.
実 施 例 1
硫酸銅めっき浴による孔埋めめっき:
(1)孔径0.13〜0.25μm、深さ0.5μmの孔、孔径0.5〜1.0μm、深さ0.5μmの孔、溝幅0.13〜0.25μm、深さ0.5μmの溝および溝幅0.5〜1.0μm、深さ0.5μmの溝を有するシリコンウエハーの基材を、常法により導電化した後、下記の硫酸銅めっき浴1を用い、銅めっきを施した。
Example 1
Hole filling plating with copper sulfate plating bath:
(1) A hole having a hole diameter of 0.13 to 0.25 μm and a depth of 0.5 μm, a hole diameter of 0.5 to 1.0 μm, a hole having a depth of 0.5 μm, a groove width of 0.13 to 0.25 μm, and a depth of 0 A silicon wafer substrate having a groove of 0.5 μm, a groove width of 0.5 to 1.0 μm, and a depth of 0.5 μm was made conductive by a conventional method, and then the copper sulfate plating bath 1 described below was used to make a copper Plating was applied.
初めの5分間は平均0.1A/dm2でめっきし、次いで、1A/dm2で5分間めっきして、平坦部でトータル1100nmの銅めっきを析出させた。この基材を孔および溝を含むようにFIBで切断し、その断面をFE−SEMで観察したところ、ボイドの発生はなく孔や溝は全て、銅めっきで充填されていた。更に平均部で測定した銅めっきの体積抵抗率は、1.9μΩ・cmと良好であった。 Plating was performed at an average of 0.1 A / dm 2 for the first 5 minutes, followed by plating at 1 A / dm 2 for 5 minutes to deposit a total of 1100 nm of copper plating on the flat portion. When this base material was cut with FIB so as to include holes and grooves and the cross section was observed with FE-SEM, no voids were generated and all the holes and grooves were filled with copper plating. Furthermore, the volume resistivity of the copper plating measured at the average part was as good as 1.9 μΩ · cm.
( 硫酸銅めっき浴 1 )
硫酸銅五水塩 75 g/l
硫 酸 180 g/l
塩 酸 0.14 ml/l
(塩素イオンとして60mg/l)
添 加 剤* 5 ml/l
浴 温 28 ℃
* Cu−Brite THS(荏原ユージライト(株)製)
(Copper sulfate plating bath 1)
Copper sulfate pentahydrate 75 g / l
Sulfuric acid 180 g / l
Hydrochloride 0.14 ml / l
(60 mg / l as chloride ion)
Additive * 5 ml / l
Bath temperature 28 ℃
* Cu-Brite THS (available from Ebara Eugene Corporation)
(2)下記の硫酸銅めっき浴2を用い、上記(1)で用いたのと同じ基板に硫酸銅めっきを行った。 めっきは、初めの1分間は0.05A/dm2の電流密度で、次の1分間は0.1A/dm2で、更に次の1分は0.2A/dm2で、最後の2分は2A/dm2で行なった。 この結果、平坦部でトータル900nmの銅めっきがついた。 (2) Using the following copper sulfate plating bath 2, copper sulfate plating was performed on the same substrate used in (1) above. Plating at a current density of 0.05 A / dm 2 for 1 minute in the beginning, the following 1 minute 0.1 A / dm 2, and more following 1 minute 0.2 A / dm 2, the last two minutes Was performed at 2 A / dm 2 . As a result, a total of 900 nm of copper plating was applied to the flat portion.
上記(1)と同様に断面観察を行った結果、0.13μmφでアスペクト比4の孔、0.6μm径の孔と、同じ巾の溝の全てがボイドなく良好に充填されていた。 更に、銅皮膜の体積抵抗率は、1.85μΩ・cmであった。 As a result of cross-sectional observation in the same manner as in (1) above, 0.13 μmφ, aspect ratio 4 holes, 0.6 μm diameter holes, and all grooves with the same width were filled well without voids. Furthermore, the volume resistivity of the copper film was 1.85 μΩ · cm.
( 硫酸銅めっき浴 2 )
硫酸銅五水塩 200 g/l
硫 酸 60 g/l
塩 酸 0.14 ml/l
(塩素イオンとして60mg/l)
添 加 剤* 5 ml/l
浴 温 25 ℃
* Cu−Brite THS(荏原ユージライト(株)製)
(Copper sulfate plating bath 2)
Copper sulfate pentahydrate 200 g / l
Sulfuric acid 60 g / l
Hydrochloride 0.14 ml / l
(60 mg / l as chloride ion)
Additive * 5 ml / l
Bath temperature 25 ℃
* Cu-Brite THS (available from Ebara Eugene Corporation)
実 施 例 2
ピロリン酸銅めっき浴による孔埋めめっき:
有機添加剤を全く含まない、下記のピロリン酸銅めっき浴を用い、実施例1の(1)と同じ基板に銅めっきを行った。 めっきは、初めの30秒間は、0.2A/dm2の電流密度で、次の30秒は0.5A/dm2で、更にその後30秒かけて2A/dm2まで電流を上げ、そのまま2分間めっきした。 この結果、平坦部でトータル約1100nmの銅めっきが析出した。
Example 2
Hole filling plating with copper pyrophosphate plating bath:
Copper plating was performed on the same substrate as (1) of Example 1 using the following copper pyrophosphate plating bath containing no organic additive. Plating was performed at a current density of 0.2 A / dm 2 for the first 30 seconds, 0.5 A / dm 2 for the next 30 seconds, and then increased to 2 A / dm 2 over 30 seconds. Plated for minutes. As a result, a total of about 1100 nm of copper plating was deposited on the flat portion.
実施例1の(1)と同様に断面観察した結果、基材の有していた0.15〜1.0μmまでの孔や溝は全て充填されており、ボイドは認められなかった。 また、銅めっき被膜の体積抵抗率は、2.0μΩ・cmと良好な値であった。
なお市販の有機添加剤を併用した場合もほぼ同様な優れた孔埋めめっきが得られた。
As a result of observing the cross section in the same manner as in (1) of Example 1, all the holes and grooves from 0.15 to 1.0 μm that the substrate had were filled, and no voids were observed. Further, the volume resistivity of the copper plating film was a good value of 2.0 μΩ · cm.
When a commercially available organic additive was used in combination, almost the same excellent hole filling plating was obtained.
( ピロリン酸銅めっき浴 )
ピロリン酸銅三水塩 90 g/l
ピロリン酸カリウム 340 g/l
アンモニア水(28%) 3 ml/l
浴 温 55 ℃
pH 8.5
(Copper pyrophosphate plating bath)
Copper pyrophosphate trihydrate 90 g / l
Potassium pyrophosphate 340 g / l
Ammonia water (28%) 3 ml / l
Bath temperature 55 ° C
pH 8.5
比 較 例 1
実施例1の(2)で用いた硫酸銅めっき浴2を使用し、実施例1(2)で用いたのと同じ基材を2A/dm2で3分間めっきした。 平坦部でのめっき厚は、約1200nmで、体積抵抗率は、1.85μΩ・cmであった。
Comparative Example 1
Using the copper sulfate plating bath 2 used in (2) of Example 1, the same substrate as used in Example 1 (2) was plated at 2 A / dm 2 for 3 minutes. The plating thickness at the flat portion was about 1200 nm, and the volume resistivity was 1.85 μΩ · cm.
めっき後の断面をFE−SEMで観察した結果、0.6μm径、巾以上の孔や溝は良好に埋まっていたが、0.13μmφの孔や0.2μm角・アスペクト比4の孔には、孔の中心部から入口にかけてボイドを生じているものが多く観察された。 また、0.1A/dm2でめっきを行った場合は、ボイドがみられなかったが、めっき厚を必要量得るには、60分以上のめっき時間がかかった。 As a result of observing the cross section after plating with an FE-SEM, holes and grooves with a diameter of 0.6 μm and a width or more were well filled. However, 0.13 μmφ holes and 0.2 μm square holes with an aspect ratio of 4 Many voids were observed from the center of the hole to the inlet. In addition, when plating was performed at 0.1 A / dm 2 , no void was observed, but it took 60 minutes or more of plating time to obtain the required amount of plating thickness.
比 較 例 2
実施例2と同じピロリン酸銅浴を用い、実施例1の(1)と同じ基板に1A/dm2で5分間めっきし、平坦部で約1000nmの銅めっきを得た。 この銅めっき被膜の体積抵抗率は2.0μΩ・cmであった。
Comparative Example 2
Using the same copper pyrophosphate bath as in Example 2, the same substrate as (1) in Example 1 was plated at 1 A / dm 2 for 5 minutes to obtain a copper plating of about 1000 nm on the flat part. The volume resistivity of this copper plating film was 2.0 μΩ · cm.
断面観察の結果、0.5μmφ以上の孔は、シームはあるものの良好に埋まっていたが、0.15〜0.3μmφまでの孔は、孔の中心部から入口にかけて、細長い形状のボイドが多く観察された。 As a result of cross-sectional observation, holes with a diameter of 0.5 μmφ or more were satisfactorily filled with seams, but holes with a diameter of 0.15 to 0.3 μmφ had many elongated voids from the center of the hole to the entrance. Observed.
Claims (12)
The method of filling a substrate with a fine hole and / or fine groove according to claim 9 or 10, wherein the plating bath contains an additive.
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JP4307408B2 (en) * | 2005-05-18 | 2009-08-05 | 株式会社荏原製作所 | Method for hole-filling plating of base material having fine holes and / or fine grooves |
JP5000941B2 (en) * | 2006-07-27 | 2012-08-15 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP5089322B2 (en) * | 2007-10-04 | 2012-12-05 | 株式会社野毛電気工業 | Via filling method |
JP5134339B2 (en) | 2007-11-02 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor integrated circuit device |
JP5362500B2 (en) * | 2009-09-18 | 2013-12-11 | 富士通株式会社 | Manufacturing method of semiconductor device |
JP5767154B2 (en) * | 2012-04-13 | 2015-08-19 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP5749302B2 (en) * | 2013-08-20 | 2015-07-15 | 株式会社荏原製作所 | Plating method |
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JPH05243730A (en) * | 1992-03-03 | 1993-09-21 | Hitachi Chem Co Ltd | Manufacture of printed wiring board |
JPH1098268A (en) * | 1996-09-24 | 1998-04-14 | Oki Electric Ind Co Ltd | Method for plating columnar conductor and multi-layered printed wiring board obtained by it |
JP3694594B2 (en) * | 1998-09-03 | 2005-09-14 | 株式会社荏原製作所 | Method for hole-filling plating of substrate having fine holes and / or fine grooves |
JP4307408B2 (en) * | 2005-05-18 | 2009-08-05 | 株式会社荏原製作所 | Method for hole-filling plating of base material having fine holes and / or fine grooves |
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