TWI376433B - Method of direct plating of copper on a substrate structure - Google Patents

Method of direct plating of copper on a substrate structure Download PDF

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TWI376433B
TWI376433B TW095138839A TW95138839A TWI376433B TW I376433 B TWI376433 B TW I376433B TW 095138839 A TW095138839 A TW 095138839A TW 95138839 A TW95138839 A TW 95138839A TW I376433 B TWI376433 B TW I376433B
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Taiwan
Prior art keywords
layer
copper
barrier
substrate
plating
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TW095138839A
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Chinese (zh)
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TW200732518A (en
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Aron Rosenfeld
Hooman Hafezi
Hua Chung
John Dukovic
Lei Zhu
Nicolay Kovarsky
Renren He
Zhi-Wen Sun
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Applied Materials Inc
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Priority claimed from US11/255,368 external-priority patent/US20070125657A1/en
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34—Pretreatment of metallic surfaces to be electroplated
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/615—Microstructure of the layers, e.g. mixed structure
    • C25D5/617—Crystalline layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

1376433 九、發明說明： 【發明所屬之技術領域】 本發明之實施例大體上是關於藉由電化學電鐵沉積 屬層的方法，且特別是關於直接電鍍銅層至阻障成黏著 上的方法》 金 層1376433 IX. Description of the Invention: [Technical Field of the Invention] Embodiments of the present invention generally relate to a method of depositing a layer by electrochemical electric iron, and in particular, a method for directly plating a copper layer to a barrier to adhesion Gold layer

【先前技術】 對目前與未來的積體電路製程而言’次西分之 (sub-quarter)微米尺寸之特徵結構的金層化乃為基礎 術。在一些元件中（例如極大型積體電路元件’即具有數 萬邏輯閘極構成之積體電路的元件），位於元件核心之多 内連線通常是以導電材料（例如銅或鋁）填充高深寬比 内連線特徵结構而形成。傳統上，沉積技術（如化學氣相 積（chemical vapor deposition ; CVD)與物理氣相’’几 (physical vapor deposition ； PVD))已用於填充内連線特 結構。然而隨著内連線尺寸變小與元件特徵結構之深寬 增加，使用傳統金屬化技術來無孔隙（void-free)填充内 線特徵結構變得非常困難。因此在積體電路製造過程中 電鍍技術（如電化學電鍍（ECP)與無電電鍍）成為可實行 填充次四分之一微米尺寸之高深寬比内連線特徵結構的 程。 ECP製程可有效將導電材料(例如銅)填入形成於基 表面中的^分之*~微米尺寸之高深寬比内連線特徵結 内。大部分的町製程通常為二階段製程，其中種晶層 技 百 層 之 沉積 徵 比連 於製材 構 先 5 1376433 形成於基材表面的特 行）’接者將基材表面 偏壓施加於基材與電 待電至基材表面的 應，以還原金屬離子 晶層上而形成膜層。 徵結構上（此步驟可在獨立系統中 的特徵結構暴露於電解液中，同時 解液中的陽極之間。電解液一般富 離子。故施加電偏壓可驅動還原 並沈澱金屬。沈澱時，金屬電鍍至[Prior Art] Gold stratification of the sub-quarter micron-sized feature structure for the current and future integrated circuit processes is fundamental. In some components (such as a very large integrated circuit component 'that is an component of an integrated circuit composed of tens of thousands of logic gates), the plurality of interconnects at the core of the component are usually filled with a conductive material (such as copper or aluminum). The aspect ratio is formed by the inner wiring characteristic structure. Traditionally, deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been used to fill interconnect structures. However, as the interconnect size becomes smaller and the depth of the component features increases, it becomes very difficult to fill the inner feature with void-free using conventional metallization techniques. Thus, in the fabrication of integrated circuits, electroplating techniques, such as electrochemical plating (ECP) and electroless plating, have become the process of filling the high aspect ratio interconnect features of the sub-quarter micron size. The ECP process effectively fills a conductive material (e.g., copper) into a high-aspect-ratio interconnect feature formed in the base surface. Most of the processing in the town is usually a two-stage process, in which the deposition of the seed layer is more specific than that of the material structure 5 1376433 formed on the surface of the substrate. The material and the electricity to be electrolyzed to the surface of the substrate to reduce the metal ion crystal layer to form a film layer. In the structure (this step can be exposed to the electrolyte in the independent system, and at the same time between the anodes in the solution. The electrolyte is generally rich in ions. Therefore, the application of an electrical bias can drive the reduction and precipitation of the metal. Metal plating to

隨著現今微電子元件的關鍵尺寸微缩至〇1微诗 下，銅内連線的製程要求已越來越嚴苛。因此傳統電鸯 程將無法滿足未來内連線技術的需求。一般電鍍的實勒 括利用物理氣相沉積（pVD)、化學氣相沉積（CVD)或原^ 沉積（atomic layer deposition; ALD)來沉積銅種晶層屋 散阻障層（例如钽或氮化鈕）上。然而，利用pvD技術通 會在尚深寬比之特徵結構底部附近形成非連續的島狀銅 塊，因此PVD技術極難用於階梯覆蓋（step c〇verage ) 晶層。對P VD技術而言，為了於特徵結構整個深度中形As the critical dimensions of today's microelectronic components shrink to less than one microsecond, the process requirements for copper interconnects have become more stringent. Therefore, traditional power systems will not be able to meet the needs of future interconnect technology. Generally, electroplating is performed by using physical vapor deposition (pVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) to deposit a copper seed layer barrier layer (such as germanium or nitride). Button). However, the use of pvD technology leads to the formation of discontinuous island-shaped copper blocks near the bottom of the feature structure of the aspect ratio, so PVD technology is extremely difficult to use for step c〇verage layers. For P VD technology, in order to shape the entire depth of the feature structure

連續的側壁覆蓋，其通常會在外圍形成較厚的銅層（如大 200埃），以致特徵結構之入口部在其側壁完成覆蓋前已 封閉。對CVD技術而言，因配位前驅物難以完全移淨， 銅的純度通常仍存有疑慮。ALD技術雖然可進行保 (conformal)沉積且與阻障層間有良好的黏著性，但其 以在側壁上沉積連續銅膜層而使其具有足夠厚度以作為 晶層的沉積速度非常低。 由於傳統阻障材料（例如组或氮化组）通常會於整個 面形成絕緣的原生氧化物’因此很難在阻障材料上進行 實 電 含 反 種 以製 包 層 擴常 結 種 成 於 先 故 型 用種 表 直 6 1376433 接電鍍。並且在電鍍的過程中，導電阻障材料（例如鈷）一 般會在接近自由銅離子的還原電位氡化。故在電鍍銅層時 阻障層的完整性可能會受到危害。A continuous sidewall covering typically forms a thicker copper layer (e.g., 200 angstroms) at the periphery such that the entrance portion of the feature is closed before its sidewalls are covered. For CVD technology, the purity of copper is often still a concern because the coordination precursor is difficult to completely remove. Although ALD technology can perform conformal deposition and has good adhesion to the barrier layer, it deposits a continuous copper film layer on the sidewall to have a sufficient thickness to deposit as a crystal layer. Since conventional barrier materials (such as groups or nitrided groups) usually form insulating native oxides over the entire surface, it is difficult to perform real-life reaction on the barrier material to make the cladding expansion. The type is connected to the plate with a straight table 6 1376433. Also, during the electroplating process, the conductive barrier material (e.g., cobalt) is generally decomposed at a reduction potential close to free copper ions. Therefore, the integrity of the barrier layer may be compromised when plating a copper layer.

PVD為沉積銅種晶層的較佳技術，且已知無電電鍍技 術可用於沉積種晶層至鈕或氮化钽阻障層。然這些技術仍 面臨多項問題，例如銅種晶層與阻障層間的黏著性不佳、 完整之無電電鍍系統所增添的複雜度、及相關製程控制的 困難度。此外，對3 2至4 5奈米尺寸的小型内連線特徵結 構而言，最好是無間斷地進行種晶層之沉積和填充間隙， 以免在種晶層上形成氧化物或其他污染物。再者，黏著性 佳的種晶層具有數個優點，例如其可避免阻障層遭電鍍塊 體銅層時所用之酸液的破壞。另外，銅種晶層可支持接續 沉積之塊體銅層而減少銅層自阻障層上脫落。銅層的黏著 性對製造電子元件來說是很重要的，其可防止元件的特徵 結構在後續的化學機械研磨（CMP)製程受到破壞。阻障層 與接續沉積之銅層間若具有良好的黏著性，還可避免元件 因應力遷移（stress migration)而失效。應力遷移失效是 高度局部化的分層不足，其發生於電子元件之與正常使用 相關連的熱循環（thermal cycling)過程中。熱循環會產生孔 隙，長時間後孔隙會相互接合而形成失效點。因此，銅層 與阻障層間的黏著性對製造電子元件來說是很重要的考量 因素。 此技藝中決定沉積膜層之黏著性的常用方法包括膠帶 拉力測試（t a p e p u 11 t e s t )或”拉力測試’’、和刻劃影線測 7 1376433PVD is a preferred technique for depositing a copper seed layer, and electroless plating techniques are known to deposit a seed layer to a button or tantalum nitride barrier layer. However, these technologies still face many problems, such as poor adhesion between the copper seed layer and the barrier layer, the added complexity of the complete electroless plating system, and the difficulty of related process control. In addition, for a small interconnect characteristic of 3 2 to 45 nm, it is preferable to carry out the deposition and filling gap of the seed layer without interruption to avoid formation of oxides or other contaminants on the seed layer. . Furthermore, the well-adhesive seed layer has several advantages, for example, it can avoid the destruction of the acid layer used when the barrier layer is plated with the copper layer. In addition, the copper seed layer can support the successive deposition of the bulk copper layer to reduce the copper layer from falling off the barrier layer. The adhesion of the copper layer is important for the manufacture of electronic components that prevent the features of the components from being destroyed in subsequent chemical mechanical polishing (CMP) processes. If the barrier layer has good adhesion to the successively deposited copper layer, it can also prevent the component from failing due to stress migration. Stress migration failure is a highly localized stratification that occurs during the thermal cycling of electronic components associated with normal use. Thermal cycling creates voids that open up to each other to form a failure point. Therefore, the adhesion between the copper layer and the barrier layer is an important factor for the manufacture of electronic components. Common methods in this art that determine the adhesion of a deposited film layer include a tape pull test (t a p e p u 11 t e s t ) or a "pull test", and a scribe line test 7 1376433

試（scribe-hatch test)或”劃線測試’，。拉力測試包含附加 勝帶至已沉積待測膜層的基材表面，接著移除膠帶’而未 充分點著於基材的膜層也會被移除。劃線測試屬於此較嚴 格的拉力測試，其中基材表面在加上膠帶前會先刻割十字 凹槽。儘管這些測試僅能稍微定性，但熟諳此技藝者皆知 通過測試的沉積膜層確實於之後不會展顯出相關的黏著問 題，例如在CMP的過程中被拔起、或在使用電子元件的過 程中產生應力遷移失效。未良好黏著於下表面的沉積膜層 照慣例無法通過拉力測試，且甚至可能會自行從下表面剝 落。稍具黏著性的沉積臈層可通過拉力測試，但讦能無法 通過劃線測試》稍具黏著性的沉積膜層亦可能同時通過拉 力測試與劃線測試’但可靠度不佳，例如，沉積膳層可能 只有在基材的特定區域上沒有通過劃線測試、或著其可能 只有在部分基材上沒有通過劃線測試、或著上述兩者皆發 生。故在此之具黏著性的沉積膜層或具”良好黏著性”的沉 積膜層是定義成可破實在基材的所有區域及所有基材上通 過拉力測試與劃線測試的沉積膜或沉積層。 由於其他沉積銅種晶層至阻障層上的方法仍有問題， 因此已考慮直接電鑛鋼層至阻障材料上。在此之”直接電 鍍”是定義為電化學電鍍較具導電性的金屬層（如銅種晶層） 至實質上較不具導電性的膜層（如阻障層或阻障/黏著 層），以利後續均勻且無孔隙沉積溝填（gapfiu)層及/或過填 (overfUl)層。由於傳統限障材料（例如钽或氮化钽）通常會 於整個表面形成絕緣的原生氧化物，因此很難在阻障材料 1376433A scribe-hatch test or a "scribe test". The tensile test consists of attaching the tape to the surface of the substrate on which the film to be tested has been deposited, and then removing the tape's and not sufficiently covering the substrate. Will be removed. The scribing test is part of this more stringent tensile test where the surface of the substrate is first cut into the cross recess before the tape is applied. Although these tests are only slightly qualitative, those skilled in the art are well aware of the test. The deposited film layer does not exhibit relevant adhesion problems afterwards, such as being pulled up during CMP or stress migration failure during the use of electronic components. The deposited film layer that is not well adhered to the lower surface is conventional. It is impossible to pass the tensile test and may even peel off from the lower surface by itself. The slightly adhesive deposit layer can be tested by tensile force, but the flaw can not be tested by scribing. The slightly adhesive deposited layer may also pass the tensile force at the same time. Testing and scribing tests' but the reliability is poor, for example, the deposited layer may not be tested by scribing on specific areas of the substrate, or it may only be in the section The substrate is not tested by scribing, or both. Therefore, an adhesive deposited film layer or a "good adhesion" deposited film layer is defined as being breakable in all areas of the substrate. And deposited films or deposited layers on all substrates by tensile testing and scribing. Since other methods of depositing copper seed layers onto the barrier layer are still problematic, direct electromineral steel layers have been considered to the barrier material. Here, "direct plating" is defined as electrochemically plating a more conductive metal layer (such as a copper seed layer) to a substantially less conductive film layer (such as a barrier layer or a barrier/adhesive layer). In order to facilitate the subsequent uniform and non-porous deposition of the gapfiu layer and/or the overfill (overfUl) layer. Since conventional barrier materials (such as tantalum or tantalum nitride) usually form insulating native oxides on the entire surface, Therefore it is difficult to block material 1764433

上進行直接電鍍。氧化钽會惡化電鍍銅層與阻擇 著性。預電鏟處理（如在還原氣體中進行熱退火及 已試圖用於组系（tantalum-based)阻障層，但絮 臻改善。故直接電鍍銅層依然不良黏著於已經有 來還原其表面之氧化钽的钽系阻障層。此乃因沐 钽表面在電解液中很快即鈍化，如1秒，而黏著 物還來不及形成其上。 因此，需要一種沉積銅種晶層至阻障層或#4 方法。此方法所沉積的銅種晶層應牢牢黏著於其 均勻地分布在整個基材表面。另外，此方法應可 範圍的阻障/黏著層材料，包括鈷、鎢、氮化鎢、 鈦、鈦鎢（Ti-W)合金、鈕、氮化鈕、釕、釕鈕（Ru-錄、把、鐵、錯化銀、給、銳、鉬、及翻。再 或黏著層在沉積種晶層時應具極少或甚至不具 且在沉積時亦不被化學還原。最後，此方法應 鑛浴中依序沉積種晶層和溝填層。 【發明内容】 本發明教示沉積銅種晶層至基材表面的方A 是沉積至阻障層或黏著層上。阻障層或黏著層3 金屬及/或VIII族金屬，或者阻障層為VIII族j 金屬的合金。’’VIII族金屬’’（舊的CAS系統標記 指8、9與10族的元素，如旬"（Ru)、錄、纪、鈷 銀、及钻。财火金屬可包括纽、欽、錯、給、銳 層間的黏 陰極還原） 著性卻未 電鍍處理 經處理的 之銅沉積 著層上的 下膜層且 應用到大 欽、氮化 Ta)合金、 ，阻障層 化反應， 在同一電 •，且一般 '包括耐火 屬與耐火 法）一般意 、鎳、锇、 、雜、鶴、 9 1376433 及其組合物。在一實施例中，合金可由至少50原子〇/0的釕 與衡量的组組成。銅層可直接電鍵至合金上β 方法包括在不含銅離子但含酸的溶液中陰極前處理基 材表面。基材接著置入含有錯合銅離子的中性或鹼性銅溶 液（酸鹼值（ρΗ)^7.0)，而電流或偏壓施加至整個基材表 面。錯合銅離子包括羧酸鹽配位體（如草酸鹽或酒石酸 鹽）、或乙二胺（ED)、乙二胺四乙酸（EdtA)、及/或醋醆鹽。Direct plating is performed on it. Cerium oxide can deteriorate the electroplated copper layer and resistivity. Pre-shovel treatment (such as thermal annealing in reducing gas and attempting to use a tantalum-based barrier layer, but the flocculation is improved. Therefore, the direct electroplated copper layer is still poorly adhered to the surface that has been restored. The lanthanum barrier layer of cerium oxide. This is because the surface of the cerium is quickly passivated in the electrolyte, such as 1 second, and the adhesive is too late to form thereon. Therefore, it is necessary to deposit a copper seed layer to the barrier layer. Or #4 method. The copper seed layer deposited by this method should be firmly adhered to the surface of the substrate uniformly. In addition, this method should cover the range of barrier/adhesive layer materials, including cobalt, tungsten and nitrogen. Tungsten, titanium, titanium-titanium (Ti-W) alloy, button, nitride button, 钌, 钌 button (Ru-record, handle, iron, mis-silver, give, sharp, molybdenum, and turn. or adhesive layer When depositing the seed layer, there should be little or no, and it will not be chemically reduced during deposition. Finally, this method should deposit the seed layer and the trench layer in the ore bath. [Description of the Invention] The present invention teaches the deposition of copper. The square A of the seed layer to the surface of the substrate is deposited on the barrier layer or the adhesive layer. Layer or adhesive layer 3 metal and / or group VIII metal, or barrier layer is alloy of group VIII j metal. ''Group VIII metal'' (old CAS system mark refers to elements of groups 8, 9 and 10, such as "(Ru), Record, Ji, Cobalt, and Drill. The fossil metal may include the bonded cathode reduction between New Zealand, Chin, Wrong, Giving, and Sharp layers.) The uncoated but untreated copper deposited layer The upper film layer is applied to the Daqin, Ta(N) alloy, the barrier stratification reaction, in the same electricity, and generally 'including the fire-resistant genus and fire-resistant method. General meaning, nickel, bismuth, miscellaneous, crane , 9 1376433 and its compositions. In one embodiment, the alloy may be composed of at least 50 atomic 〇/0 钌 and a measured group. The copper layer can be directly bonded to the alloy. The beta method involves pre-treating the surface of the substrate in a solution that does not contain copper ions but contains an acid. The substrate is then placed with a neutral or alkaline copper solution (pH ≤ 7.0) containing copper ions, and a current or bias is applied to the entire substrate surface. The mismatched copper ion includes a carboxylate ligand (e.g., oxalate or tartrate), or ethylenediamine (ED), ethylenediaminetetraacetic acid (EdtA), and/or vinegar salt.

錯合銅離子經還原而沉積銅種晶層至阻障層或黏著層上。 在一實施例中，錯合鹼浴（bath)接著用來電化學電鍍（Ecp) 溝填層至基材表面’然後在同—電鍍浴中形成過填層。在 此實施例中，沉積種晶層、溝填層和過填層的ECp可在同 —製程反應室中進行。在另一實施例中，酸浴用來Ecp溝 填層至基材表面，然後亦在酸性電鍍浴中以ECp形成過填 層。所有實施例的銅電鍍液還可包含一或多種添加化合 物’包括抑制劑、平整劑、光亮劑、及穩定劑。 隹一貫m例The copper ions are deposited by reduction to deposit a copper seed layer onto the barrier layer or the adhesion layer. In one embodiment, a miscible alkali bath is then used to electrochemically plate (Ecp) the trench fill to the substrate surface' and then an overfill layer is formed in the same-electroplating bath. In this embodiment, the ECp for depositing the seed layer, the trench fill layer and the overfill layer can be carried out in the same process chamber. In another embodiment, an acid bath is used to fill the surface of the substrate with an Ecp trench, and then an overfill layer is also formed with ECp in an acid plating bath. The copper plating bath of all of the examples may further comprise one or more additional compounds' including inhibitors, leveling agents, brighteners, and stabilizers.隹 consistent m

/剪开阿火金屬 之合金的阻障層乃浸沒於酸性電鍵浴巾，*達到臨界過電 位成核密度的成核波形則開始施加$阳_ 丨見障層，以形成連續 且保型（conformal )的鋼種晶層。滏拔 屏填波形接著可施加至 基材表面，以電化學電鍍銅溝填層$其 嶒主基材表面。在另—奋 施例中’基材浸沒於含有錯合鋼離子 貝 Y改或驗性鋼溶液 (ρΗ>7·0) ’而電流或偏壓施加至整個就以▲ 固基材表面。錯合銅離 子包括羧酸鹽配位體（如草酸鹽每讲r私 飞'酉石酸鹽）' 或乙二胺 (ED)、乙二胺四乙酸（EDTA)、及/哎萨 次醋酸鹽。錯合銅離子/ Cut the barrier layer of the alloy of A-fire metal is immersed in the acid key bath towel, * The nucleation waveform that reaches the critical overpotential nucleation density begins to apply the $yang_ 丨 see barrier layer to form continuous and conformal (conformal ) The steel seed layer. The screen fill waveform can then be applied to the surface of the substrate to electrochemically plate the copper trench fill layer to the surface of the master substrate. In another embodiment, the substrate is immersed in a solution containing a mismatched steel ion, or a current or bias is applied to the surface of the substrate. The mismatched copper ion includes a carboxylate ligand (such as oxalate per gram of fly 'tartrate)' or ethylenediamine (ED), ethylenediaminetetraacetic acid (EDTA), and /哎萨次Acetate. Misaligned copper ion

10 137643310 1376433

經還原而沉積連續且保型的銅種晶層至阻障層上。溝填波 形接著寸施加至基材表面，以電化學電鍍銅溝填層至基材 表面。在又一實施例中，連續的銅種晶層是藉由上述中性 或鹼性銅溶液來形成於合金之阻障層上，但溝填層是藉由 酸性電鍍液來電鍍至銅種晶層上。在再一實施例中，在進 行電鍍之前，先調整阻障層之表面狀況（condition )以來 改善黏著性與降低電鍍至阻障層的臨界電流密度。調整狀 況之方法可包括在不含銅離子但含酸的溶液中進行陰極前 處理步驟、或在氫氣或氫氣/氦氣混合氣體中進行電漿前處 理步驟。 【實施方式】A continuous and conformal copper seed layer is deposited onto the barrier layer by reduction. The trench fill pattern is applied to the surface of the substrate to electrochemically plate the copper trench to the substrate surface. In still another embodiment, the continuous copper seed layer is formed on the barrier layer of the alloy by the above neutral or alkaline copper solution, but the trench fill layer is electroplated to the copper seed crystal by an acidic plating solution. On the floor. In still another embodiment, prior to plating, the surface condition of the barrier layer is adjusted to improve adhesion and reduce the critical current density of the plating to the barrier layer. The method of adjusting the condition may include performing a cathodic pretreatment step in a solution containing no copper ions but containing an acid, or performing a pre-plasma treatment step in a hydrogen or hydrogen/helium mixed gas. [Embodiment]

本發明教示沉積銅層至基材表面的方法，且一般是沉 積至阻障層或黏著層上。阻障層可包括耐火金屬及/或VIII 族金屬。方法包括在不含銅離子但含酸的溶液中對基材表 面進行陰極前處理。前處理步驟可降低以電化學電鍍（.ECP) 製程形成連續且無孔隙之種晶層至阻障層或黏著層上時所 需的臨界電流密度（critical current density; CCD)。基材 接著置入含有錯合銅離子的中性或鹼性（PH27.0)錯合銅溶 液，而電流或偏壓施加至整個基材表面。在此之”錯合浴 (complex bath)”或”錯合溶液”是指含有至少一錯合或螯合 之化合物與金屬離子源的電鍍液，其中金屬離子源包含待 電鍍至基材的金屬（例如铜）。在此之”鹼性”是定義成 pH27.0。錯合銅離子經還原而沉積連續且無孔隙的銅種晶 11 1376433The present invention teaches a method of depositing a copper layer to the surface of a substrate, and is generally deposited onto a barrier layer or an adhesive layer. The barrier layer may comprise a refractory metal and/or a Group VIII metal. The method involves subjecting the surface of the substrate to a pre-cathode treatment in a solution containing no copper ions but containing an acid. The pre-treatment step reduces the critical current density (CCD) required to form a continuous and void-free seed layer onto the barrier or adhesive layer in an electrochemical plating (.ECP) process. The substrate is then filled with a neutral or alkaline (pH 27.0) mismatched copper solution containing copper ions, and a current or bias is applied to the entire substrate surface. By "complex bath" or "mismatched solution" herein is meant a plating solution containing at least one compound of a mis- or chelation compound and a source of metal ions, wherein the source of metal ions comprises a metal to be electroplated to the substrate. (eg copper). Here, "alkaline" is defined as pH 27.0. Continuously and non-porous copper seed crystals deposited by reduction of copper ions 11 1376433

層至阻障層或黏著層上。在一實施例中，錯合鹼浴接 來電化學電鍍溝填（gapfill)層至種晶層上，然後在酸 鍵浴中電化學電鍍過填（overfill)層。在此實施例中， 層與溝填層之ECP沉積可在同一製程反應室中進行， 佳是使用相同的電鍍液。在另一實施例中，酸性電鍵 用來ECP溝填層至基材表面，然後同樣在酸性電錄浴 行E C P過填步驟。 在一實施例中，於直接電鍍銅層至阻障層上之前 先進行陰極電化學前處理步驟或電漿處理步驟來調整 層表面之狀態（condition)。利用成核電壓脈衝可在酸 解質中電链鋼層至阻障層上、或在含鋼錯合劑的驗浴 行電鍍。 對小於45奈米（nm)的技術而言，利用如化學氣相 (CVD)、原子層沉積（ALD)或物理氣相沉積（PVD)所沉 得的釕（Ru)薄膜可能做為内部金屬介電（IMD)層與鋼 線間的無種晶内層（seedless interlayer)。在此之，，户 是指沉積於介電層與後續沉積之金屬層間的膜層。内 例子包括鋼阻障層、黏著層、及結合之阻障/黏著層。 VIII族金屬，具有相當低的電阻（電阻約— 與高 定性（高炫點〜230 (TC )。釕甚至在含有氧與水的環境溫 亦相當穩定。釕的導熱度與導電度是鈕（Ta)的兩倍。 低於900 °C時亦不與銅形成合金，並與銅具良好的黏著 因此半導體工業有意使用釕做為内層或黏著層。釕之 阻特性尚有助於在無種晶層的情況下來填充銅至覆蓋 著用 性電 種晶 且較 浴為 中進 ，可 阻障 性電 中進 沉積 積而 内連 9層” 層的 釕為 熱穩 度下 釕在 性。 低電 釕的 < S ) 12 1376433The layer is on the barrier layer or the adhesive layer. In one embodiment, a mismatched alkali bath is used to electrochemically plate a gapfill layer onto the seed layer and then electrochemically plate an overfill layer in an acid bath. In this embodiment, the ECP deposition of the layer and the trench fill layer can be carried out in the same process chamber, preferably using the same plating solution. In another embodiment, an acidic bond is used to fill the surface of the substrate with the ECP trench, and then the E C P overfilling step is also performed in the acid electrocalation bath. In one embodiment, a cathodic electrochemical pre-treatment step or a plasma treatment step is performed prior to directly plating the copper layer onto the barrier layer to adjust the condition of the layer surface. The nucleation voltage pulse can be used to electroplate the electric chain steel layer to the barrier layer in the acid or in the bath containing the steel misc. For technologies less than 45 nanometers (nm), ruthenium (Ru) films deposited using, for example, chemical vapor (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) may be used as internal metals. A seedless interlayer between the dielectric (IMD) layer and the steel wire. Here, the household refers to a film deposited between the dielectric layer and the subsequently deposited metal layer. Examples include steel barrier layers, adhesive layers, and bonded barrier/adhesive layers. Group VIII metal, has a relatively low resistance (resistance about - and high qualitative (high dazzle ~ 230 (TC). 钌 even in the temperature of the environment containing oxygen and water is quite stable. The thermal conductivity and conductivity of 钌 is the button ( It is twice as high as Ta). When it is lower than 900 °C, it does not form an alloy with copper, and it adheres well to copper. Therefore, the semiconductor industry deliberately uses ruthenium as an inner layer or an adhesive layer. In the case of the crystal layer, the copper is filled to cover the useful seed crystal and the bath is medium-introduced, and the barrier layer can be deposited in the conductive layer and the inner layer is 9 layers. The layer of germanium is thermally stable. Electric &<S) 12 1376433

特徵結構。然而，釕層通常很薄（1 Ο-1 〇〇埃）且電阻為銅的 3倍以上，因此釕層仍具高的片電阻（sheetresistance)， 例如厚度100埃的釕層之片電阻大於20歐姆/平方。試著 把材料電鍍至具高片電阻之材料將難以形成均勻且無孔隙 的銅層於200毫米與300毫米大小的基材上。此外，釕層 不能單獨當作銅的擴散阻障層。故釕黏著層需搭配傳統钽 系阻障層，以增進銅層黏著性及防止銅離子擴散。但對3 2 至4 5奈米大小的内連線特徵結構而言，個別的黏著層與阻 障層可能會佔用部分的内連線特徵結構，因而影響元件性 能。Feature structure. However, the tantalum layer is usually very thin (1 Ο-1 〇〇) and the resistance is more than three times that of copper, so the ruthenium layer still has a high sheet resistance, for example, a sheet thickness of 100 angstroms is greater than 20 Ohm/square. Trying to plate materials to materials with high sheet resistance will make it difficult to form a uniform, void-free copper layer on substrates of 200 mm and 300 mm. In addition, the tantalum layer cannot be used alone as a diffusion barrier layer for copper. Therefore, the adhesive layer needs to be matched with a conventional barrier layer to enhance the adhesion of the copper layer and prevent the diffusion of copper ions. However, for interconnect features of 3 2 to 45 nanometers, individual adhesive layers and barrier layers may occupy part of the interconnect features and thus affect component performance.

本發明之實施例包括採用結合的阻障/黏著層，其中阻 障/黏著層包含至少 50原子％釕的合金，而合金的剩餘比 例則包含銅的擴散阻障材料，例如钽。在其他實施例中， 合金的阻障材料可為对火金屬，如欽、錯、鈴、鈮、鉬、 鎢、及其組合物。銅黏著層接著可直接電化學電鍍至阻障/ 黏著層上，而不需額外的阻障層或黏著層。其方法將參照 第4、5及6A圖說明如下。在一實施例中，合金為釕與钽 的均質層。在另一實施例中，合金為Ru-Ta合金，且銅種 晶層與阻障/黏著層之間的介面富含釕。在又一實施例中， 合金為Ru-Ta合金，且阻障/黏著層與内部金屬介電層的介 面富含钽。本發明之實施例更包括採用合金的阻障/黏著 層，合金包含至少50原子％的VIII族金屬（除釕外），例如 姥、纪、钻、錦、锇、銥、及钻。 第1 A-1 E圖繪示銅内連線製造流程之各階段的基材剖 13 1376433 面圖，並結合使用VIII族金屬層。第1A.圖為基材丨〇〇的 剖面圖’具有金屬接觸層1〇4與介電層102形成於其上》 基材100可包含半導體材料，如矽、鍺、或砷化鎵D介電 層102可包含絕緣材料，如二氧化矽、氮化梦、氮氧化梦、 及/或摻雜碳之氧化矽（Si 〇xCy，例如註冊商標為黑鑽石 • (BLACK DIAM〇NDtm)之低介電常數材料，其由美國加州 聖克拉拉市的應用材料公司（Applied Materials，jnc )所供 φ 應）。金屬接觸層104可包含銅或其他材料。孔洞120可位 於介電層102中，以提供開口於金屬接觸層1〇4上方。定 義於介電層1 02中的孔洞ι2〇可利用傳統之微影術及蝕刻 • 技術形成。孔洞12〇的寬度可大至約900埃（Α)、小至約 400Α ° "電層1〇2的厚度可介於約1〇〇〇人至約ι〇〇〇〇α之 " 間。 阻障層106亦可為阻障/黏著層，其可形成於介電層 102中的孔洞120内。阻障層1〇6可包括一或多層含耐火 金屬之層，以做為銅阻障材料，例如鈷、鈦、氮化鈦、氮 , 化夺鈦、組、氮化纽、氛化矽鈕、鎢氮化鎢及鈦鎢（Ti W) 合金等。阻障層106可利用適當的沉積製程形成，例如 ALD、CVD或PVD。阻障層1〇6的厚度介於約5入至15〇人 之間’較佳為小於1 〇 〇 A。 如上所述’阻障層1〇6或可包含νπι族金屬薄膜例 如釕（Ru)、釕鈕合金、铑（Rh)、鈀（pd)、餓（〇s)、銥、 及鉑（Pt)。此類νΠΐ族金屬具防腐蝕與抗氧化的性質而 可接續利用電化學電鍍（ECP)沉積鋼層於其表面。νιπ族 14 1376433Embodiments of the invention include the use of a bonded barrier/adhesion layer wherein the barrier/adhesive layer comprises an alloy of at least 50 atomic percent bismuth and the remaining proportion of the alloy comprises a diffusion barrier material of copper, such as germanium. In other embodiments, the barrier material of the alloy can be a fire metal such as chin, sham, bell, samarium, molybdenum, tungsten, and combinations thereof. The copper adhesion layer can then be electrochemically plated directly onto the barrier/adhesive layer without the need for an additional barrier or adhesive layer. The method will be described below with reference to Figures 4, 5 and 6A. In one embodiment, the alloy is a homogeneous layer of tantalum and niobium. In another embodiment, the alloy is a Ru-Ta alloy and the interface between the copper seed layer and the barrier/adhesive layer is rich in bismuth. In yet another embodiment, the alloy is a Ru-Ta alloy and the interface of the barrier/adhesive layer and the inner metal dielectric layer is rich in ruthenium. Embodiments of the invention further include the use of an alloy barrier/adhesive layer comprising at least 50 atomic percent of a Group VIII metal (other than bismuth), such as ruthenium, kiln, diamond, brocade, tantalum, niobium, and drill. Figure 1 A-1 E shows the substrate section 13 1376433 at various stages of the copper interconnect manufacturing process, using a combination of Group VIII metal layers. 1A. is a cross-sectional view of a substrate ' having a metal contact layer 1 〇 4 and a dielectric layer 102 formed thereon. The substrate 100 may comprise a semiconductor material such as germanium, germanium, or gallium arsenide D. The electrical layer 102 may comprise an insulating material such as cerium oxide, nitriding dream, nitroxide dream, and/or carbon doped cerium oxide (Si 〇 x Cy, such as the registered trademark black diamond • (BLACK DIAM 〇 NDtm) Dielectric constant material, supplied by Applied Materials, Jnc, Santa Clara, California, USA). Metal contact layer 104 can comprise copper or other materials. The holes 120 may be located in the dielectric layer 102 to provide openings above the metal contact layer 1〇4. The holes ι2 defined in the dielectric layer 102 can be formed using conventional lithography and etching techniques. The width of the hole 12〇 can be as large as about 900 angstroms (Α), as small as about 400 Α ° " the thickness of the electrical layer 1 〇 2 can be between about 1 〇〇〇 to about ι 〇〇〇〇 α . The barrier layer 106 can also be a barrier/adhesive layer that can be formed in the holes 120 in the dielectric layer 102. The barrier layer 1〇6 may include one or more layers of refractory metal as a copper barrier material, such as cobalt, titanium, titanium nitride, nitrogen, titanium, group, nitride, and button , tungsten tungsten nitride and titanium tungsten (Ti W) alloy. Barrier layer 106 can be formed using a suitable deposition process, such as ALD, CVD, or PVD. The thickness of the barrier layer 1 〇 6 is between about 5 and 15 Å, preferably less than 1 〇 〇 A. As described above, the barrier layer 1〇6 may contain a metal film of a νπι group such as ruthenium (Ru), a ruthenium alloy, rhodium (Rh), palladium (pd), hungry (〇s), ruthenium, and platinum (Pt). . Such ν Πΐ metal has anti-corrosion and anti-oxidation properties and can be subsequently deposited on the surface by electrochemical plating (ECP). Νιπ族 14 1376433

金屬可當作銅阻障層。或者，VIII族金屬可沉積在傳統的 阻障層（例如钽（Ta)及/或氮化钽（TaN))上，以做為傳統阻障 層與後續沉積之銅層間的黏著層或其他内層。VIII族金屬 一般使用CVD、ALD、或PVD來沉積。參照第1B圖，VIII 族金屬内層1〇8(例如釕（Ru))形成於基材上，且在此例中位 於阻障層1 06上。VIII族金屬内層108的厚度通常視欲製 造的元件結構而定。一般來說，VIII族金屬内層108(例如 釕）的厚度小於約1000人，較佳為約5人至約200人。Metal can be used as a copper barrier. Alternatively, the Group VIII metal can be deposited on a conventional barrier layer (such as tantalum (Ta) and/or tantalum nitride (TaN)) as an adhesion layer or other inner layer between the conventional barrier layer and the subsequently deposited copper layer. . Group VIII metals are typically deposited using CVD, ALD, or PVD. Referring to Fig. 1B, a Group VIII metal inner layer 1 〇 8 (e.g., ruthenium (Ru)) is formed on the substrate, and in this case, on the barrier layer 106. The thickness of the Group VIII metal inner layer 108 is generally determined by the structure of the component to be fabricated. Generally, the Group VIII metal inner layer 108 (e.g., tantalum) has a thickness of less than about 1000, preferably from about 5 to about 200.

直接電鍍金屬層（如銅層110)至含純Ta或TaN的阻障 層1 06上已發現無法得到良好的製程結果。電鍍金屬層至 純Ta或TaN之阻障層的問題之一在於，钽非常親氧，因 而在Ta或TaN表面會形成熱力學穩態的氧化層，導致直 接電鍍之金屬層無法良好黏著至Ta或TaN之阻障層1 06。 黏著問題常見於直接電鍍製程，因沉積膜層易從阻障層 106表面脫離或去結合。適合用來移除Ta與TaN之表面氧 化物的傳統方法（例如：水、熱或電漿處理）乃試圖還原 所形成之氧化物，但由於剛露出的表面會很快地再氧化， 故此方法通常不是很有效。 如第1 A-1C圖所示，做為VIII族金屬内層108的Ru-Ta 合金不但如同傳統钽阻障層般可有效阻隔铜擴散，還可提 供適合直接電鍍銅種晶層的表面，且不會發生傳統Ta與 TaN阻障層存有的相同黏著問題。因此根據本發明之一實 施例，阻障層1 0 6包含由約7 0原子％至約9 5原子％之釕與 衡量之組組成的Ru-Ta合金。在另一實施例中，阻障層106 15 (S ) 1376433 較佳為包含由約7 0原子％至約9 0原子％之釕與衡量之钽组 成的Ru-Ta合金。在又一實施例中，阻障層106更佳為包 含由約 8 0原子％至約 9 0原子％之釕與衡量之鈕組成的 Ru-Ta合金。根據一實施例為期望選用表面區域不含純釕 及/或純组的Ru-Ta合金。Direct plating of a metal layer (e.g., copper layer 110) to a barrier layer containing pure Ta or TaN 106 has found that good process results are not obtained. One of the problems of plating a metal layer to a barrier layer of pure Ta or TaN is that the ruthenium is very oxophilic, and thus a thermodynamically stable oxide layer is formed on the surface of Ta or TaN, resulting in the direct plating of the metal layer not adhering well to Ta or TaN. The barrier layer 106. Adhesion problems are common in direct plating processes because the deposited film layer is easily detached or unbonded from the surface of the barrier layer 106. Conventional methods suitable for removing surface oxides of Ta and TaN (eg, water, thermal or plasma treatment) attempt to reduce the oxide formed, but since the exposed surface is quickly reoxidized, this method Usually not very effective. As shown in Fig. 1A-1C, the Ru-Ta alloy as the Group VIII metal inner layer 108 not only effectively blocks copper diffusion like the conventional barrier layer, but also provides a surface suitable for direct plating of the copper seed layer, and The same adhesion problems that exist in the conventional Ta and TaN barrier layers do not occur. Thus, in accordance with an embodiment of the present invention, barrier layer 106 includes a Ru-Ta alloy comprised of a combination of about 70 atomic percent to about 9.5 atomic percent. In another embodiment, the barrier layer 106 15 (S ) 1376433 preferably comprises a Ru-Ta alloy comprising from about 70 atomic percent to about 90 atomic percent of germanium. In still another embodiment, the barrier layer 106 more preferably comprises a Ru-Ta alloy consisting of about 80 atomic percent to about 90 atomic percent of germanium and gauge. According to one embodiment, it is desirable to select a Ru-Ta alloy that does not contain pure tantalum and/or a pure group of surface regions.

在一些實施例中，VIII族金屬内層108也可包含非連 續的銅層，如PVD形成的銅薄層（<10〇A)。此銅層也許不 具導電性，但可做為後續沉積之銅層的成核基點（site)，以 實質降低VIII族金屬内層的有效臨界電流密度（CCD)。In some embodiments, the Group VIII metal inner layer 108 may also comprise a discontinuous copper layer, such as a thin layer of copper formed by PVD (<10〇A). The copper layer may not be electrically conductive, but may serve as a nucleation site for the subsequently deposited copper layer to substantially reduce the effective critical current density (CCD) of the inner layer of the Group VIII metal.

參照第1 C圖，隨後可藉由一或多個直接電鍍製程而 填充銅層110於孔洞120中，以完成銅内連線。直接電鍍 銅可施行於阻障層1 06或VIII族金屬内層1 08上。然而， 為降低電鍍銅至基材表面（即阻障層106或VIII族金屬内 層1 0 8)所需的C C D，本發明之實施例在沉積銅層11 0前， 先進行陰極前處理步驟。臨界電流密度與陰極前處理步驟 將配合第3圖說明於下。本發明之實施例更包含使用不同 的電鍍法來沉積銅層110。 參照第2圖，銅層11 0可包、含多層由不同電化學電鍍 法沉積而得的銅層。為清楚說明，沉積銅層前，基材上的 沉積膜層（如介電層102、金屬接觸層104、阻障層106、 和VIII族金屬内層108)—併繪成第2圖的導電基材表面 114。銅層110可包括薄、實質保型、連續且無孔隙的膜層， 以下稱之為種晶層1 11、溝填層1 1 2、及過填層1 1 3。 在一實施例中，陰極前處理基材表面之後，種晶層1 11 16 1376433 為利用錯合鹼浴與配合第3、5及6圖所述之電鍍法而電化 學電鍵至導電基材表δ 114。溝填層112接著為利用配合 第3、5及6圖所述之錯合鹼浴溝填法或配合第5及6圖所 述之傳統酸浴溝填法而電化學電鍍至種晶層丨^上。在一 實施例中’過填層113然後利用配合第5及6圖所述之酸 浴ECP製程而沉積至溝㈣112上。與電鍵室的 例子將配合第4、5及6圖說明於下。Referring to Figure 1C, the copper layer 110 can then be filled into the holes 120 by one or more direct plating processes to complete the copper interconnect. Direct plating of copper can be performed on the barrier layer 106 or the Group VIII metal inner layer 108. However, in order to reduce the C C D required to electroplate copper to the surface of the substrate (i.e., the barrier layer 106 or the Group VIII metal inner layer 108), embodiments of the present invention perform a cathodic pretreatment step prior to depositing the copper layer 110. The critical current density and cathode pretreatment steps will be described below in conjunction with Figure 3. Embodiments of the invention further include depositing a copper layer 110 using different electroplating methods. Referring to Fig. 2, the copper layer 110 may comprise a plurality of layers of copper deposited by different electrochemical plating methods. For clarity, the deposited film layer on the substrate (such as dielectric layer 102, metal contact layer 104, barrier layer 106, and Group VIII metal inner layer 108) is deposited before the copper layer - and is depicted as the conductive layer of FIG. Material surface 114. The copper layer 110 may comprise a thin, substantially conformal, continuous and void-free film layer, hereinafter referred to as a seed layer 1 11 , a trench fill layer 1 1 2, and an overfill layer 1 13 . In one embodiment, after the surface of the substrate is pretreated by the cathode, the seed layer 1 11 16 1376433 is electrochemically bonded to the conductive substrate by using a mixed alkali bath and the plating method described in FIGS. 3, 5 and 6 δ 114. The trench fill layer 112 is then electrochemically plated to the seed layer by filling with a miscellaneous alkali bath as described in Figures 3, 5 and 6 or by conventional acid bath filling as described in Figures 5 and 6. ^ On. In one embodiment, the overfill layer 113 is then deposited onto the trench (four) 112 using an acid bath ECP process as described in Figures 5 and 6. Examples with the key chamber will be described below in conjunction with Figures 4, 5 and 6.

在另一實施例中，阻障/黏著層1〇6八可形成於介電層 102 t的孔洞12〇内。第115及1E圖為基材1〇〇的剖面圖， 具有金屬接觸層104與介電層102形成於其上。阻障/黏著 層106 A為金屬合金薄膜，其中合金包含至少5〇原子％之 VIII族金屬（例如釕）與衡量之阻障金屬（例如鈕或其他耐 火金屬）。合金是用來提供黏著至介電層1〇2之良好點著 性，並做為銅的擴散阻障層，且使銅後續可直接電鍍於其 上。阻障/點著層i 06 A可利用適當的沉積製程形成，例如 ALD、CVD或PVD。在一較佳實施例中，阻障/黏著層1〇6八 為利用PVD沉積於孔洞120中。阻障/黏著層i〇6a沿著側 壁120a的厚度可為約5A至約50A，較佳為小於約3〇a。 如第1〇及1E圖所示’做為阻障/黏著層ι〇6Α的^-。合 金不但如同傳統鈕阻障層般可有效阻隔鋼擴散還可提供 適合直接電鍍鋼種晶層的表面，且不會引起傳統Ta與TaN 阻障層存有的黏著問題。因此根據本發明實施例，阻 障/黏著層106A包含由約70原子％至約95原子％之釘與衡 量之纽組成的Ru-Ta合金。在另一實施例中，阻障/黏著層 17 1376433 106A較佳為包含由約7〇原子％至約9〇原子％之封與衡量 之钽组成的Ru_ta合金。在又一實施例中，阻障/黏著層 106A更佳為包含由約8〇原子％至約9〇原子％之釘舆衡量 之鈕组成的R_u_Ta合金。根據一實施例為期望選用表面區 域不含純纽的Ru_Ta合金。 P且障/黏著層1〇6A較佳是以PVD形成，如此可沉積出 非均質的Ru-Ta合金層，即可控制、改變合金的濃度分布。 例如，其有助於降低阻障/黏著層1〇6A與銅層11〇(鋼層ιι〇 繪於第1 E圖）之介面的鈕濃度。介面的钽濃度較低可減少 造成銅層110與阻障/黏著層106A黏著不佳的純鈕區域。 其亦有助於提高阻障/黏著層1〇6A與介電層1〇2之介面的 钽濃度，以增進阻障/黏著層i 〇6A阻隔銅擴散的性質。 參照第1 E圖，孔洞丨20隨後可藉由一或多個施行於 阻障/黏著層106 A上的直接電鍍製程而填入銅層11〇，以 完成銅内連線。本發明之實施例包含在直接電鍍前、先調 整阻障/黏著層1〇6Α表面之狀態。調整狀態（c〇ndition)之 方法包括：陰極電化學前處理步驟、和在氫氣或氫氣/氛氣 混合氣體中進行電漿處理步驟。調整阻障/點著層i 〇6 A的 表面狀態可藉由降低臨界電流密度或形成更均勻且密集的 成核現象，而有益於直接電鍍製程。臨界電流密度（ccd) 及其對直接電鍍製程的影響將配合第3圖與針對阻障/黏 著層之陰極電化學前處理的敘述而說明於下。 除了可降低CCD外，調整阻障/黏著層1〇6A的表面狀 態已顯示可改善直接電鍍其上之電鍍鋼層的黏著性。如上 18 1376433 述，經由陰極還原或在還原氣逋中進行熱 傳統组系（tantalum-based)阻障層上的氧 其對於改善電鍍銅層的黏著性係為無效的 合金的陰極電化學前處理已顯示可改善後 黏著性。由此可確信，某種程度地前處理 不只是還原合金表面的氧化鋁，而是較佳 (也許只有單層原子）。在沉積Ru_Ta合金峡 沉積的過程_，可能會形成純钽的結塊或， 區域中形成薄薄的單層）。此起因於PVD争 在父替電聚脈衝時先行沉積合金各成分、 表面、或甚至在濺鍍至基材表面後因金屬 形成類原子聚集。上述任一機制可在名為 上產生純组區域’當鈕接觸大氣時即行氧 在任一情況下，陰極還原已顯示可改 層附著至Ru-Ta合佥表面的黏著性，其中 實無用於傳統Ta與TaN表面。例如，直 之Ru，Ta合金的鋼層僅稍具黏著性，反之 處理後亦潤濕與乾燥合金表面，經陰極電 電鍍銅層仍具良好的黏著性。確信陰極還 Ru-Ta合金表面的理由之一為，合金上產 為混合的Ru-Ta合金，其比氧化钽更易接 某些Ru-Ta合金而言，富含鋥之區域比例 成之黏著銅層的表面上有夠大的鋼成核密 合金的再純化動力夠慢，以維持活化區域 退火處理來還原 化链’已經證實 。反之’ RLh 續電鐘之銷層的 Ru-Ta合金可能 地移除少量的钽 -’尤其是在PVD sj狀物（也許在__ ：·材缺乏均質性、 先行再濺鍍合金 原子的移動性而 均質合金的表面 fb。 善直接電鍍之銅 此類前處理已證 接電鍍至90/10 ’即使在陰極前 化學前處理後的 原可成功應用於 生的氧化物可能 受陰極還原。對 夠小，因此待形 度。或者，Ru-Ta 有足夠的時間來 19 1376433 和缓銅電鐘。In another embodiment, a barrier/adhesion layer 1 can be formed in the via 12 of the dielectric layer 102 t. FIGS. 115 and 1E are cross-sectional views of the substrate 1A with the metal contact layer 104 and the dielectric layer 102 formed thereon. The barrier/adhesive layer 106A is a metal alloy film in which the alloy contains at least 5 atom% of a Group VIII metal (e.g., ruthenium) and a barrier metal (e.g., a button or other fire resistant metal). The alloy is used to provide good adhesion to the dielectric layer 1 and is used as a diffusion barrier for copper, and copper can be subsequently electroplated directly onto it. The barrier/dot layer i 06 A can be formed using a suitable deposition process, such as ALD, CVD or PVD. In a preferred embodiment, the barrier/adhesion layer 1 is deposited in the via 120 using PVD. The barrier/adhesive layer i〇6a may have a thickness along the side wall 120a of from about 5A to about 50A, preferably less than about 3〇a. As shown in Figures 1 and 1E, as a barrier/adhesive layer 〇6Α. The alloy not only effectively blocks the steel diffusion like the traditional button barrier layer, but also provides a surface suitable for direct plating of the steel seed layer without causing adhesion problems in the conventional Ta and TaN barrier layers. Thus, in accordance with an embodiment of the present invention, the barrier/adhesive layer 106A comprises a Ru-Ta alloy consisting of from about 70 atomic percent to about 95 atomic percent of a nail and a gauge. In another embodiment, the barrier/adhesive layer 17 1376433 106A preferably comprises a Ru_ta alloy consisting of a seal of about 7 〇 atom% to about 9 〇 atom%. In still another embodiment, the barrier/adhesive layer 106A is more preferably an R_u_Ta alloy comprising a button of about 8 〇 atom% to about 9 〇 atom%. According to one embodiment, it is desirable to use a Ru_Ta alloy having a surface region that does not contain a pure bond. P and the barrier/adhesive layer 1〇6A are preferably formed by PVD, so that a heterogeneous Ru-Ta alloy layer can be deposited, and the concentration distribution of the alloy can be controlled and changed. For example, it helps to reduce the button concentration of the interface of the barrier/adhesive layer 1〇6A and the copper layer 11〇 (the steel layer is plotted on Fig. 1E). The lower germanium concentration of the interface reduces the area of the button that causes the copper layer 110 to adhere poorly to the barrier/adhesive layer 106A. It also helps to increase the germanium concentration of the interface of the barrier/adhesive layer 1〇6A and the dielectric layer 1〇2 to enhance the barrier property of the barrier/adhesive layer i 〇6A. Referring to Figure 1E, the hole 20 can then be filled into the copper layer 11 by one or more direct plating processes performed on the barrier/adhesion layer 106 A to complete the copper interconnect. Embodiments of the present invention include the state of adjusting the surface of the barrier/adhesive layer 1 〇 6 前 before direct plating. The method of adjusting the state includes a cathodic electrochemical pretreatment step, and a plasma treatment step in a hydrogen or hydrogen/atmosphere gas mixture. Adjusting the surface state of the barrier/dot layer i 〇6 A can be beneficial to the direct plating process by reducing the critical current density or forming a more uniform and dense nucleation phenomenon. The critical current density (ccd) and its effect on the direct plating process will be described in conjunction with Figure 3 and the description of the cathodic electrochemical pretreatment for the barrier/adhesive layer. In addition to lowering the CCD, adjusting the surface state of the barrier/adhesive layer 1 〇 6A has been shown to improve the adhesion of the galvanized steel layer directly electroplated thereon. As described in 18 1376433, the cathodic electrochemical pretreatment of an alloy which is ineffective for improving the adhesion of the electroplated copper layer via cathodic reduction or in a reduction gas tantalum-based barrier layer has been The display improves post-adhesion. From this, it is believed that some degree of pretreatment is not only the reduction of alumina on the surface of the alloy, but rather (perhaps only a single layer of atoms). During the deposition of the Ru_Ta alloy gorge, it is possible to form a pure tantalum agglomerate or a thin monolayer in the region. This is due to the fact that PVD competes for the deposition of alloy constituents, surfaces, or even after sputtering onto the surface of the substrate. Any of the above mechanisms can produce a pure group region on the name. When the button is in contact with the atmosphere, oxygen is applied. In either case, the cathode reduction has been shown to adhere to the adhesion of the Ru-Ta bonded surface, which is not used in the conventional Ta and TaN surfaces. For example, the steel layer of the straight Ru, Ta alloy is only slightly adhesive, and the surface of the alloy is wetted and dried after the treatment, and the copper layer still has good adhesion through the cathode electroplating copper layer. One of the reasons for believing that the cathode is also a Ru-Ta alloy surface is that the alloy is a mixed Ru-Ta alloy which is more accessible to some Ru-Ta alloys than yttrium oxide. The repurification power of a sufficiently large steel nucleation dense alloy on the surface of the layer is slow enough to maintain the activation zone annealing treatment to reduce the chain' has been confirmed. Conversely, the Ru-Ta alloy of the pin layer of the RLh renewed clock may remove a small amount of bismuth--especially in the PVD sj (maybe in the __: material lacking homogeneity, the first re-sputtering of the atomic movement of the alloy) The surface of the homogeneous and homogeneous alloy fb. Good direct plating of copper such pretreatment has been electroplated to 90/10 'Even oxides that can be successfully applied to raw oxides after chemical pretreatment before the cathode may be subject to cathode reduction. It is small enough to be shaped. Or, Ru-Ta has enough time to come to 19 1376433 and a slow copper clock.

亦值得注意的是，阻障/黏著層之前處理無法永久增進 後續電鍍之銅層的黏著性。前處理步驟與直接電鍍步驟若 相隔過久將消除前處理阻障/黏著層的效果。為得良好的黏 著性，應在進行前處理後的150分鐘内將直接電鍍之銅層 電鍍至阻障/黏著層上，且較佳是在約120分鐘内，更佳是 在約2至5分鐘内。前處理步驟與電鍍步驟若相隔約4小 時以上，已顯示將實質減弱已經改善的黏著性。 本發明之實施例更包含用於沉積銅層110之不同電鍍 法。參照第2A圖，銅層110可包含多層由不同電化學電 鍍法沉積而得的銅層。為清楚說明，沉積銅層前，沉積於 基材上的膜層（如介電層 102、金屬接觸層 104、和阻障/ 黏著層106 A)—併繪成第2A圖的導電基材表面114。銅層 1 10可包括薄、實質保型、連續且無孔隙的膜層，以下稱 之為種晶層1 1 1、及溝填層11 2。It is also worth noting that the prior treatment of the barrier/adhesive layer does not permanently enhance the adhesion of the subsequently plated copper layer. If the pre-treatment step is too long compared to the direct plating step, the effect of the pre-treatment barrier/adhesive layer will be eliminated. For good adhesion, the directly plated copper layer should be plated onto the barrier/adhesive layer within 150 minutes of pre-treatment, and preferably within about 120 minutes, more preferably between about 2 and 5. Within minutes. If the pre-treatment step and the electroplating step are separated by about 4 hours or more, it has been shown to substantially weaken the improved adhesion. Embodiments of the invention further include different plating methods for depositing the copper layer 110. Referring to Fig. 2A, the copper layer 110 may comprise a plurality of layers of copper deposited by different electrochemical plating methods. For clarity, the film layer deposited on the substrate (such as dielectric layer 102, metal contact layer 104, and barrier/adhesive layer 106 A) before deposition of the copper layer - and painted as the surface of the conductive substrate of FIG. 2A 114. The copper layer 1 10 may comprise a thin, substantially conformal, continuous and void-free film layer, hereinafter referred to as a seed layer 11 1 , and a trench fill layer 11 2 .

在一實施例中，利用陰極前處理或電漿處理來調整基 材表面狀況後，種晶層11 1為利用錯合鹼浴與配合第3、5 及6A圖所述之電鍍法、或利用配合第5及6A圖所述之傳 統酸浴溝填法，而電化學電鍍至導電基材表面114上。電 化學電鍍（ECP)系統與電鍍室的例子將配合第 4、5及6A 圖說明於下。 在另一實施例中，利用陰極電化學前處理或電漿處理 來調理整基材表面狀態後，種晶層1 11為利用酸性電鍍浴 而電化學電鍍至導電基材表面114上，其中於形成種晶層 20 (S ) 1376433In one embodiment, after the surface pretreatment or the plasma treatment is used to adjust the surface condition of the substrate, the seed layer 11 1 is formed by using the wrong alkali bath and the electroplating method described in the drawings 3, 5 and 6A, or utilizing It is electrochemically plated onto the surface 114 of the conductive substrate in accordance with the conventional acid bath filling method described in Figures 5 and 6A. Examples of electro-chemical plating (ECP) systems and plating chambers will be described in conjunction with Figures 4, 5 and 6A. In another embodiment, after the cathode electrochemical pretreatment or plasma treatment is used to condition the surface state of the entire substrate, the seed layer 11 is electrochemically plated onto the conductive substrate surface 114 by using an acidic plating bath, wherein the formation is performed. Seed layer 20 (S ) 1376433

111時，成核脈衝開始施加到導電基材表面11 4。 種晶層至阻障層的成核脈衝將配合第3圖說明於 層 112接著為利用相同的電鍍浴而電化學電鍍 11 1 上。 電化學電鍍製程與調整狀態步驟 阻障層之陰極前處理 本發明之實施例包含在電化學電鍍銅層至基4 之前，先陰極前處理基材表面。本發明之實施例； 電化學電鍍铜層至Ru-Ta合金上之前，先陰極電巧 理由該合金組成的基材表面。此前處理步驟已證1 電鍵之銅層黏著至合金上。 典型ECP銅種晶層之製程的電鍍電流一般為； 培/平方公分（mA/cm2)至約10mA/cm2，用以填入4 米的溝渠及/或通孔結構，如第1 A-1 C圖所示的孔 然而，使用2-10 mA/cm2的電鍍電流密度已發現¥ 連續的銅層至釕層上，反而會形成孔隙。若提高1 密度及/或降低電解質阻抗而超出傳統銅電鍍製卷 數值，則可於釕層上形成連續的銅層。已確定最λΙ 度或臨界電流密度（CCD)，其中當電鍍電流密度驾 於此值時，將會於釕層上形成連續的銅層，當電袭 度小於此值時，於釕層上將不會形成連續的銅層。 大小與電鍍液的阻抗息息相關。At 111 o'clock, a nucleation pulse is applied to the surface 11 4 of the conductive substrate. The nucleation pulse of the seed layer to the barrier layer will be described in conjunction with Figure 3 for layer 112 followed by electrochemical plating 11 1 using the same electroplating bath. Electrochemical Plating Process and Conditioning Steps Cathodic Pretreatment of the Barrier Layer Embodiments of the invention include pre-cathode pretreatment of the substrate surface prior to electrochemically plating the copper layer to the substrate 4. Embodiments of the invention; prior to electrochemically plating a copper layer onto a Ru-Ta alloy, the surface of the substrate consisting of the alloy is preferred. The previous processing steps have proven that the copper layer of the key is adhered to the alloy. The plating current of a typical ECP copper seed layer process is generally: psi/cm 2 (mA/cm 2 ) to about 10 mA/cm 2 for filling 4 m trenches and/or via structures, such as 1 A-1. Holes shown in Figure C However, using a plating current density of 2-10 mA/cm2, it has been found that a continuous copper layer is on the tantalum layer, which instead forms pores. If the density is increased by 1 and/or the electrolyte resistance is lowered beyond the conventional copper electroplating coil value, a continuous copper layer can be formed on the tantalum layer. The maximum λ 或 or critical current density (CCD) has been determined, where a continuous copper layer will be formed on the ruthenium layer when the plating current density is at this value, and when the electrical attack is less than this value, No continuous copper layer is formed. The size is closely related to the resistance of the plating solution.

第3圖舉例說明CCD與硫酸（H2S04)濃度的I 21 接電鍍 。溝填 種晶層 卜表面上 I包含在 :學前處 &可加強 2毫安 3至次微 洞 120 ° ^法沉積 :鍍電流 .所用的 、電流密 :於或大 [電流密 CCD的 丨係。第 1376433 3圖之CCD定義為於釕層表面形成1000A之連續銅層所需 的最小電流密度。小於CCD時，無法察覺具光澤之連續銅 層沉積到基材的中央區域。CCD的大小與電鍍浴的酸性息 息相關®Figure 3 illustrates the I 21 plating of CCD and sulfuric acid (H2S04) concentrations. Ditch filling seed layer on the surface I is included in: pre-school & can be strengthened 2 mA 3 to sub-micro hole 120 ° ^ deposition: plating current. Used, current density: at or large [current dense CCD 丨system. The CCD of 1376433 is defined as the minimum current density required to form a continuous copper layer of 1000A on the surface of the tantalum layer. When it is smaller than the CCD, it is impossible to detect the deposition of a glossy continuous copper layer to the central region of the substrate. The size of the CCD is related to the acidity of the plating bath®

_般熟知，電沉積的成核與結晶成長動力學與在成核/ 成長基點的區域電化學過電位（over-potential )、和結晶 成長的表面情況密切相關。過電位定義為實際電位與零電 流（開路）電仇的差值。高過電位藉由降低臨界晶核尺寸與 增加晶核密度而傾向成核新的結晶；低電化學過電位則傾 向於在現存的微晶（crystallite)上成長。由於電鍍電流密 度視給定之電鍍浴的電化學過電位而定，故銅沉積的結構/ 形態會受電鍍電流密度影響。另外，成核過程亦視基材表 面的”活性”而定，即基材上的，，活化基點，，濃度。任一種表 面缺陷（如晶格差排、晶格邊界、或摻入的異原子）均可做 為活化基點。在同樣的過電位或同樣的施加電流密度下， 若阻障層未摻雜不需的沉積物（如氧化釕與某些有機化合 物）’將形成較高的晶核量，否則沉積物會阻隔活化基點而 抑制成核。 如同理論所預測及掃瞄式電子顯微鏡（SEM)圖所證 實’具有銅層的基材（銅層是在含有10克/公升（g/Ι)硫 酸之 電鍍液與電鍍電流為3 mA/cm2的條件下電鐘至1 〇〇A之釕 層上）在基材中央區域有較大的微晶與較差的沉積層。電鐘 鋼層於基材邊緣的厚度為1000A。依據第3圖所示的結 果，硫酸濃度為Mg/1時，CCD约為40mA/cm2。3mA/cm2 22 1376433As is well known, the nucleation and crystallization growth kinetics of electrodeposition are closely related to the over-potential of the nucleation/growth point region and the surface condition of crystal growth. The overpotential is defined as the difference between the actual potential and the zero current (open circuit). High overpotentials tend to nucleate new crystals by reducing critical nucleation size and increasing nucleation density; low electrochemical overpotions tend to grow on existing crystallites. Since the plating current density depends on the electrochemical overpotential of the given plating bath, the structure/morphology of the copper deposition is affected by the plating current density. In addition, the nucleation process also depends on the "activity" of the surface of the substrate, i.e., on the substrate, the activation site, and the concentration. Any surface defect (such as lattice difference row, lattice boundary, or incorporated heteroatoms) can be used as the activation base point. At the same overpotential or the same applied current density, if the barrier layer is not doped with unwanted deposits (such as yttria and certain organic compounds), a higher amount of nucleation will be formed, otherwise the deposit will block. The base point is activated to inhibit nucleation. As predicted by theory and confirmed by scanning electron microscopy (SEM), the substrate with copper layer (the copper layer is in a plating solution containing 10 g/liter (g/Ι) sulfuric acid and the plating current is 3 mA/cm2. Under the condition of the electric clock to the layer of 1 〇〇A, there is a large crystallite and a poor deposition layer in the central region of the substrate. The electric clock steel layer has a thickness of 1000 A at the edge of the substrate. According to the results shown in Fig. 3, when the sulfuric acid concentration is Mg/1, the CCD is about 40 mA/cm2. 3 mA/cm2 22 1376433

的電流密度遠低於第3圖的40 mA/cm2 (CCD)，故如預料 地會形成非連續的膜層。一般相信在此電鍍條件下，只有 少數的微晶夠穩定而能作為進一步結晶成長的成核中心， 因此電鍍電流產生的能量基本上是用來成長這些結晶進 而幫助銅吸附原子（adat〇m)快速地表面擴散。故Sem圖顯 示出基材中央區域有大型微晶與島狀的銅沉積物。要在此 條件下於整個基材表面形成連續的銅層，沉積層必須非常 厚’使得沉積層可能含有孔隙，導致其不適合用於鋼内連 線。即使電鍍電流密度僅略低於CCD’仍會發現此種不佳 的沉積層。例如，採用含有60g/l硫酸之電鍍液與電鍵電 流後度為約1 〇 m A / c m2 (略低於1 5 m A / c m的C C D)的條件， 可在基材上形成5〇〇〇A厚的連續銅層於lOOA厚的釕層（由 PVD沉積）上。然一如理論所述，銅/釕介面會有大孔隙。The current density is much lower than the 40 mA/cm2 (CCD) in Figure 3, so a discontinuous film layer is expected as expected. It is generally believed that under this plating condition, only a small number of crystallites are stable enough to serve as a nucleation center for further crystal growth, so the energy generated by the plating current is basically used to grow these crystals and thereby help the copper adsorption atoms (adat〇m). Rapid surface diffusion. Therefore, the Sem diagram shows large crystallites and island-like copper deposits in the central region of the substrate. To form a continuous layer of copper over the entire surface of the substrate under these conditions, the deposited layer must be very thick so that the deposited layer may contain voids, making it unsuitable for use in steel wiring. This poor deposition layer is found even if the plating current density is only slightly lower than that of the CCD'. For example, a plating solution containing 60 g/l of sulfuric acid and a post-current of about 1 〇m A / c m2 (a CCD slightly lower than 15 m A / cm) can be used to form 5 基材 on the substrate. A thick continuous copper layer of 〇A is deposited on a 10A thick layer of tantalum (deposited by PVD). As the theory suggests, the copper/germanium interface will have large pores.

僅藉由提高電鍍電流密度來電锻無孔隙且連續之膜層 至釕内層仍有一些缺點；一般而言，咼電鐘電流密度傾向 於較差的填洞能力。電鍍電流密度小於約10 mA/cm2已發 現可促進由下往上（bottom-up )沉積溝渠或通孔（如第 1 A-1 C圖中，具溝填層〖1 2的孔洞1 20)的能力。為了降低 電鍍電流密度使其落在適合由下往上填洞的範圍’需增加 電鍍浴的離子濃度。例如，使用硫酸濃度為1 6〇g/i之電链 浴與5mA/cm2之電鍵電流已顯示可沉積ΙΟΟΟΑ的連續銅層 於基材上100A的釕層》參照第3圖，5 mA/cm2等同於此 特定酸性濃度下的CCD。然SEM的剖面圖顯示，銅/針介 面有孔隙形成。當電鍍電流升至1〇 mA/cm2(5mA/Cm2之 23 1376433There are still some disadvantages in that the punch-free and continuous film layer to the inner layer is only forcibly by increasing the plating current density; in general, the current density of the xenon clock tends to be poor. Electroplating current densities of less than about 10 mA/cm2 have been found to promote bottom-up deposition of trenches or vias (as in Figure 1 A-1 C, trenches with a trench fill of 1 2) Ability. In order to reduce the plating current density so that it falls within the range suitable for filling the hole from the bottom up, it is necessary to increase the ion concentration of the plating bath. For example, using an electric chain bath with a sulfuric acid concentration of 16 〇g/i and a bond current of 5 mA/cm 2 has been shown to deposit a continuous copper layer of ruthenium on the substrate at 100 A. See Figure 3, 5 mA/cm 2 Equivalent to the CCD at this particular acid concentration. However, the cross-sectional view of the SEM shows that the copper/needle interface has pore formation. When the plating current rises to 1〇 mA/cm2 (5mA/Cm2 of 23 1376433

CCD的兩倍）且使用相同的電鍍浴時，5000A的連 成於100 A的釕層上，並且沒有孔隙形成在銅/釕 CCD取決於電鍍浴酸性的因素之一乃與上 化學過電位有關。此外，酸性較強的電鍍液可移 多餘的沉積物，並增加電鍍表面的活性。然而， 酸濃度來降低CCD仍會引起其他問題。由於直接 圖於阻障層上形成均勻且保型的金屬層，因此宜 低電鍍浴的導電度。導電性較佳的電鍍浴（如含高 電鍍浴）會惡化生成膜層的均勻度。 北德州大學的Chyan等人於西元2003年3 , 27曰、路易斯安那州紐奥良市舉辦之美國化學學 議中所發表的近期研究顯示，氧化釕（Ru02)具有 電性，而銅亦會電鍍且牢牢黏著於氧化釕上。由 觀測到的高 CCD可能是釕表面上多餘的沉積物 結果。在此之”多餘的沉積物’’是包括沉積表面不 氧化反應和聚集於剛沉積完之金屬表面的污染物 表面認為對銅成核更具活性。並且，不含多餘 Ru-Ta合金表面認為對銅成核更具活性。故在 前，先以前處理製程來移除多餘的沉積物，可大 成連續銅層所需的電鍍電流與電鍍浴酸性，且可： 釕介面形成孔隙。本發明之實施例包含前處理製 括陰極前處理阻障層或阻障/黏著層（例如阻障層 /黏著層106A)、或第1A-1E圖所示之VIII族金屬 上述陰極前處理製程為在不含銅離子的酸液 續銅層形 介面。 述區域電 除表面上 藉由增加 電鍍是意 盡可能降 酸濃度的 弓23日至 會國際會 類金屬導 釕表面所 所造成的 欲產生的 。”純”釕 沉積物的 電鍍銅之 幅降低形 避免在銅/ 程，其包 1 0 6、阻障 内層1 0 8。 中電化學 (S ) 24 1376433 處理基材表面。形成於基材上之剛沉積釘阻障/黏著層的金 屬氧化表面，尤其是Ru_Ta_〇x表面，可以陰極還原處理·。 另外，弱鍵結表面的有機污染物可以陰極極化而自表面移 除。在電化學電鍍前先移除基材表面上多餘的沉積物已 證實可降低阻障/黏著層的CCm可能的還原反應如方程式 (1)所示： >Double CCD) and using the same plating bath, 5000A is connected to the 100 A layer, and no pores are formed in the copper/钌 CCD. One of the factors depending on the acidity of the plating bath is related to the upper chemical overpotential. . In addition, the more acidic plating solution removes excess deposits and increases the activity of the plated surface. However, the acid concentration to lower the CCD still causes other problems. Since a uniform and conformal metal layer is formed directly on the barrier layer, the conductivity of the plating bath should be low. A plating bath having a good conductivity (e.g., containing a high plating bath) deteriorates the uniformity of the resulting film layer. A recent study published by Chyan et al. at the University of North Texas in the American Chemical Conference held in New York, New Orleans, Louisiana, in 2003, shows that ruthenium oxide (Ru02) is electrically and copper is also electroplated. And firmly adhere to the yttrium oxide. The observed high CCD may be the result of excess deposits on the surface of the crucible. Here, the "excess deposit" is a surface containing contaminants that do not oxidize on the deposition surface and accumulate on the surface of the newly deposited metal. It is considered to be more active for copper nucleation. Moreover, it does not contain excess Ru-Ta alloy surface. It is more active for copper nucleation. Therefore, the previous treatment process to remove excess deposits can greatly increase the plating current required for the continuous copper layer and the acidity of the plating bath, and can: form the pores of the tantalum interface. Embodiments include a pretreatment process comprising a cathodic pretreatment barrier layer or a barrier/adhesive layer (eg, barrier layer/adhesive layer 106A), or a Group VIII metal as shown in FIG. 1A-1E. The cathode pretreatment process is The copper-containing acid solution continues to form a copper layer interface. The surface of the electrode is removed by the addition of electroplating, which is intended to reduce the acid concentration as much as possible. The thickness of the electroplated copper of the "pure" tantalum deposit is reduced in the copper/process, and it covers 100, the inner layer of the barrier is 10.8. The electrochemical (S) 24 1376433 treats the surface of the substrate. It is formed on the substrate. Just deposited nail barrier / sticky The metal oxide surface of the layer, especially the Ru_Ta_〇x surface, can be cathodically reduced. In addition, the organic contaminants on the weak bonding surface can be cathodically polarized and removed from the surface. The substrate is removed prior to electrochemical plating. Excess deposits on the surface have been shown to reduce the possible reduction of CCm in the barrier/adhesive layer as shown in equation (1): >

Ru02 + 4H* + 4e' Ru + 2H2〇 ⑴ .可進行陰極處理的電化學電鍍室類似配合第5圖說明 於下的銅電鍍室、或與銅電鍍系統分開的處理室。陰極處 理室需要陽極、陰極和不含銅離子的酸浴。最佳的製程參 數可依待處理之合金組成而做調整。冑的濃度範圍介於約 10g/l至ioog/ι之間，較佳為介於約1〇g/l至5〇g"之間。 金马例酸濃度較佳為約 10g/卜或ρΗ = 〇·7。較佳的酸為硫酸，作 π瓜吸但具他類型的酸液亦 可使用，例如有機磺酸溶液（如 、如T暴碩酸）。處理時間為約 2秒至約30分鐘，但在大量虚揮其 里處理基材時為維持適當的產 能’處理時間較佳為小於5分錆。 刀埯。電々丨L密度一般介於約〇 〇5 mA/cm2 至約 5 mA/cm2 之 Μ。、.上…Λ 之間。以處理90%-10%之Ru_Ta合 金為例，電流密度較佳為介於 2 〜丨於約1 itiA/cm2至約5 mA/cm2, 更佳為以約3 mA/cm2處理約„ · 力60秒。另外，酸浴需不含銅 離子’以免銅在陰極處理時沉摇s主二 u積至表面。此沉積行為將形 成較差成核的島狀銅，造成逢 ^成點著性不佳或形成孔隙。 陰極處理可透過電位抟钿^ 饥控制或電流控制來達成。 電 位控制法時’除工作電極（龙 成抹用電 ’、為於晶圓表面的初鐘对薄膜） 25 1376433 與陽極外，還需有參考電極來監測晶圓電位。電位控制可 透過恆電位儀（P〇tentiostat)實行。受控之釕電極相對於參 考電極的電位為介於約〇伏特至約〇伏特，較佳為約_〇 8 伏特（相對於氣化銀（Agcl))。除了 Ru0x還原成釕外，釕層 表面還可能釋出H2’故避免施加過高的還原電位至基材上 是很重要的。#用電流控制法時，陰極電流會流通於覆蓋 如釕層之基材與陽極間。電流密度應介於約〇 〇5 mA/cm2 至約1 mA/cm2之間。處理時間為約2秒至約3〇分鐘。但 在大量處理基材時，為維持適當的產#，處理時間較佳為 小於5分鐘。 值得注意的是，不同於直接電鍍至高阻抗之膜層（如第 1E圖的阻障/黏著層106A)，上述陰極還原步驟並不受限於 末端（terminal)作用。當直接電鍍至高阻抗之膜層時，整個 基材的過電位需报平均，以於基材中央達到適當電流◎此 乃因激烈的末端作用與基材表面有關，而基材表面的阻抗 比傳統銅種晶層還高。其影響直接電鍍膜層的均勻度、和 均勻電鍍連續膜層至基材中央的能力。為能直接電鍍至此 類膜層，已發展出數種特殊的特徵手段來加強標準電鍍 室，包括：惰性多區陽極、準直儀、輔助分流電極（auxiUary thief electrode)、及連續接觸環。然而，已顯示對於適當 地陰極處理整個基材表面而言，此類設備的改良並非為必 須。也不需施加顯著的過電位。反而，均勻處理基材表面 只需以極低電流密度通過的電流，如i mA/cm2 »其理由在 於’陰極還原乃基於電流流動而無任何成核過程，因此不 26 需最小 最小成 面有效 表面施加 之基材表 過電位；反之，於電鍍時，應於整個基材 核過電位，以形成連續的銅層；而具阻抗 降低朝向基材中央的電鑛偏壓。 Θ極前處理基材 點為（特幻 丄〜r且呼增〜丨〜干'部考僧的另一優 著声^是該層為νιπ族金屬内層_，增進鋪層與黏 二θ的的黏著性。實驗結果已顯示，因無孔 面之故，銅層與，前處理、乾淨或可能不具2 入’面間有較佳的黏著性。銅層與釕層間的良好介面 整合：助於形成可靠的半導體元件具有經前處理：対 疋達成於釕層上之尚品質沉積銅層的關鍵因素。另 外，，在電鍍鋼前先陰極前處理舒表面可增進基材表面的親 ,^由於經處理之表面較為親水而可使電鍍液更深入特 徵、口構因此可藉以改善於基材之特徵結構（如孔洞120) 上的電鑛銅之階梯覆蓋性。 上述相關Ru的實驗結果與討論僅為舉例說明。本發 概亦可應用到其他νιπ族金屬，例如铑（Rh)、鉞（〇〇 與銥及阻障材料，例如：#、鈦、氣化鈦、氣化破 氮化鈕、氮化矽钽、鎢、氮化鎢鈦鎢（丁卜贾）合 及対α金。再，者’陰極還原製程不侷限使用上述製 程參數。>(列如’陰極還原製程還可在不是酸性、而是中性 或驗性的溶液（如ρΗ^7·0)中進行。 電漿處理 本發明之實施例包含在電化學電鍍鋼層至基材表面前 27 1376433Ru02 + 4H* + 4e' Ru + 2H2〇 (1) The electrochemical plating chamber that can be subjected to cathodic treatment is similarly described with reference to Fig. 5 to illustrate the copper plating chamber or the processing chamber separate from the copper plating system. The cathode processing chamber requires an anode, a cathode, and an acid bath that does not contain copper ions. The optimum process parameters can be adjusted depending on the composition of the alloy to be treated. The concentration of cerium ranges from about 10 g/l to about ioog/ι, preferably from about 1 〇g/l to 5 〇g". The concentration of acid in the golden horse is preferably about 10 g/b or ρΗ = 〇·7. The preferred acid is sulfuric acid, which can also be used as a π melon but with other types of acid, such as an organic sulfonic acid solution (e.g., T-taste). The treatment time is from about 2 seconds to about 30 minutes, but the processing time is preferably less than 5 minutes to maintain proper productivity in handling the substrate in a large amount of voids. Knife. The electric 々丨L density is generally between about 〇 5 mA/cm 2 and about 5 mA/cm 2 . Between. For example, in the case of processing 90%-10% of Ru_Ta alloy, the current density is preferably from 2 to 丨about 1 itiA/cm 2 to about 5 mA/cm 2 , more preferably about 3 mA/cm 2 . 60 seconds. In addition, the acid bath needs to contain no copper ions' to prevent the copper from sinking to the surface during the cathode treatment. This deposition behavior will form a poorly nucleated island-like copper, causing no punctuality. Good or pore formation. Cathodic treatment can be achieved by potential gamma control or current control. In the potential control method, except for the working electrode (the dragon is wiped out, the film is the first clock on the surface of the wafer) 25 1376433 In addition to the anode, a reference electrode is needed to monitor the wafer potential. The potential control can be performed by a potentiostat (P〇tentiostat). The potential of the controlled crucible electrode relative to the reference electrode is between about 〇VV and about 〇VV. Preferably, it is about _〇8 volts (relative to the vaporized silver (Agcl)). In addition to the reduction of Ru0x into ruthenium, the surface of the ruthenium layer may also release H2', so avoiding the application of excessive reduction potential to the substrate is very Important. When using the current control method, the cathode current will flow through the cover layer. Between the substrate and the anode, the current density should be between about 5 mA/cm2 and about 1 mA/cm2. The processing time is from about 2 seconds to about 3 〇 minutes, but in order to maintain proper handling of the substrate in large quantities. The processing time is preferably less than 5 minutes. It is worth noting that, unlike the direct plating to a high-resistance film layer (such as the barrier/adhesive layer 106A of FIG. 1E), the above-described cathode reduction step is not limited. The role of the terminal. When directly plating to a high-impedance film layer, the overpotential of the entire substrate should be averaged to achieve an appropriate current in the center of the substrate. This is due to the intense end effect associated with the surface of the substrate. The surface resistance of the material is higher than that of the conventional copper seed layer, which affects the uniformity of the direct plating layer and the ability to uniformly plate the continuous film layer to the center of the substrate. Several kinds of layers have been developed for direct plating to such layers. Special features to enhance the standard plating chamber, including: inert multi-zone anodes, collimators, auxiliary auxiliary electrodes (auxiUary thief electrodes), and continuous contact rings. However, it has been shown that the entire substrate table is properly cathodically processed. In this case, improvements in such equipment are not necessary. There is no need to apply significant overpotentials. Instead, the substrate surface is treated with a very low current density, such as i mA/cm2. The reduction is based on the current flow without any nucleation process, so the surface of the substrate surface with the minimum and minimum surface effective surface application is required. On the contrary, during the plating, the potential of the entire substrate core should be over-exposed to form continuous copper. Layer; while the impedance is reduced toward the center of the substrate of the electric mine bias. The front of the bungee processing substrate point is (special illusion ~ r and hurry ~ 丨 ~ dry 'partition test another excellent sound ^ is the The layer is a νιπ group metal inner layer _, which enhances the adhesion of the layer to the viscous two θ. The experimental results have shown that the copper layer has a better adhesion between the copper layer and the pre-treatment, clean or may not have a 2-face because of the non-porous surface. Good interface between the copper layer and the germanium layer. Integration: Helps to form reliable semiconductor components with pre-treatment: 关键 疋 The key factor in the quality of the deposited copper layer on the germanium layer. In addition, before the electroplating steel, the pre-cavity treatment of the surface can improve the surface of the substrate. Since the treated surface is relatively hydrophilic, the electroplating solution can be further characterized and the mouth structure can be improved to improve the characteristic structure of the substrate. (eg, hole 120) The step coverage of the electric ore copper. The experimental results and discussion of the above related Ru are only examples. The present invention can also be applied to other νιπ group metals, such as rhodium (Rh), niobium (tantalum and niobium and barrier materials, such as: #, titanium, titanium carbide, vaporized nitriding button, tantalum nitride) Tungsten, tungsten nitride, titanium tungsten (Butb) and 対α gold. Furthermore, the 'cathodic reduction process is not limited to the above process parameters.> (such as 'the cathode reduction process can be not acidic, but Neutral or inductive solution (eg, ρΗ^7·0). Plasma Treatment Embodiments of the invention are included in the electrochemical plating of steel layers to the surface of the substrate before 27 1376433

先電漿處理基材表面’其中表面是由合金組成’例如阻障/ 黏著層106A。如上述結合第1A及1B圖之說明’合金是 由至少50原子。/。之VI11族金屬與衡量之阻障金屬所組 成。電漿表面處理較佳是在氫氣或氫氣/氦氣中使用射頻 (RF)電漿並施加偏座至基材而進行°此技藝已知基材之電 聚蚀刻處理可有效移除基材表面上的氧化材料。因此’在 電鍍銅前先電漿處理Ru_Ta合金確信可具有與陰極電化學 前處理相同的好處，藉以還原及/或移除合金表面上的原生 氧化物，尤其是阻障金屬氧化物。電漿處理可以感應耦合 電漿或電容耦合電漿為基礎。The surface of the substrate is first plasma treated 'where the surface is composed of an alloy' such as a barrier/adhesion layer 106A. As described above in connection with the description of Figures 1A and 1B, the alloy is composed of at least 50 atoms. /. The VI11 metal is composed of the measured barrier metal. The plasma surface treatment is preferably carried out by using radio frequency (RF) plasma in hydrogen or hydrogen/helium gas and applying a bias to the substrate. It is known that the electropolymerization etching treatment of the substrate can effectively remove the surface of the substrate. Oxidized material on. Therefore, the plasma treatment of Ru_Ta alloy prior to electroplating of copper is believed to have the same benefits as electrochemical pretreatment of the cathode, thereby reducing and/or removing native oxides on the surface of the alloy, particularly barrier metal oxides. Plasma processing can be based on inductively coupled plasma or capacitively coupled plasma.

第3A圖為電漿表面處理室的剖面示意圖，其亦稱為 預洗室，用以施行本發明之實施例。預洗室3 1 0可結合至 電化學處理系統，如配合第 4圖所述之電化學處理系統 (ECPS)400。較佳地，預洗室310置於ECPS 400的工廠介 面（FI)430，即ECPS 400中處理與操作乾燥基材的最佳位 置。如此基材經電漿表面處理後，即可在很短的時間内進 行電鍍（如數分鐘或數秒），而不像由個別的處理平台來進 行電漿表面處理那樣久。於ECPS 400中增設預洗室3 10 還可使基材間有均一的等待時間。故對於在E C P S 4 0 0進 行處理的各基材而言，電鍍前的等待時間不僅可大幅縮 短’電漿表面處理步驟與電鍍步驟間的等待時間亦可控制 成相同，進而減少各基材的製程變數。 預洗室310 —般具有基材支撐構件312，其係設置於 室封閉區314的石英圓頂316下。基材支撐構件312可包 28 6433 括中央座板318，其係設置於石英絕緣板322的 内°在一些實施例中，基材支榜構件312可為加 支律構件，以於電漿處理的過程中加熱基材。典型 央座板318的頂面延伸超過石英絕緣板322的頂面 326底面與石英絕緣板322頂面間的間隙324 一奋 密爾（《1丨1)至15密爾。處理時，基材326放置在中 318上且可藉由定位銷332定位。基材3 26的邊緣 延伸超過石英絕緣板322，並突出石英絕緣板322 ί 石英絕緣板322的斜面部分328位於基材326的突 部分下方’而較低的環形平面330自斜面部分328 外緣處延伸。絕緣板3 2 2和圓頂3 1 6可包含其他介1 例如氧化鋁與氮化矽。 用於預洗室310之基材326的電漿表面處理製 涉及採用基材3 2 6做為濺鍍靶材的濺鍍蝕刻製程。 體（如氫氣或氦氣/氫氣混合氣體）流過預洗室31〇β 應室外的線圈317來施加RF電源至反應室，可點 室内的電漿。直流（DC)偏壓可施加至基材326，以 漿中的離子朝基材326移動。 根據一用於300毫米尺寸之基材的電漿表面處 實例，氫氣的使用流量介於約1 0 0 s c c m至約1 2 0 0 間。9 5 %氦氣/ 5 %氫氣之混合氣體的使用流量可高起 seem »製程進行時，預洗室3 1 〇的壓力維持在約1 (mTorr)至約50毫托耳；RF功率為約1 000瓦（W)至 瓦；基材溫度維持在約2 0 °C至約3 5 0 °C。處理時間 7 處 320 ί之基材 地，中 。基材 ί為約5 央座板 .部分可 Kj上緣。 .出邊緣 較低的 電材料* 程一般 清洗氣 透過反 燃反應 力α速電 理製程 seem 之 t 約 500 毫托耳 約 3 000 視合金 29 1376433 组成而定，熟諳此技藝者可依特定的合金表面輕鬆決定出 處理時間。Figure 3A is a schematic cross-sectional view of a plasma surface treatment chamber, also referred to as a pre-wash chamber, for carrying out embodiments of the present invention. The prewash chamber 310 can be coupled to an electrochemical processing system, such as the electrochemical treatment system (ECPS) 400 described in connection with FIG. Preferably, the prewash chamber 310 is placed in the factory interface (FI) 430 of the ECPS 400, i.e., the ECPS 400 is optimally positioned to handle and dry the substrate. Once the substrate is surface treated with a plasma, it can be plated in a short period of time (e.g., minutes or seconds), rather than as long as the plasma surface treatment by an individual processing platform. The addition of a pre-wash chamber 3 10 to the ECPS 400 also provides a uniform waiting time between the substrates. Therefore, for each substrate processed in ECPS 400, the waiting time before plating can be greatly shortened. 'The waiting time between the plasma surface treatment step and the plating step can be controlled to be the same, thereby reducing the substrate. Process variables. The prewash chamber 310 generally has a substrate support member 312 disposed under the quartz dome 316 of the chamber enclosure 314. The substrate support member 312 can include 28 6433 including a central seating plate 318 disposed within the quartz insulating plate 322. In some embodiments, the substrate support member 312 can be an additional member for plasma processing. The substrate is heated during the process. The top surface of the typical center plate 318 extends beyond the gap 324 between the bottom surface of the top surface 326 of the quartz insulating plate 322 and the top surface of the quartz insulating plate 322 by a mil (1 to 1) to 15 mil. When processed, the substrate 326 is placed on the middle 318 and can be positioned by the locating pin 332. The edge of the substrate 3 26 extends beyond the quartz insulating plate 322 and protrudes from the quartz insulating plate 322. The beveled portion 328 of the quartz insulating plate 322 is located below the protruding portion of the substrate 326 and the lower annular plane 330 is from the outer edge of the beveled portion 328. Extended. The insulating plate 3 2 2 and the dome 3 16 may contain other media such as alumina and tantalum nitride. The plasma surface treatment process for the substrate 326 of the prewash chamber 310 involves a sputtering etch process using a substrate 326 as a sputtering target. The body (such as hydrogen or helium/hydrogen mixed gas) flows through the preheating chamber 31 〇β outside the coil 317 to apply RF power to the reaction chamber, and the plasma in the chamber can be clicked. A direct current (DC) bias can be applied to the substrate 326 to move ions in the slurry toward the substrate 326. According to an example of a plasma surface for a substrate having a size of 300 mm, the flow rate of hydrogen is between about 10 s c c m and about 1 2 0 0. The flow rate of 9 5 % helium / 5 % hydrogen gas mixture can be increased from the seem » process, the pressure of the pre-wash chamber 3 1 维持 is maintained at about 1 (mTorr) to about 50 mTorr; RF power is about 1 000 watts (W) to watt; substrate temperature maintained at about 20 ° C to about 350 ° C. Processing time 7 at 320 ί of substrate, medium. The substrate ί is about 5 central seat plates. The part can be Kj upper edge. The lower edge of the electrical material * the general cleaning gas through the flashback reaction force α speed electric power process seem t about 500 mTorr about 3 000 depending on the composition of the alloy 29 1376433, familiar with this skill can be specific The surface of the alloy easily determines the processing time.

根據另一用於3 00毫米尺寸之基材的電漿表面處理製 程實例，95%氦氣/5%氫氣之混合氣體的使用流量介於約 50 seem至約200 seem之間。製程進行時，RF功率為約 300瓦至約1000瓦；基材溫度維持在約20°C至約3 50°C。 在此實施例中，施加的基材偏壓為約0瓦至約1 0 0瓦。處 理時間視合金組成而定，熟諳此技藝者可依特定的合金表 面輕鬆決定出處理時間。According to another example of a plasma surface treatment process for a substrate having a size of 300 mm, a mixed gas of 95% helium/5% hydrogen is used at a flow rate of between about 50 seem and about 200 seem. The RF power is from about 300 watts to about 1000 watts as the process proceeds; the substrate temperature is maintained from about 20 ° C to about 35 ° C. In this embodiment, the applied substrate bias is from about 0 watts to about 1000 watts. The processing time depends on the composition of the alloy. Those skilled in the art can easily determine the processing time according to the specific alloy surface.

在含氮混合氣體（forming gas)中所進行之熱前處理 (如在4%氫氣/9 6%氮氣之混合氣體中進行2 5 0乞熱退火處 理），已證實不能有效改善電鍍銅層黏著到钽系阻障層的黏 著性。熱退火製程無法成功還原氧化钽的原因在於，退火 溫度通常很低以避免整合發生問題，而氧化鈕在此退火溫 度下為熱穩狀態。但更精進的只用氫氣處理方式或氦氣/ 氫氣處理方式結合RF電漿及/或基材偏壓，可還原合金表 面的氧化組，使得沉積銅詹可黏著到合金表面。 利用錯合之鹼性電解液而直接電鍍至阻障層或阻障/黏著 層上 本發明之實施例教導使用含錯合銅源之鹼性電鍍液而 直接電鍍銅層至阻障層或阻障/黏著層上。在此之”直接電 鍍”是定義為將較具導電性的金屬層（如第2圖的種晶層 111)電化學電鍍至實質上較不具導電性的膜層（如導電基 30 1376433 材表面11 4)，以利後續之溝填層112及/或過填層113的均 勻且無孔隙沉積。可實行此方法的電鍍室類似配合第5圖 說明於下的電化學處理室。Thermal pretreatment in a nitrogen-containing forming gas (such as thermal annealing in a mixed gas of 4% hydrogen / 9 6% nitrogen) has proven to be ineffective in improving the adhesion of the electroplated copper layer. Adhesion to the barrier layer of the lanthanide. The reason why the thermal annealing process cannot successfully reduce yttrium oxide is that the annealing temperature is usually low to avoid integration problems, and the oxidation button is thermally stable at this annealing temperature. However, more refined hydrogen treatment or helium/hydrogen treatment combined with RF plasma and/or substrate bias can reduce the oxidation of the alloy surface so that the deposited copper can adhere to the alloy surface. Direct Electroplating to a Barrier Layer or Barrier/Adhesive Layer Using a Miscible Alkaline Electrolyte Embodiments of the present invention teach direct plating of a copper layer to a barrier layer or barrier using an alkaline plating solution containing a mismatched copper source Barrier/adhesive layer. "Direct plating" is defined herein as the electrochemical plating of a more conductive metal layer (such as seed layer 111 of FIG. 2) to a substantially less conductive film layer (eg, conductive substrate 30 1376433 material surface). 11 4) to facilitate uniform and non-porous deposition of the subsequent trench fill 112 and/or overfill 113. The plating chamber in which this method can be practiced is similar to the electrochemical processing chamber illustrated in Figure 5 below.

含錯合銅源的電鍍液比不含銅離子的電鍍液具有.更高 負值的沉積電位。一般而言，錯合銅離子的沉積電位為約 -1.1伏特（V)至約-0.5V，其視特定錯合劑而定。當參考電 極為銀/氯化銀（Ag/AgCl)(lM的氯化鉀（KC1))且其相對標 準氫電極的電位為0.235 V時，不含銅離子的沉積電位介 於約-0.3 V至約-0.1 V之間。例如：The plating solution containing the wrong copper source has a higher negative deposition potential than the plating solution containing no copper ions. In general, the deposition potential of the mismatched copper ions is from about -1.1 volts (V) to about -0.5 V, depending on the particular intermixing agent. When the reference electrode is silver/silver chloride (Ag/AgCl) (1M potassium chloride (KC1)) and its potential relative to the standard hydrogen electrode is 0.235 V, the deposition potential without copper ions is between about -0.3 V. To about -0.1 V. E.g:

Cu2(C6H4〇7) + 2H2〇 -> 2Cu° + C6H8〇7 + 〇2 Δε = -0.7V ； Cu + 2 + 2e_ Cu° Αε = -0.2V。Cu2(C6H4〇7) + 2H2〇 -> 2Cu° + C6H8〇7 + 〇2 Δε = -0.7V; Cu + 2 + 2e_ Cu° Α ε = -0.2V.

另外，錯合電鍍浴中與電位相依的電流實質上也比不 含銅離子的電鍍浴小。因此可改善整個基材表面的局部電 流密度差異，即使低導電度之阻障金屬薄層造成整個基材 表面有大的電位梯度，同樣有改善效果。如此可使整個基 材表面有較佳的沉積均勻度。更詳細的銅錯合浴之電化學 極化說明可參見美國專利申請號1 0/616,097、申請曰為西 元2003年7月8曰的申請案，其一併附上供作參考。 適合用於在此所述之電鍍銅製程的電鍍液可包括至少 一銅源化合物、至少一餐合或錯合之化合物、或選擇性加 入潤濕劑或抑制劑、或選擇性加入pH調整劑與溶劑。 電鑛液包含至少一與至少一配位體（ligand)錯合或螯 合的銅源化合物。錯合銅源包括位於核心的銅原子，周圍 環繞著配位體、官能基、強烈親銅的分子或離子（相較於較 31 1376433 不親合配位體（例如水）的自由銅離子）。錯合銅源可在加到 電鍍液前先行螯合、或原位（in situ)結合自由銅離子源與 錯合劑而形成之。銅原子在與配位體錯合的過程或前後皆 可為任一氧化態，如0、1或2。故整篇說明書使用的銅（Cu) 包括金屬銅（Cu)、一價銅（Cu+1)、或二價銅（Cu + 2)，除非其 有特別指明。In addition, the potential-dependent current in the electroplating bath is substantially smaller than that of the electroplating bath containing no copper ions. Therefore, the difference in local current density across the surface of the substrate can be improved, and even a low-conductivity barrier metal layer causes a large potential gradient across the substrate surface, which also has an improvement effect. This allows for better deposition uniformity across the substrate surface. A more detailed description of the electrochemical polarization of a copper mismatch bath can be found in U.S. Patent Application Serial No. 10/616,097, the entire disclosure of which is incorporated herein by reference. A plating bath suitable for use in the electroplating copper process described herein may comprise at least one copper source compound, at least one compound or compound, or a wetting agent or inhibitor, or a pH adjusting agent. With solvent. The electromineral liquid comprises at least one copper source compound that is mismatched or chelated with at least one ligand. A mismatched copper source consists of a copper atom at the core surrounded by a ligand, a functional group, a strongly pro-copper molecule or ion (as compared to the free copper ion of 31 1376433 non-affinity ligand (eg water)) . The mismatched copper source can be formed by chelation or in situ bonding of a source of free copper ions and a miscible agent prior to addition to the plating solution. The copper atom may be in any oxidation state, such as 0, 1, or 2, before or after the process of mismatching with the ligand. Therefore, copper (Cu) used throughout the specification includes metallic copper (Cu), monovalent copper (Cu+1), or divalent copper (Cu + 2) unless otherwise specified.

適合做為銅源化合物的例子包括檸檬酸銅、乙二胺 (ED)铜、乙二胺四乙酸（EDTA)銅等。一特定銅源化合物可 具各種配位體。例如，擰檬酸銅包括至少--價銅原子、Examples of suitable copper source compounds include copper citrate, ethylenediamine (ED) copper, ethylenediaminetetraacetic acid (EDTA) copper, and the like. A particular copper source compound can have a variety of ligands. For example, copper citrate includes at least a valence copper atom,

二價銅原子或其組合物、及至少一檸檬酸配位體，並包括 Cu(C6H7〇7)、Cll2(C6H4〇7)、CU3(C6H5〇7)、或 Cll(C6H7〇7)2。 在另一例子中，EDTA銅可包括至少一 一價銅原子、二價 銅原子或其組合物、及至少一 EDTA配位體，並包括 CU(C1 οΗ 15〇8N2 ) ' C U2 (C1 οΗ 14〇8 Ν2 ) ' CU3(Cι 〇 Η ι 3〇8 Ν 2 ) ' Cll4(Ci〇Hi2〇8N2) ' Cu(Ci〇Hi4〇8N2)、或 Cll2(Ci〇Hi2〇8N2)。 適合做為銅源化合物的例子包括硫酸銅、焦碌酸銅、和氟 硼酸銅。 電鑛液含有一或多種螯合或錯合化合物，其包括具一 或多個官能基的化合物，且官能基選自由羧酸基、羥基、 烧氧基、含氡酸（oxo acid)基、經基與缓酸基之混合物、 及其組合物。適合做為螯合化合物的其他例子包括具一或 多個胺與醯胺官能基的化合物，例如乙二胺（ED)、二乙烯 三胺、二乙烯三胺衍生物、己二胺、胺基酸、乙二胺四乙 酸（EDTA)、甲基曱醯胺、或其組合物。電鍍液可包括一或 < S ) 32 1376433 多種濃度約為0.02M至1.6M的螯合劑。A divalent copper atom or a combination thereof, and at least one citric acid ligand, and includes Cu (C6H7〇7), Cll2 (C6H4〇7), CU3 (C6H5〇7), or C11(C6H7〇7)2. In another example, the EDTA copper can include at least a monovalent copper atom, a divalent copper atom, or a combination thereof, and at least one EDTA ligand, and includes CU(C1 οΗ 15〇8N2 ) ' C U2 (C1 οΗ 14〇8 Ν2 ) ' CU3(Cι 〇Η ι 3〇8 Ν 2 ) ' Cll4(Ci〇Hi2〇8N2) 'Cu(Ci〇Hi4〇8N2), or Cll2(Ci〇Hi2〇8N2). Examples of suitable copper source compounds include copper sulfate, copper pyrophosphate, and copper fluoroborate. The electromineral liquid contains one or more chelating or staggering compounds including a compound having one or more functional groups selected from a carboxylic acid group, a hydroxyl group, an alkoxy group, an oxo acid group, a mixture of a base group and a slow acid group, and a composition thereof. Other examples suitable as chelating compounds include compounds having one or more amine and guanamine functional groups, such as ethylenediamine (ED), diethylenetriamine, diethylenetriamine derivatives, hexamethylenediamine, amine groups. Acid, ethylenediaminetetraacetic acid (EDTA), methylguanamine, or a combination thereof. The plating bath may comprise a chelating agent of a concentration of from about 0.02 M to about 1.6 M.

一或多種螯合化合物還可包括螯合化合物的鹽類，例 如鋰、鈉'鉀、鉋、鈣、鎂、銨、及其組合物。螯合化合 物的鹽類可完全或部分含有上述陽離子（例如鈉（N a))和酸 性質子’例如 Nax(C6H8-x〇7)或 NaxEDTA，X = 1-4。此種 鹽類結合銅源而生成NaCu(C0H5〇7)。合適的無機或有機酸 鹽的例子包括有機酸敍或有機酸卸鹽，例如草酸敍、檸檬 酸敍、玻站酸銨 '檸檬酸鉀（單鹽基；m0nobasic )、檸檬 酸卸（雙鹽基；dibasic)、檸檬酸鉀（三鹽基；tribasic)、 酒石酸鉀、酒石酸敍、破绍酸鉀、草酸卸、及其組合物。 一或多種螯合化合物還可包括錯合鹽類，例如水合物（如檸 檬酸納二水合物）。 润濕劑或抑制劑的添加量為約10 ppm至約2〇〇〇 ppm ’較佳為約5 0 ppm至約1 〇〇〇 ppm。抑制劑包括聚丙烯 胺、聚丙稀酸聚合物、聚羧酸酯共聚物、環氧乙院及/或環 氧丙烧（EO/PO)的聚驗或聚輯、椰子油酸二乙醇醯胺The one or more chelating compounds may also include salts of chelating compounds such as lithium, sodium 'potassium, planer, calcium, magnesium, ammonium, and combinations thereof. The salt of the chelating compound may wholly or partially contain the above cation (e.g., sodium (N a)) and an acid species such as Nax(C6H8-x〇7) or NaxEDTA, X = 1-4. This salt combines with a copper source to form NaCu (C0H5〇7). Examples of suitable inorganic or organic acid salts include organic acid or organic acid salt-removing salts, such as oxalic acid, citric acid, ammonium silicate potassium citrate (single salt base; m0nobasic), citric acid unloading (double salt base) Dibasic), potassium citrate (tribasic), potassium tartrate, tartaric acid, potassium sulphate, oxalic acid unloading, and combinations thereof. The one or more chelating compounds may also include a miscible salt such as a hydrate (e.g., sodium dihydrate citrate). The wetting agent or inhibitor is added in an amount of from about 10 ppm to about 2 Torr ppm, preferably from about 50 ppm to about 1 〇〇〇 ppm. Inhibitors include polyacrylamide, polyacrylic acid polymers, polycarboxylate copolymers, polyacrylamide and/or oxypropylene (EO/PO) polymerization or collection, and coconut oleic acid diethanolamine

(coconut diethanolamide )、油酸二乙醇醯胺（oleic diethanolamide)、乙醇醯胺衍生物、或其組合物。 一或多種pH調整劑為選擇性加入電鍵液，使其 ρΗ27·0，較佳為介於約7 〇至約9 5之間。pH調整劑的用 量視不同配方的組成濃度而定。不同的化合物在特定濃度 下有不同的pH值，例如組成包括約0_1ν〇ι %至約ι〇ν〇1 % 的鹼（如氫氧化鉀、氫氧化銨、或其組合物）可提供預定的 pH值。一或多種pH調整劑還可包括酸，例如羧酸（如乙(coconut diethanolamide), oleic diethanolamide, ethanolamine derivative, or a combination thereof. The one or more pH adjusting agents are selectively added to the key solution such that it is ρ Η 27·0, preferably between about 7 〇 and about 9.5. The amount of pH adjuster depends on the compositional concentration of the different formulations. Different compounds have different pH values at specific concentrations, for example, a composition comprising from about 0 to about 10% to about 1% by weight of alkali (such as potassium hydroxide, ammonium hydroxide, or a combination thereof) can provide a predetermined pH value. The one or more pH adjusting agents may also include an acid such as a carboxylic acid (eg, B

< S 33 1376433 酸、檸檬酸、草酸）、含磷酸鹽之化合物（包括磷酸、磷酸 錄、鱗酸钾）、無機酸（如硫酸、硝酸、鹽酸）、及其组合物。 根據採用Cu-EDTA鹼性電解液之直接電鍍製程的實 鉍例，施加至基材的恆定陰極電流會形成恆定的電流密 度，其可在約〇· 1秒至5.0秒内形成约i mA/cm2至約10 mA/cm2的電流密度。如此可形成厚度為約5〇a至約3〇〇入 的銅種晶層於阻障層上。 利用酸性電解液而直接電鍍至阻障/黏著層上 或者’為媒保上述直接電鍍製程可形成均勻且無孔隙 之種晶層於基材上，當基材表面最先接觸電解液時，可使 用”成核尖峰（nucleation spike)”或，，成核脈衝”。在此之，，成 核尖峰或”成核脈衝”是定義為較大的初始電鍍電流，其協 助沉積鋼成核於基材表面，其中初始電鍍電流至少是等於 或較佳是大於CCD。此電鍍電流可超過允許由下往上填充 基材之特徵結構的最大電鍍電流，因而僅施加很短的時 間，以免基材之高深寬比特徵結構的填充不完全而產生孔 隙。成核脈衝初始係施加到基材表面，以確保在上述直接 電鍍製程中，形成均勻、具良好黏著性且無孔隙之膜層（如 第2圖的種晶層丨丨丨）於高阻抗之阻障/黏著層上。例如，以 電鍍銅種晶層至釕阻障層為例，在提供約〇1秒至約1〇秒 的成核脈衝時’介於约5 mA/cm2至约2〇 ^α/^2的恆定電 鍍電流為施加至阻障層。如此可形成保型均勻且無孔隙 之膜層（如第2圖的種晶層111)於基材上。可實行此方法的 34 1376433 電鍍室類似配合第5圖說明於下的電化學處理室。此電鍍 製程不需使用錯合劑。 利用錯合之鹼性電解液而電鍍至銅種晶層上<S 33 1376433 acid, citric acid, oxalic acid), phosphate-containing compound (including phosphoric acid, phosphoric acid, potassium sulphate), inorganic acid (such as sulfuric acid, nitric acid, hydrochloric acid), and combinations thereof. According to a practical example of a direct electroplating process using a Cu-EDTA alkaline electrolyte, a constant cathode current applied to the substrate forms a constant current density which can form about i mA in about 〇 1 sec to 5.0 sec. Current density from cm2 to about 10 mA/cm2. Thus, a copper seed layer having a thickness of about 5 Å to about 3 Å can be formed on the barrier layer. Directly electroplating onto the barrier/adhesive layer using an acidic electrolyte or 'solving the above direct plating process to form a uniform and non-porous seed layer on the substrate. When the surface of the substrate first contacts the electrolyte, Use a "nucleation spike" or, a nucleation pulse." Here, a nucleation spike or "nucleation pulse" is defined as a larger initial plating current that assists in depositing steel nucleation on the base. The surface of the material, wherein the initial plating current is at least equal to or preferably greater than the CCD. This plating current can exceed the maximum plating current that allows the features of the substrate to be filled from bottom to top, and thus is applied only for a short period of time to avoid substrate The high aspect ratio feature structure is incompletely filled with voids. The nucleation pulse is applied to the surface of the substrate to ensure uniform, good adhesion and void-free film layer in the above direct plating process (eg, 2nd) The seed layer of the figure is on the high-impedance barrier/adhesion layer. For example, in the case of electroplating a copper seed layer to a germanium barrier layer, nucleation is provided in about 1 second to about 1 second. Pulse time A constant plating current of between about 5 mA/cm2 and about 2 〇^α/^2 is applied to the barrier layer. Thus, a uniform and non-porous film layer can be formed (such as the seed layer 111 of FIG. 2). On the substrate, the 34 1376433 electroplating chamber that can be used in this method is similar to the electrochemical treatment chamber described in Figure 5. This electroplating process does not require the use of a miscible agent. Electroplating to copper species using a miscible alkaline electrolyte On the crystal layer

本發明之實施例教導使用錯合之鹼性電解液來電鍍溝 填層（如第2圖的溝填層11 2)至種晶層上（如種晶層111 )， 其中種晶層已藉由鹼液ECP製程直接沉積至阻障層上。可 實行此方法的電化學電鍍室類似配合第5圖說明於下的電 化學處理室。 本方法類似上述利用錯合之鹼性電解液來直接電鍍至 阻障層上的方法。製程參數包括電鍍電‘流與沉積時間，可 加以調整來增強由下往上的填洞能力。此方法通常採用較 快的沉積速率與電鍍電流密度。Embodiments of the present invention teach the use of a miscible alkaline electrolyte to electroplate a trench fill (such as trench fill layer 11 2 of Figure 2) onto a seed layer (e.g., seed layer 111), wherein the seed layer has been borrowed Direct deposition onto the barrier layer by the lye ECP process. The electrochemical plating chamber in which this method can be practiced is similarly illustrated in the electrochemical processing chamber illustrated in Figure 5. The method is similar to the above method of directly plating onto a barrier layer using a miscible alkaline electrolyte. Process parameters include electroplating's flow and deposition time, which can be adjusted to enhance the ability to fill holes from bottom to top. This method typically uses a faster deposition rate and plating current density.

此製程所用的電鍍浴亦類似直接電鍍製程所用的電鍍 浴。如前所詳述，用來填洞的錯合鹼浴含有至少一鋼源化 合物和至少一錯合化合物。一或多種錯合化合物還可包括 上列螯合化合物的鹽類。電鑛浴尚含有潤濕劑和一或多種 Ρ Η調整劑（參見上述說明）。電鍍浴的組成濃度可加以調整 來增強由下往上的填洞能力。 另外，形成均勻且無孔隙之金屬層至種晶層上不需使 用成核脈衝。 利用酸性電解液來電鍍至銅種晶層上 本發明之實施例教導使用傳統酸性電解質來電鍍溝填 35 1376433 層至已藉由鹼液ECP製程直接沉積至阻障層上的種晶層。 使用酸性電鍍液來ECP溝填沉積銅層至鋼種晶層上為此技 藝所熟知’且可實行此方法的電化學電鍍室類似配合第4 及5圖說明於下的銅電鐘室。此方法還可用來沉積銅過填 層（如第2圖的過填層113)至基材上。The electroplating bath used in this process is also similar to the electroplating bath used in the direct electroplating process. As described in detail above, the miscible alkali bath used to fill the hole contains at least one steel source compound and at least one compound. The one or more miscible compounds may also include salts of the above listed chelate compounds. The electromine bath also contains a wetting agent and one or more Ρ Η adjusters (see above). The composition concentration of the plating bath can be adjusted to enhance the ability to fill holes from bottom to top. In addition, the formation of a uniform and void-free metal layer onto the seed layer does not require the use of nucleation pulses. Electroplating onto a Copper Seed Layer Using an Acidic Electrolyte Embodiments of the present invention teach the use of a conventional acid electrolyte to electroplate a 35 1376433 layer to a seed layer that has been deposited directly onto the barrier layer by a lye ECP process. The use of an acidic plating bath to deposit a copper layer onto a steel seed layer on an ECP trench is well known in the art and the electrochemical plating chamber in which this method can be practiced is similar to the copper bell chamber illustrated in Figures 4 and 5. This method can also be used to deposit a copper overfill (e.g., overfill 113 of Figure 2) onto a substrate.

用於ECP的傳統電化學電鍍液（即非錯合電鐘液）一般 包括銅源、酸源、氯離子源、和至少一電鍍液添加劑即 平整劑、抑制劑、促進劑、抗泡劑等。例如，電鑛液可包 含約30 g/Ι至60 g/丨的銅、約10 g/丨至5〇 g/i的硫酸約 20 ppm至100 ppm的氣離子、約5 ppm至3〇 ppm的添加 促進劑、約100 ppm至1 000 ppm的添加抑制劑、約1 ml/1 至6 ml/1的添加平整劑。電鍍電流可介於約2 mA/cm2至 約10 mA/cm2之間，以填充約300A至約3〇〇〇a的銅層至 次微米大小的溝渠及/或通孔結構中。實質類似的製程可用 於過填電鐘法，其中另一厚度為約5000A至約1〇〇〇〇人的 銅層電鐘至基材上’以完成銅内連線結構β銅電锻之化學 劑與製程的例子可參見共同受讓之美國專利申請號 1 0/616,097、名稱「直接電鍍銅於阻障金屬上的多步驟電 沉積製程（Multiple-Step Electrodeposition Process for Direct Copper Plating on Barrier Metals) j ' 申請日為西元 2003年 7月 8曰的申請案、以及美國專利申請號 60/5 1 0,1 90、名稱「初始保型電化學沉積銅於次微米特徵 結構中的方法與化學劑（Methods and Chemistry for Providing Initial Conformal Electrochemical Deposition 36 1376433 of Copper in Sub-micron Features)」、申請日 a 工-内一， J J 句西兀2003 年10月10曰的申請案。 電鍍設備之範例 電化學處理系統 第4圖為電化學處理系統（ECPS)400之一訾从，，L , 视例的上 視圖，其可施行本發明之方法。ECPS 400 —船白上 73又a括製程平The conventional electrochemical plating solution for ECP (ie, non-missing electric clock liquid) generally includes a copper source, an acid source, a chloride ion source, and at least one plating solution additive, that is, a leveling agent, an inhibitor, an accelerator, an antifoaming agent, etc. . For example, the electromineral liquid may comprise from about 30 g/Ι to 60 g/丨 of copper, from about 10 g/丨 to 5〇g/i of sulfuric acid from about 20 ppm to 100 ppm of gas ions, from about 5 ppm to about 3 ppm. Adding accelerator, about 100 ppm to 1 000 ppm of added inhibitor, about 1 ml / 1 to 6 ml / 1 of added leveling agent. The plating current can be between about 2 mA/cm2 and about 10 mA/cm2 to fill a copper layer of about 300A to about 3〇〇〇a into a submicron sized trench and/or via structure. A substantially similar process can be used for the overfilling clock method, in which another thickness is about 5,000 A to about 1 铜 of the copper layer clock to the substrate 'to complete the copper interconnect structure β copper electric forging chemistry Examples of agents and processes can be found in the commonly assigned U.S. Patent Application Serial No. 10/616,097, entitled "Multiple-Step Electrodeposition Process for Direct Copper Plating on Barrier Metals". j ' The application date is July 8th, 2003, and the US patent application number 60/5 1 0, 1 90, the name "initial conformation of electrochemical deposition of copper in submicron features and chemical agents (Methods and Chemistry for Providing Initial Conformal Electrochemical Deposition 36 1376433 of Copper in Sub-micron Features)", application day a - internal one, JJ sentence Xixi 10 October 2003 application. Example of Electroplating Apparatus Electrochemical Processing System Fig. 4 is a top view of an electrochemical processing system (ECPS) 400, which can be carried out by a method of the present invention. ECPS 400 — ship white 73

台413’其具有位於中央的機械裝置420。機械裝置42〇 一般包括一或多個機械臂422、424，用以支授 a·听丞材於兵Stage 413' has a centrally located mechanism 420. The mechanical device 42〇 generally includes one or more mechanical arms 422, 424 for teaching a· listening to the coffin

上。此外’機械裝置42〇和機械臂422、424 —般可延伸、 轉動與垂直移動，故機械裝置420可***與移出基材，使 基材進出製程平台413上的多個製程位置402、404、406、 40 8、410、412、414、416。製程位置可為無電電鍍室電 化學處理室、基材洗滌室及/或乾燥室、基材斜面清洗室、 基材表面清洗至或預洗室、及/或其他有利於電锻製程的處 理室。較佳地，本發明之實施例是施行在製程位置4〇2、 404、406、408、41 0、4 12 至少其中之―内。 ECPS 400更包括工薇介面（Fl)430。pi 430 —般包括 至少一？1機械裝置43 2’且其位於鄰接製程平台413之1?1 430的一側。FI機械裝置432可設置用來接取基材卡匣434 中的基材426。FI機械裝置432傳送基材426至其中之一 製程位置414或41 6 ’以開始進行處理程序。同樣地，完 成基材處理程序後’ FI機械裝置432可用來取回製程位置 414或416中的基材。此時’FI機械裝置432可將基材426 37 1376433 傳回卡E434而移出系統400夕卜。再者，機械裝置432還 可延伸至連接工廢介面430與製程平台413的連結通道 415。另外，以機械裝置432可進入連接？143〇的退火室 43^根據本發明包括電襞處理之實施例，退火室‘η較佳 是當作配合第3A圖說明於上的電聚處理室31〇。這是因為 ? 430最好是用來操作與處理乾燥基材，@平台⑴最好 是用來操作與處理濕潤基材。on. In addition, the mechanical device 42 and the mechanical arms 422 and 424 can be extended, rotated and vertically moved, so that the mechanical device 420 can insert and remove the substrate, and the substrate can enter and exit the plurality of processing positions 402, 404 on the processing platform 413. 406, 40 8, 410, 412, 414, 416. The process position may be an electroless plating chamber electrochemical processing chamber, a substrate washing chamber and/or a drying chamber, a substrate bevel cleaning chamber, a substrate surface cleaning to or pre-wash chamber, and/or other processing chambers that facilitate electrical forging processes. . Preferably, embodiments of the present invention are implemented at least within the process locations 4, 2, 404, 406, 408, 41 0, 4 12 . ECPS 400 also includes the work interface (Fl) 430. Does pi 430 generally include at least one? 1 Mechanical device 43 2' and located on the side of 1 to 1 430 adjacent to the process platform 413. The FI mechanism 432 can be configured to pick up the substrate 426 in the substrate cassette 434. The FI mechanism 432 transfers the substrate 426 to one of the process locations 414 or 41 6 ' to begin the processing sequence. Similarly, the FI mechanism 432 can be used to retrieve the substrate in process position 414 or 416 after the substrate processing procedure is completed. At this point, the 'FI mechanism 432 can transfer the substrate 426 37 1376433 back to the card E434 and out of the system 400. Furthermore, the mechanical device 432 can also extend to the connection channel 415 of the connection waste interface 430 and the process platform 413. In addition, can the mechanical device 432 enter the connection? Annealing Chamber 143 43 In accordance with an embodiment of the present invention comprising an electric enthalpy treatment, the anneal chamber 'n is preferably used as the electropolymerization processing chamber 31A described above in connection with Figure 3A. This is because the 430 is best used to handle and process dry substrates, and the @platform (1) is best used to handle and process wet substrates.

電化學電鍵室 第5圖為電化學電鍍室之一實施例的局部剖面圖，以 下稱之為電鍍室500,其可用於第4圖的製程位置4〇2、 4〇4、406、4〇8、41〇、412、414、416。電鍍室5〇〇一般包 括電鍍頭組件600、框架構件5〇3、外盆5〇1、和位在外盆 501内的内盆502。Electrochemical Key Chamber 5 is a partial cross-sectional view of an embodiment of an electrochemical plating chamber, hereinafter referred to as a plating chamber 500, which can be used in the process positions 4, 2, 4, 4, 406, 4 of Figure 4 8, 41, 412, 414, 416. The plating chamber 5 generally includes a plating head assembly 600, a frame member 5〇3, an outer basin 5〇1, and an inner basin 502 positioned within the outer basin 501.

電鍍頭组件600包括接收構件6 0 1，以於沈浸至電化 學處理液與電化學處理時來支撐與轉動基材。在此實施例 中’接收構件601包括被裝載空間606隔開的接觸環6〇2 與推盤組件6〇4。接觸環602可電氣接觸基材周圍，藉以 施加所需電偏壓到基材。接觸環602更可包括設在基材表 面附近的參考電極。更詳細的接觸環602與推盤組件6〇4 之說明可參見共同受讓之美國專利申請案號i 〇/2 78,527、 申請曰為西元2002年10月22曰、名稱「藉由塑形接觸環 來控制電銀之均勻度（Plating Uniformity Control By Contact Ring Shaping)」的申請案、以及共同受讓之美國 38 1376433 專利證書號6,251，236、名稱*「用认 顔严Η r ^ 學沉積的陰極接 觸環（Cathode Contact Ring 〇r ElectrochemicalThe plate head assembly 600 includes a receiving member 601 for supporting and rotating the substrate upon immersion in the electrochemical treatment fluid and electrochemical treatment. The receiving member 601 in this embodiment includes a contact ring 6〇2 and a pusher assembly 6〇4 separated by a loading space 606. Contact ring 602 can electrically contact the periphery of the substrate to apply the desired electrical bias to the substrate. Contact ring 602 may further include a reference electrode disposed adjacent the surface of the substrate. A more detailed description of the contact ring 602 and the pusher assembly 6〇4 can be found in the commonly assigned U.S. Patent Application Serial No. i 〇/2 78,527, filed on Oct. 22, 2002, entitled "by Forming Contact "Plating Uniformity Control By Contact Ring Shaping" application, and the commonly assigned US 38 1376433 Patent Certificate No. 6,251,236, name * "Used Yan Yan Η r ^ Cathode Contact Ring 〇r Electrochemical

Dep〇sltl〇n)J的申請案，其均一併附上供 電鍍室500的框架構件5〇3 ^ 偉環形基底構件504於 其上部。由於框架構件5 03的一側為 调1為棱向，故基底構件5〇4The application of Dep〇sltl〇n)J is attached to the upper portion of the frame member 5〇3 of the plating chamber 500. Since one side of the frame member 530 is adjusted to be an angling, the base member 5〇4

的頂面-般會對應框架構件5G3的傾角而水平傾斜相同角 度》基底構件504包括盤形陽極5〇5。電锻室5〇〇可傾斜 設置’即，可提高電錄室500之框架構件5〇3的一側，使 電鍍室500的元件傾斜約3度至約3〇度。 内盆5 02叙含有電化學處理基材的處理液’例如電 鍍液或陰極前處理溶液。處理過程中，處理液―般為連續 供應給内盆5 02，因此處理液為持續溢流出内盆5〇2的最 面點502&(—般稱為”堰’’）’並由外盆5〇1收集後排出以供 化學處理與回收。電化學處理室的例子更可參見共同受讓The top surface will generally be inclined horizontally by the same angle corresponding to the inclination of the frame member 5G3. The base member 504 includes a disk-shaped anode 5〇5. The electric forging chamber 5 〇〇 can be tilted to set 'i.e., one side of the frame member 5〇3 of the electric recording chamber 500 can be raised, and the components of the plating chamber 500 can be inclined by about 3 degrees to about 3 degrees. The inner pot 502 describes a treatment liquid containing an electrochemically treated substrate, e.g., an electroplating solution or a cathodic pretreatment solution. During the treatment, the treatment liquid is generally continuously supplied to the inner basin 502, so the treatment liquid is the outermost point 502 & (generally referred to as "堰'')) of the inner basin 5〇2 and overflows from the outer basin. 5〇1 is collected and discharged for chemical treatment and recovery. Examples of electrochemical treatment chambers can be found in the joint transfer.

之美國專利申請案號10/268,284、申請曰為西元2002年 10 月 9 日、名稱「電化學處理室（Eiectrochemical Processing Cell)」的申請案，其主張美國專利臨時申請案號 60/398,345、中請日為西元2〇〇2年7月24日之中請案的 優先權，二者皆一併附上供作參考。 根據電化學處理之一實施例，例如配合第6圖說明於 下的基材處理程序610，基材可傳送到電化學處理室（例如 電鍵室500)’且面朝下放置在接觸環602上。推盤組件604 於處理時來維持基材位置。基材接著浸入内盆502中的電 解液，且其由接觸環6〇2轉動的速度通常介於約5 rpm至 < S ) 39 1376433U.S. Patent Application Serial No. 10/268,284, filed on October 9, 2002, entitled "Eiectrochemical Processing Cell", which claims U.S. Patent Provisional Application No. 60/398,345, Please refer to the priority of the case filed on July 24, 2002. Both are attached for reference. According to one embodiment of the electrochemical treatment, the substrate can be transferred to the electrochemical processing chamber (e.g., the key chamber 500) and placed face down on the contact ring 602, for example, in conjunction with the substrate processing procedure 610 illustrated in FIG. . The pusher assembly 604 maintains the position of the substrate during processing. The substrate is then immersed in the electrolyte in the inner pot 502 and its speed of rotation by the contact ring 6〇2 is typically between about 5 rpm to <S) 39 1376433

約60rpm之間。電解液可包含不含鋼的酸性溶液 '含錯合 銅的鹼性溶液、或傳統含銅的酸性溶液，其視處理基材的 製程而定。接觸環602在處理過程中轉動基材的轉速為約 10 rpm至約1 00 rpm。處理時間視各特定製程而定，如陰 極前處理製程、種晶層沉積製程、種晶層與溝填層沉積製 程等。處理完後，接著移除偏壓，並將基材移到電解液與 内盆502的最高點502a上方而移出電鍍室500。在移出電 鐘室5〇0前，基材可以约1〇〇 rpm至1000 rpm的轉速旋轉 約1秒至1 0秒，以移除基材上多餘的電解液。 處理程序 第6圖為基材處理程序610的流程圖》本發明之實施 例包括沉積金屬層至基材上之阻障層及/或黏著層的方 法，其包括： 陰極前處理步驟611:在含酸之處理浴中陰極前處理 阻障層或黏著層。Between about 60 rpm. The electrolyte may comprise an acidic solution containing no steel, an alkaline solution containing copper, or a conventional copper-containing acidic solution, depending on the process of treating the substrate. Contact ring 602 rotates the substrate at a speed of from about 10 rpm to about 100 rpm during processing. Processing time depends on each specific process, such as cathode pretreatment process, seed layer deposition process, seed layer and trench fill deposition process. After processing, the bias is then removed and the substrate is moved over the electrolyte and the highest point 502a of the inner pot 502 to exit the plating chamber 500. The substrate may be spun from about 1 rpm to 1000 rpm for about 1 second to 10 seconds before removing the clock chamber 5 〇 0 to remove excess electrolyte from the substrate. Process Figure 6 is a flow diagram of a substrate processing program 610. An embodiment of the invention includes a method of depositing a metal layer onto a barrier layer and/or an adhesion layer on a substrate, comprising: a cathode pretreatment step 611: The cathodic pretreatment barrier layer or adhesive layer in the acid-containing treatment bath.

種晶層沉積步驟6 1 2 :沉積連續且無孔隙之種晶層至 經陰極前處理的膜層上。 溝填層沉積步驟6丨3 _·沉積溝填層至種晶層上。 選擇性過填沉積步驟614 :選擇性過填沉積一 ECP過 填層。 根據一實施例，陰極前處理步驟6 11為用來處理基材 表面，如第2圖的導電基材表面114。如上述，陰極前處 理步驟6 1 1可降低形成均勻、無孔隙且保型之金屬層至阻 40 1376433Seed layer deposition step 6 1 2: depositing a continuous and void-free seed layer onto the cathodized pretreated layer. The trench fill deposition step 6丨3 _· deposits the trench to the seed layer. A selective overfill deposition step 614: selective overfill deposition of an ECP overfill. According to an embodiment, the pre-cathode treatment step 611 is a conductive substrate surface 114 as used to treat the surface of the substrate, such as Figure 2. As described above, the pre-cathode treatment step 61 1 can reduce the formation of a uniform, non-porous and conformal metal layer to the resistance 40 1376433

障層上所需的臨界電流密度。 其次進行種晶層沉積步驟 6 1 2，藉由使用 電化學電鍍製程來直接電鍍種晶層（如第2圖的 至導電基材表面114。在一實施例中，成核脈 善種晶層的品質。在一實施例中，陰極前處理 種晶層沉積步驟 612是在相同的電化學處理 (如參照第4圖說明的ECPS 400)，以缩短經陰 面接觸氧氣或環境污染物的時間為數分鐘、 鐘。如此可盡量避免經處理之阻障層表面在沉 形成不當的沉積物。 接著進行溝填層沉積步驟6 1 3，藉由使用 浴的電化學溝填製程來電鍍溝填層（如第2圖的 至種晶層1 11上。在一實施例中，種晶層沉積 溝填層沉積步驟613是依序在使用相同電鍍液 室中進行。此特別適用於溝填小於6 5奈米大小 徵結構；如此小的内連線特徵結構易受溝填時 隙、和種晶層與溝填層介面之多餘沉積物的影 步驟為使用單一浴槽，在進行溝填層沉積步驟 晶層表面從未接觸大氣，故可減少不欲之氧化 再者，溝填層沉積步驟6 1 3為緊接在種晶層沉 之後進行，因此有機污染物實際上也沒有時間 層表面。 接著於基材上進行過填沉積步驟614，其’ 層（如過填層1 1 3)可以沉積來完成内連線結構。 錯合鹼浴的 |種晶層111) 衝是用來改 步驟611與 系統中進行 極處理之表 甚至為數秒 積種晶層前 上述錯合驗 溝填層112) 步驟612與 的同一電鍍 的内連線特 所形成之孔 響。由於二 613前，種 反應發生。 積步驟612 聚集到種晶 中ECP過填 在一實施例 41 1376433The critical current density required on the barrier. Next, a seed layer deposition step 612 is performed to directly electroplate the seed layer by using an electrochemical plating process (such as the conductive substrate surface 114 of FIG. 2. In one embodiment, the nucleation pulse seed layer In one embodiment, the cathodic pretreatment seed layer deposition step 612 is performed at the same electrochemical treatment (e.g., ECPS 400 as described with reference to Figure 4) to reduce the time of contact with oxygen or environmental contaminants through the labyrinth. Minutes, clocks. This avoids the formation of improper deposits on the surface of the treated barrier layer. Next, the trench fill deposition step 613 is used to electroplate the trench fill by using the electrochemical trench fill process of the bath ( The seed layer 1 11 is as shown in Fig. 2. In one embodiment, the seed layer deposition trench fill deposition step 613 is performed sequentially in the same plating bath chamber. This is particularly suitable for trench filling less than 6 5 Nano-size structure; such a small interconnect feature is susceptible to trench filling time slots, and the excess deposits of the seed layer and the trench fill interface are the use of a single bath, in the trench fill deposition step The surface of the layer never touches the atmosphere Therefore, the oxidation of the unwanted oxidation can be reduced, and the deposition step of the trench filling layer is performed immediately after the seed layer is deposited, so that the organic contaminant does not actually have the surface layer of the time layer. Depositing step 614, the 'layer (such as overfill layer 133) can be deposited to complete the interconnect structure. The mismatched alkali bath | seed layer 111) is used to modify step 611 and the system for pole treatment The table even has the hole formed by the same electroplated interconnects in step 612 and the above-mentioned misaligned trench fill layer 112. Since the second 613, the species reaction occurred. The accumulation step 612 is concentrated into the seed crystal where the ECP is overfilled in an embodiment 41 1376433

中’溝填層沉積步驟613與過填沉積步驟614是依序在使 用相同電鍵液的同一電鍍室中進行。如此可避免溝填層在 進行過填沉積步驟614前已遭氧化和有機污染。在另一實 施例中’過填沉積步驟614是採用傳統酸性電解液ECP製 輕°在此實施例中，溝填層沉積步驟613與過填沉積步驟 614之間增加—道洗滌步驟，以免ECP過填步驟所用的電 鍵液父又污染。增加的洗滌步驟可在專門的洗蘇室中進 行’洗蘇室較佳是設在實行基材處理程序610的同一電化 學處理系統中。基材以水溶液洗滌且轉速為約2〇 rpm至約 40 0 rpm ’隨後並以氣流乾燥及/或旋乾。由於酸液與鹼液 本質上即不相容’且各電鍍液之有機添加劑的交互污染問 題嚴重’因此對每一待處理之基材而言，溝填層沉積步驟 6 1 3與過填沉積步驟6丨4之間必須確實清洗電鍍室。較佳 反而是使用二個分開的ECP室於基材的孔洞120中形成銅 層110 :其^ —反應室為專門進行以鹼為基礎的電鍍製程 (即種晶層沉積步驟612與溝填層沉積步驟613)，另一反 應至則專門進行以酸為基礎的電鑛製程（即過填沉積步驟 6 1 4)。為縮紐過填沉積步驟6丨4前的等待時間及減少溝填 層的關聯氧化反應與污染’二個ECP室最好皆設在同一基 材處理平D ’如配合第4圖說明於上的電鍍系統。過填沉 積步驟614特別有助於同時填充基材表面上的大型内連線 特徵，’。構與小型内連線特徵結構。小型内連線特徵結構（或 具问冰寬比）是利用溝填層沉積步驟6丨3來填充而大型内 連線特徵結構（或具低深寬比）是利用沉積速率較快的Ecp 42 1376433The middle trench fill deposition step 613 and the overfill deposition step 614 are performed sequentially in the same plating chamber using the same key fluid. This avoids oxidation and organic contamination of the trench fill layer prior to the overfill deposition step 614. In another embodiment, the 'overfill deposition step 614 is lighter with a conventional acidic electrolyte ECP. In this embodiment, an additional wash step is performed between the trench fill deposition step 613 and the overfill deposition step 614 to avoid ECP. The liquid key used in the overfilling step is contaminated. The additional washing step can be carried out in a dedicated lavatory chamber. The lavage chamber is preferably located in the same electrochemical processing system in which substrate processing program 610 is practiced. The substrate is washed with an aqueous solution and rotated at a speed of from about 2 rpm to about 40 rpm' and subsequently dried and/or spin dried. Since the acid and the alkali are essentially incompatible, and the interaction of the organic additives of the plating solutions is serious, the trench deposition step 613 and the overfill deposition are performed for each substrate to be treated. The plating chamber must be cleaned between steps 6丨4. Preferably, instead of using two separate ECP chambers, a copper layer 110 is formed in the holes 120 of the substrate: the reaction chamber is specifically subjected to an alkali-based plating process (ie, the seed layer deposition step 612 and the trench fill layer). The deposition step 613), the other reaction, is specifically performed on an acid-based electrowinning process (ie, an overfill deposition step 614). Waiting time for the refilling deposition step 6丨4 and reducing the associated oxidation reaction and contamination of the trench fill layer. The two ECP chambers are preferably placed on the same substrate to process the flat D' as described in Fig. 4 Plating system. The overfilling step 614 is particularly helpful in simultaneously filling large interconnect features on the surface of the substrate,'. Structure and small interconnect features. The small interconnect feature (or the ice-to-width ratio) is filled with the trench fill deposition step 6丨3 and the large interconnect feature (or low aspect ratio) is Ecp 42 with a faster deposition rate. 1376433

過填步驟來填充。 根據另一實施例，陰極前處理步驟611為用來處理 材表面，如第2圖的導電基材表面114。如前一實施例 述，陰極前處理步驟611可降低臨界電流密度。 其次，於基材上進行種晶層沉積步驟612，藉由使 錯合鹼浴的電化學電鍍製程來直接電鍍種晶層至導電基 表面114。在一實施例中，成核脈衝是用來改善種晶層 品質。在一實施例中，陰極前處理步驟611與種晶層沉 步驟612是在相同的電化學處理系統中進行。在另一實 例中，基材上最小的内連線特徵結構是於種晶層沉積步 6 1 2填充完成，而較大的内連線特徵結構表面只有形成 型的種晶層。如前一實施例之種晶層沉積步驟6 1 2所述 在同一電化學處理系統中進行陰極前處理步驟611與種 層沉積步驟612有助於避免經處理之阻障層表面在沉積 晶層前形成不當的沉積物。 在溝填層沉積步驟6 1 3中，溝填層為藉由使用上述 統酸浴的電化學溝填製程而電鍍至種晶層1 1 1上。此電 製程不需使用錯合劑。較佳地，溝填層沉積步驟61 3與 晶層沉積步驟612是在不同的電化學處理室中進行，以 開以酸為基礎的電鍍製程和以鹼為基礎的電鍍製程。在 實施例中，種晶層沉積步驟6 1 2與溝填層沉積步驟6 1 3 間增加一道洗滌步驟，以免溝填步驟所用的電鍍液交叉 染《增加的洗滌步驟大致上類似前一實施例之過填沉積 驟6 1 4所述的洗滌步驟。 基 所 用 材 的 積 施 驟 保 > 晶 種 傳 鍍 種 隔 之 步 43 1376433 在過填沉積步驟614中，可沉積ECP過填層來完成内 連線結構。在一實施例中，過填沉積步驟614是採用傳統 的酸性電解液ECP製程。過填沉積步驟614與溝填層沉積 步驟613可在相同的電化學處理室中進行，以避免在溝填 層與過填層的介面形成氧化物或其他表面污染物。在另一 實施例中，過填沉積步驟614與溝填層沉積步驟613是在 相同的電化學處理系統中進行，但在不同的電化學處理室。Fill in the steps to fill. According to another embodiment, the cathodic pre-treatment step 611 is for treating the surface of the material, such as the conductive substrate surface 114 of Figure 2. As in the previous embodiment, the cathodic pretreatment step 611 can reduce the critical current density. Next, a seed layer deposition step 612 is performed on the substrate to directly electroplate the seed layer to the conductive substrate surface 114 by electrochemical plating of the mixed alkali bath. In one embodiment, nucleation pulses are used to improve seed layer quality. In one embodiment, the cathode pretreatment step 611 and the seed layer sinking step 612 are performed in the same electrochemical processing system. In another example, the smallest interconnect features on the substrate are filled in the seed layer deposition step 612, while the larger interconnect features have only formed seed layers on the surface. The pre-cathode pre-treatment step 611 and the seed layer deposition step 612 in the same electrochemical treatment system as described in the previous embodiment of the seed layer deposition step 612 help to prevent the surface of the treated barrier layer from being deposited in the deposited layer. Forming improper deposits before. In the trench fill deposition step 613, the trench fill is electroplated onto the seed layer 11 by an electrochemical trench fill process using the above-described acid bath. This circuit does not require the use of a wrong agent. Preferably, the trench fill layer deposition step 61 3 and the seed layer deposition step 612 are performed in different electrochemical processing chambers to open an acid based plating process and an alkali based plating process. In an embodiment, the seed layer deposition step 612 and the trench fill layer deposition step 613 add a washing step to avoid cross-dyeing of the plating solution used in the trenching step. The increased washing step is substantially similar to the previous embodiment. This is done by filling the washing step described in the deposition step 614. Accumulation of the base material > seed plating step 43 1376433 In the overfill deposition step 614, an ECP overfill layer may be deposited to complete the interconnect structure. In one embodiment, the overfill deposition step 614 employs a conventional acidic electrolyte ECP process. The overfill deposition step 614 and the trench fill deposition step 613 can be performed in the same electrochemical processing chamber to avoid the formation of oxides or other surface contaminants at the interface of the trench fill layer and the overfill layer. In another embodiment, the overfill deposition step 614 and the trench fill deposition step 613 are performed in the same electrochemical processing system, but in different electrochemical processing chambers.

此實施例可在進行陰極前處理步驟6 11時溝填基材上 最小的特徵結構，且沉積種晶層至較大的内連線特徵結 構。接著在單一 ECP室中，於基材上溝填較大的内連線特 徵結構及過填沉積内連線層。此方法將二製程步驟結合到 單一電鍍室，因此可提高電化學處理系統的產率。 第6A圖為基材處理程序610A的流程圖。本發明之實 施例包括沉積金屬層至基材上之合金層的方法，其中合金 由至少50原子％之VIII族金屬與衡量之阻障金屬組成。 此沉積方法包括：This embodiment can be used to fill the smallest feature on the substrate during the pre-cathode pretreatment step 61 and deposit the seed layer to a larger interconnect feature. Next, in the single ECP chamber, a larger interconnect feature structure and an overfilled interconnect interconnect layer are trenched over the substrate. This method combines the two process steps into a single plating chamber, thereby increasing the yield of the electrochemical processing system. Figure 6A is a flow diagram of substrate processing program 610A. Embodiments of the invention include a method of depositing a metal layer onto an alloy layer on a substrate, wherein the alloy is comprised of at least 50 atomic percent of a Group VIII metal and a barrier metal as measured. This deposition method includes:

前處理步驟611A:前處理合金層。 種晶層沉積步驟6 1 2 A :沉積連續且無孔隙之種晶層至 經前處理的合金層上。 溝填層沉積步驟6 1 3 A :沉積溝填層至種晶層上。 前處理步驟611A為用來前處理基材表面，如第2圖 的導電基材表面114。在一實施例中，前處理步驟為採用 配合第3圖說明於上的陰極還原步驟。如上述，陰極電化 學前處理可降低形成均勻、無孔隙且保型之金屬層至阻障/ < S ) 44 1376433Pre-treatment step 611A: pre-treating the alloy layer. Seed layer deposition step 6 1 2 A: depositing a continuous and void-free seed layer onto the pretreated alloy layer. Ditch fill deposition step 6 1 3 A : deposit a trench fill to the seed layer. The pre-treatment step 611A is for electrically treating the surface of the substrate, such as the conductive substrate surface 114 of Figure 2. In one embodiment, the pre-processing step is a cathodic reduction step as described above in conjunction with Figure 3. As mentioned above, the cathodic electrochemical pretreatment can reduce the formation of a uniform, non-porous and conformal metal layer to the barrier / <S) 44 1376433

黏著層上所需的臨界電流密度，並增進金屬層j 層間的黏著性。陰極電化學前處理可在含酸之 之浴槽中進行。在鹼浴中進行陰極前處理的 於，若種晶層沉積步驟612A是在鹼浴中進行 現不相容之化學劑交互污染的問題，故在進行 步驟612A前，不需完全洗滌基材。反之，在 中進行陰極前處理亦不需先大量洗滌後再進行 步驟612A。在另一實施例争，前處理步驟611 合第3A圖說明於上的電漿前處理步驟。在電 漿前處理基材確信與陰極電化學前處理一樣可 黏著性及降低CCD。 無論是陰極電化學前處理步驟、或是電 驟，前處理步驟6 1 1 A與後續進行之種晶層沉年 較佳是在相同的電化學處理系統中進行，如參 明的ECPS 400。如此可縮短經處理之表面接觸 污染物的時間為數分鐘、甚至為數秒鐘，並可 之阻障層表面在沉積種晶層前形成不當的沉積 前處理步驟6 1 1 A與種晶層沉積步驟6 1 2 A間的 精確控制；若前處理步驟6 1 1 A與種晶層沉積步 在不同的基材處理平台中進行，則二步驟間的 變得較長且多變，以致電子元件特性出現不期 異。 接著於基材上進行種晶層沉積步驟612A， (如第2圖的種晶層111)為藉由電化學電鍍製 薄阻障/黏著 浴槽或含鹼 主要好處在 ，則不會出 種晶層沉積 含酸之浴槽 種晶層沉積 A為採用配 鍍前先以電 增進銅層的 聚前處理步 夤步驟6 1 2 A 照第4圖說 氧氣或環境 避免經處理 物。另外， 等待時間可 •驟612A是 等待時間將 望產生之變 其中種晶層 程而直接電 45 1376433The critical current density required on the adhesion layer and the adhesion between the layers of the metal layer j. Cathodic electrochemical pretreatment can be carried out in a bath containing acid. Cathodic pretreatment in an alkali bath, if the seed layer deposition step 612A is a problem of incompatible chemical cross-contamination in an alkali bath, the substrate need not be completely washed prior to performing step 612A. Conversely, the pre-cathode treatment does not require a large amount of washing before proceeding to step 612A. In another embodiment, pre-processing step 611 and Figure 3A illustrate the pre-plasma processing steps. Pretreatment of the substrate with the plasma is believed to be as adherent as the cathodic electrochemical pretreatment and to reduce the CCD. Whether it is a cathodic electrochemical pretreatment step or a step, the pretreatment step 61 1 A and subsequent seed layer precipitation are preferably carried out in the same electrochemical treatment system, such as the reference ECPS 400. Thus, the surface of the treated surface is exposed to contaminants for a few minutes or even seconds, and the surface of the barrier layer is improperly formed before the deposition of the seed layer. The pre-deposition treatment step 61 1 A and the seed layer deposition step Precise control between 6 1 2 A; if the pre-treatment step 6 1 1 A and the seed layer deposition step are carried out in different substrate processing platforms, the two steps become longer and more varied, so that the electronic component characteristics There is no difference. Then, a seed layer deposition step 612A is performed on the substrate, (such as the seed layer 111 in FIG. 2), which is a main advantage of electrochemically electroplating to form a thin barrier/adhesive bath or alkali, and no seed crystal is formed. Layer deposition of acid-containing bath seed layer deposition A is a pre-polymerization step of electro-promoting the copper layer before plating. Step 6 1 2 A According to Figure 4, oxygen or the environment is avoided. In addition, the waiting time can be 612A is the waiting time will be expected to change. Among them, the seeding layer is directly charged. 45 1376433

鍍至導電基材表面114。在一實施例中，種晶層111 錯合鹼浴來進行電鍍。在另一實施例中，種晶層111 酸浴來進行電鍍，而成核脈衝是用來改善種晶層的品 黏著性。 然後進行溝填層沉積步驟6 1 3A，其中溝填層（如 圖的溝填層11 2)為電鍍至種晶層111上。 在一實施例中，溝填層沉積步驟613A是採用使 合鹼浴的電化學溝填製程。此製程說明於上述”電化學 製程”之章節。在此實施例中，由於種晶層沉積步驟 與溝填層沉積步驟 613A可依序在同一基材處理室 行，因此種晶層沉積步驟6 1 2 A較佳為在錯合鹼浴中ϋ 因此二製程步驟使用單一電鍍室與溶液，故在進行溝 沉積步驟613Α前，種晶層表面從未接觸大氣，而可 不欲之氧化反應發生。再者，溝填層沉積步驟613Α 接在種晶層沉積步驟6 1 2 Α之後進行，因此有機污染 際上也沒有時間聚集到種晶層表面。此特別適用於溝 於6 5奈米尺寸的内連線特徵結構；如此小的内連線特 構易受溝填時所形成之孔隙、和種晶層與溝填層介面 餘沉積物的影響。最後，此方法將二製程步驟結合到 電鍍室，因而可提高電化學處理系統的產率。 在另一實施例中，溝填層沉積步驟6 1 3 A是採用 酸性電解質的電化學溝填製程。此製程說明於上述’’電 電鍍製程”之章節。在此實施例中，使種晶層沉積步驟 與溝填層沉積步驟6 1 3 A依序在相同的酸性電解液中 使用 使用 質與 第2 用錯 電鍍 612A 中進 i行。 填層 減少 為緊 物實 填小 徵結 之多 單一 使用 化學 612A 進行 46 1376433Plated to conductive substrate surface 114. In one embodiment, the seed layer 111 is plated with an alkali bath. In another embodiment, the seed layer 111 is acid bathed for electroplating, and the nucleation pulse is used to improve the adhesion of the seed layer. Then, a trench fill deposition step 6 1 3A is performed in which a trench fill layer (such as the trench fill layer 11 2) is electroplated onto the seed layer 111. In one embodiment, the trench fill layer deposition step 613A is an electrochemical trench fill process using a combined alkali bath. This process is described in the section "Electrochemical Processes" above. In this embodiment, since the seed layer deposition step and the trench fill layer deposition step 613A can be sequentially performed in the same substrate processing chamber, the seed layer deposition step 6 1 2 A is preferably in a miscellaneous alkali bath. Therefore, the two process steps use a single plating chamber and solution, so that before the trench deposition step 613 is performed, the surface of the seed layer is never exposed to the atmosphere, and an unwanted oxidation reaction may occur. Furthermore, the trench fill deposition step 613 is performed after the seed layer deposition step 6 1 2 , so that there is no time for organic contamination to accumulate on the surface of the seed layer. This is especially suitable for the internal interconnect characteristics of the trenches of 65 nm; such small interconnects are susceptible to pores formed during trench filling, and the effects of seed layer and trench fill interface residual deposits. . Finally, this method incorporates a two-process step into the plating chamber, thereby increasing the yield of the electrochemical processing system. In another embodiment, the trench fill deposition step 613 A is an electrochemical trench fill process using an acidic electrolyte. This process is described in the section of ''Electroplating Process''. In this embodiment, the seed layer deposition step and the trench fill layer deposition step 6 1 3 A are sequentially used in the same acidic electrolyte. 2 Use the wrong plating 612A to enter the i line. The filling layer is reduced to the tight matter of the small stagnation of the single use of chemical 612A for 46 1376433

的理由如同前一實施例（即種晶層沉積步驟612A與溝填 沉積步驟613A皆依序在錯合之鹼性電鍍液中進行）所述 在又一實施例中，種晶層沉積步驟612A是採用使 錯合鹼浴的直接電鍍製程，而溝填層沉積步驟613A是 用使用酸性電解液的傳統製程。在此實施例中，種晶層 積步驟6 1 2 A與溝填層沉積步驟6 1 3 A之間增加一道洗滌 驟，以免不相容的電鍍液交叉污染。增加的洗滌步驟可 專門的洗蘇室中進行，洗蘇室較佳是設在與實行基材處 程序6 1 Ο A相同的電化學處理系統。基材以水溶液洗滌 轉速為約2 0 r p m至約1 0 0 rp m，隨後並以氣流乾燥及/或 乾。由於酸液與鹼液本質上即不相容，且各電鍍液之有 添加劑的交互污染問題嚴重，因此對每一待處理之基材 言，種晶層沉積步驟6 1 2 A與溝填層沉積步驟6 1 3之間 須確實清洗電鍍室。較佳反而是使用二個分開的ECP室 於基材的孔洞120中形成銅層110;其中一反應室為專 進行以鹼為基礎的電鍍製程（即種晶層沉積步驟6 1 2A)， 一反應室則專門進行以酸為基礎的電鍍製程（即溝填層 積步驟613A)。為縮短溝填層沉積步驟613A前的等待時 及減少種晶層之相關聯氧化反應與污染，二個ECP室最 皆設在同一基材處理平台，如配合第4圖說明於上的電 系統。 儘管本發明已以數個較佳實施例揭露如上，然任何 習此技藝者，在不脫離本發明之精神和範圍内，當可作 種之更動與潤飾。 層 〇 用 採 沉 步 在 理 且 旋 機 而 必 而 門 另 沉 間 好 鍍 熟 各 47 1376433 雖然本發明已以數個實施例揭露如上，然在不脫離本 發明之精神和範圍内亦可得到其他實施例，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】The reason is the same as in the previous embodiment (ie, the seed layer deposition step 612A and the trench fill deposition step 613A are sequentially performed in the misaligned alkaline plating solution). In still another embodiment, the seed layer deposition step 612A The direct plating process for the miscible alkali bath is employed, and the trench fill deposition step 613A is a conventional process using an acidic electrolyte. In this embodiment, a seeding step 6 1 2 A is added to the trench fill deposition step 6 1 3 A to prevent cross-contamination of the incompatible plating solution. The additional washing step can be carried out in a dedicated lavatory chamber which is preferably provided in the same electrochemical processing system as the procedure 6 1 Ο A at the substrate. The substrate is washed with an aqueous solution at a rate of from about 20 r p m to about 10 rpm, and then dried and/or dried by a stream. Since the acid solution and the alkali solution are intrinsically incompatible, and the problem of cross-contamination of the additives in each plating solution is serious, for each substrate to be processed, the seed layer deposition step 6 1 2 A and the trench fill layer The plating chamber must be cleaned between deposition steps 6 1 3 . Preferably, instead of using two separate ECP chambers, a copper layer 110 is formed in the holes 120 of the substrate; one of the reaction chambers is dedicated to an alkali-based plating process (ie, seed layer deposition step 6 1 2A), The reaction chamber is specifically subjected to an acid-based plating process (i.e., trench filling step 613A). In order to shorten the waiting time before the trench filling deposition step 613A and reduce the associated oxidation reaction and pollution of the seed layer, the two ECP chambers are most disposed on the same substrate processing platform, as described in Fig. 4 . Although the invention has been described above in terms of several preferred embodiments, it will be apparent to those skilled in the art that the invention can be modified and modified without departing from the spirit and scope of the invention. The layer 〇 〇 采 采 采 且 旋 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 Other embodiments, therefore, the scope of the present invention is defined by the scope of the appended claims. [Simple description of the map]

為讓本發明之上述特徵更明顯易懂，可配合參考實施 例說明，其部分乃繪示如附圖式。須注意的是，雖然所附 圖式揭露本發明特定實施例，但其並非用以限定本發明之 精神與範圍，任何熟習此技藝者，當可作各種之更動與潤 飾而得等效實施例。 第1 A-1 E圖繪示銅内連線製造流程之各階段的基材剖 面圖。 第2及2A圖繪示形成於基材上的銅層，其可包含多 層由不同電化學電鍍法沉積而得的銅層。 第3圖為電鑛過程中基材表面之臨界電流密度與電鍍 浴之硫酸濃度的關係圖。In order to make the above features of the present invention more comprehensible, the description may be made in conjunction with the reference embodiments. It is to be understood that the specific embodiments of the invention are not to be construed as limiting the scope of the invention. . Figure 1 A-1 E shows a cross-sectional view of the substrate at each stage of the copper interconnect process. 2 and 2A illustrate a copper layer formed on a substrate, which may comprise a plurality of layers of copper deposited by different electrochemical plating methods. Figure 3 is a graph showing the relationship between the critical current density of the substrate surface and the sulfuric acid concentration of the plating bath during the electrominening process.

第3A圖為電漿表面處理室的簡要剖面示意圖。 第4圖為電化學處理系統的上視圖，其可施行本發明 之方法。 第5圖繪示可施行本發明方法之電鍍室之實例和電鍍 頭組件的剖面圖。 第6及6 A圖為本發明實施例之處理基材的流程圖。 為清楚說明，各圖中共通的元件以相同的標號表示。 48 (S ) 1376433Figure 3A is a schematic cross-sectional view of the plasma surface treatment chamber. Figure 4 is a top view of an electrochemical processing system that can perform the method of the present invention. Figure 5 is a cross-sectional view showing an example of a plating chamber and a plating head assembly in which the method of the present invention can be carried out. Figures 6 and 6A are flow diagrams of a substrate for processing in accordance with an embodiment of the present invention. For the sake of clarity, the elements in common in the figures are denoted by the same reference numerals. 48 (S ) 1376433

【主 要元件符號說明】 100 基材 102 介電層 104 接觸層 106 阻障層 106A 阻障/黏著層 108 内層 110 銅層 111 種晶層 112 溝填層 113 過填層 114 表面 120 孔洞 120a 側壁 3 10 預洗室/電漿處理室 3 12 支撐構件 3 14 封閉區 3 16 圓頂 3 17 線圈 3 18 中央座板 320 凹處 322 絕緣板 324 間隙 326 基材 328 斜面部份 330 平面 332 定位銷 400 系統/ECPS 402、 404 、 406 、 408 ' 410 、 412、 414 ' 416 製程位： 4 13 平台 415 連結通道 420、 432 機械裝置 422、 424 機械臂 426 基材 430 工廠介面/FI 434 卡匣 435 退火室 500 電鍍室 50 1 外盆 502 内盆 502a 最南點 503 框架構件 504 基底構件 505 陽極 600 電鍍頭組件 49 1376433 601 接收構件 602 接觸環 604 推盤组件 606 裝載空間 6 1 Ο、6 1 0A 程序[Main component symbol description] 100 substrate 102 dielectric layer 104 contact layer 106 barrier layer 106A barrier/adhesion layer 108 inner layer 110 copper layer 111 seed layer 112 trench fill layer 113 overfill layer 114 surface 120 hole 120a sidewall 3 10 Prewashing chamber/plasma processing chamber 3 12 Support member 3 14 Enclosed area 3 16 Dome 3 17 Coil 3 18 Central seat plate 320 Recess 322 Insulation plate 324 Clearance 326 Substrate 328 Beveled portion 330 Plane 332 Locating pin 400 System/ECPS 402, 404, 406, 408 '410, 412, 414 ' 416 Process bits: 4 13 Platform 415 Linking Channels 420, 432 Mechanism 422, 424 Robot Arm 426 Substrate 430 Factory Interface / FI 434 Card 435 Annealing Chamber 500 Plating chamber 50 1 Outer basin 502 Inner basin 502a Southmost point 503 Frame member 504 Base member 505 Anode 600 Plating head assembly 49 1376433 601 Receiving member 602 Contact ring 604 Pusher assembly 606 Loading space 6 1 Ο, 6 1 0A Procedure

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Claims (1)

"---一 — 十、申請專利範圍： •—種處理-基材的方法，該方法至少包含以下步驟： 提供一介電層至一基材上； 形成複數個特徵結構（feature )於該介電層之一表面； 沉積一電性連續之阻障/黏著層至該介電層表面其中 該阻障/黏箸層包含一合金，至少50原子％ (atomic%)的 該合金包含一金屬，該金屬選自由釕 '铑、鈀、钻、鎳、 锇、銥、鉑、和其組合物所構成之群組，且該合金的其餘 衡量（balance)原子選自由鈕 '鈦、锆、铪 '鈮、鉬、鎢、 和其組合物所構成之群組；以及 直接電鍍一第一銅層至該阻障/黏著層上，該第一銅層 為一電性連續層，其中該直接電鍍該第一銅層的步驟包含： 置入該阻障/黏著層至一銅溶液中，使該阻障/黏著 層接觸該鋼溶液’其中該銅溶液包含複數個銅離子；以 及 施加一第一電鍍波形至該阻障/黏著層。- 2.如申請專利範圍第1項所述之方法，更包含在電鍍該第 一銅層前’在一含酸之浴槽内藉由陰極前處理該阻障/黏著 層以調整（c〇nditioning )該電性連續之阻障/黏著層表面 的狀況。 51 1376433 3.如申請專利範圍第1項所述之方法，其t該含酸之浴槽 包含一硫酸，其中該硫酸濃度為約10 g/Ι與約50 g/Ι。 4.如申請專利範圍第1項所述之方法，其中陰極前處理該 阻障/黏著層的步驟更包含以約 1 mA/cm2至約 5 mA/cm2 的電流密度範圍來施行該陰極前處理。"---1, 10, the scope of application for patents: • A method of processing - a substrate, the method comprising at least the steps of: providing a dielectric layer to a substrate; forming a plurality of features a surface of one of the dielectric layers; depositing an electrically continuous barrier/adhesion layer to the surface of the dielectric layer, wherein the barrier/adhesive layer comprises an alloy, and at least 50 atom% of the alloy comprises a a metal selected from the group consisting of ruthenium, palladium, diamond, nickel, ruthenium, osmium, platinum, and combinations thereof, and the balance atoms of the alloy are selected from the group consisting of titanium, zirconium, a group of 铪'铌, molybdenum, tungsten, and a combination thereof; and directly plating a first copper layer onto the barrier/adhesive layer, the first copper layer being an electrically continuous layer, wherein the direct The step of electroplating the first copper layer comprises: placing the barrier/adhesive layer into a copper solution, contacting the barrier/adhesive layer with the steel solution, wherein the copper solution comprises a plurality of copper ions; and applying a A plating waveform is applied to the barrier/adhesive layer. - 2. The method of claim 1, further comprising: pre-treating the barrier/adhesive layer by a cathode in an acid-containing bath before plating the first copper layer (c〇nditioning) The condition of the electrical continuous barrier/adhesive layer surface. The method of claim 1, wherein the acid-containing bath comprises monosulfuric acid, wherein the sulfuric acid concentration is about 10 g/Ι and about 50 g/Ι. 4. The method of claim 1, wherein the step of pretreating the barrier/adhesive layer by the cathode further comprises performing the cathodic pretreatment at a current density range of from about 1 mA/cm2 to about 5 mA/cm2. . 5.如申請專利範圍第1項所述之方法，其中該陰極前處理 所施行的一電位相對於氣化銀（AgCl)為介於約0伏特至約 -1.0伏特的範圍。 6.如申請專利範圍第1項所述之方法，其中施加該第一電 鍍波形至該阻障/黏著層的方法更包含：5. The method of claim 1, wherein the potential of the cathodic pretreatment is in the range of from about 0 volts to about -1.0 volts relative to the vaporized silver (AgCl). 6. The method of claim 1, wherein the method of applying the first plating waveform to the barrier/adhesive layer further comprises: 施加一成核波形至該阻障/黏著層，該成核波形是配置 以產生一第一電流密度，該第一電流密度遍及該阻障/黏著 層且大於一臨界電流密度。 7.如申請專利範圍第1項所述之方法，更包含在該第一銅 層與該銅溶液接觸時，施加一第二電鍍波形至該第一銅層 以沉積一第二銅層至該第一銅層上。 8.如申請專利範圍第1項所述之方法，其中該銅溶液更包 含一錯合劑、複數個錯合銅離子、且一 pH值等於或大於 52 1376433 7·0。 9.如申請專利範圍第8項所述之方法，更包含沉積一第二 銅層至該第一銅層上，其中沉積該第二銅層的步驟包含： 置入該第一銅層至一第二銅溶液中，其中該第二銅溶液 為酸性且包括複數個自由銅離子；以及 施加一第二電鍍波形至該第一銅層。A nucleation waveform is applied to the barrier/adhesion layer, the nucleation waveform being configured to produce a first current density throughout the barrier/adhesive layer and greater than a critical current density. 7. The method of claim 1, further comprising applying a second plating waveform to the first copper layer to deposit a second copper layer when the first copper layer is in contact with the copper solution. On the first copper layer. 8. The method of claim 1, wherein the copper solution further comprises a complexing agent, a plurality of complex copper ions, and a pH equal to or greater than 52 1376433 7·0. 9. The method of claim 8, further comprising depositing a second copper layer onto the first copper layer, wherein depositing the second copper layer comprises: implanting the first copper layer to In the second copper solution, wherein the second copper solution is acidic and includes a plurality of free copper ions; and applying a second plating waveform to the first copper layer. 1 0.如申請專利範圍第1項所述之方法，其中該阻障/黏著 層包含一釕钽合金，其具有至少50原子％之釕，且該合金 之其餘衡量比例為组。 11. 一種電鍍一黏著銅層至一阻障層上的方法，該方法至 少包含以下步騾：The method of claim 1, wherein the barrier/adhesive layer comprises a tantalum alloy having at least 50 atomic percent and the remaining proportion of the alloy is a group. 11. A method of electroplating an adhesive copper layer onto a barrier layer, the method comprising at least the following steps: 沉積一電性連續之阻障/黏著層至一基材表面，其中該 阻障/黏著層包含一釕钽合金，其具有約70原子％至95原 子％之釕，且該合金之其餘衡量比例的组； 藉由陰極前處理該阻障/黏著層以調整該電性連續之阻 障/黏著層表面狀況；以及 直接電鍍一第一銅層至該阻障/黏著層上，該第一銅層 為一電性連續層，其中直接電鍍該第一銅層的步驟包含： 置入該基材表面至一銅溶液中，使該基材表面接觸 該銅溶液，其中該銅溶液包含複數個銅離子；以及 53 1376433 施加一第一電鍍波形至該基材表面。 12.如申請拳利範圍第11項所述之方法，其中該釕鈕合金 鄰近該阻障/黏著層與該第一銅層間之介面富含釕，而鄰近 該阻障/黏著層與該介電層間之介面富含纽。Depositing an electrically continuous barrier/adhesive layer to a substrate surface, wherein the barrier/adhesive layer comprises a tantalum alloy having a tantalum of from about 70 atomic percent to 95 atomic percent, and the remaining proportion of the alloy a group; pretreating the barrier/adhesive layer by a cathode to adjust the electrical continuity of the barrier/adhesive layer surface condition; and directly plating a first copper layer onto the barrier/adhesive layer, the first copper The layer is an electrical continuous layer, wherein the step of directly plating the first copper layer comprises: placing the surface of the substrate into a copper solution, contacting the surface of the substrate with the copper solution, wherein the copper solution comprises a plurality of copper Ion; and 53 1376433 apply a first plating waveform to the surface of the substrate. 12. The method of claim 11, wherein the button alloy is rich in germanium adjacent to the interface between the barrier/adhesive layer and the first copper layer, and adjacent to the barrier/adhesive layer and the medium The interface between the electric layers is rich in New Zealand. 13. —種沉積銅至·一基材表面的方法，其中該基材表面包 含一訂组合金，該方法至少包含以下步驟： 沉積一釕链合金至一基材表面上，其中該釕组合金包含 介於約7 0原子 ％至約9 5原子％的釕，以及具有其餘衡量 比例的组； 沉積一第一銅層至該釕组合金上，其中該第一銅層為一 連續銅層，且其中沉積該第一銅層至該釕鉅合金上的步驟 包含：13. A method of depositing copper to a surface of a substrate, wherein the surface of the substrate comprises a predetermined combination of gold, the method comprising at least the steps of: depositing a chain alloy to a surface of the substrate, wherein the combination of gold Having a enthalpy of from about 70 atomic % to about 915 atomic percent, and a group having the remaining measured ratio; depositing a first copper layer onto the tantalum composite gold, wherein the first copper layer is a continuous copper layer, And wherein the step of depositing the first copper layer onto the tantalum giant alloy comprises: 置入該基材表面至一銅溶液中，使該基材表面接觸 該銅溶液；以及 施加一第一電鍍偏壓至該基材表面。 14.如申請專利範圍第13項所述之方法，更包含沉積一第 二銅層至該第一銅層上，其中沉積該第二銅層的步驟包含： 在當與該銅溶液接觸以沈積一第二銅層至該第一銅層 時，施加一第二電鍍偏壓至該基材表面。 54 1376433 15. —種沉積一含銅種晶層至一阻障層上的方法，該方法 至少包含以下步驟： 提供一基材，該基材具有沈積在一基材表面之一阻障 層，其中該阻障層具有一包含一材料之阻障表面，該材料 係選自由下列所組成之群組：鈷、釕、鎢、鈦，以及由中 之兩者或更多者所構之化合物；以及Inserting the surface of the substrate into a copper solution to bring the surface of the substrate into contact with the copper solution; and applying a first plating bias to the surface of the substrate. 14. The method of claim 13, further comprising depositing a second copper layer onto the first copper layer, wherein depositing the second copper layer comprises: depositing in contact with the copper solution for deposition When a second copper layer is applied to the first copper layer, a second plating bias is applied to the surface of the substrate. 54 1376433 15. A method of depositing a copper-containing seed layer onto a barrier layer, the method comprising at least the steps of: providing a substrate having a barrier layer deposited on a surface of the substrate, Wherein the barrier layer has a barrier surface comprising a material selected from the group consisting of cobalt, ruthenium, tungsten, titanium, and a compound composed of two or more of them; as well as 將該基材暴露在一酸性電化學電鍵溶液，該酸性電化學 電鍍溶液包含有機添加劑且施以一電鍍偏壓穿過該基材 表面，藉以直接沈積一含銅種晶層於該阻障表面上而無一 干預層置於其間。 16. 如申請專利範圍第15項所述之方法，其中該電鍍偏壓 具有較氧化該阻障層所需電位更為負值之一電位。 17. 如申請專利範圍第15項所述之方法，其中該電鍍偏壓 具有一電流密度，該電流密度介於約 0.5 mA/cm2與約 5Exposing the substrate to an acidic electrochemical key solution, the acidic electrochemical plating solution comprising an organic additive and applying a plating bias through the surface of the substrate to directly deposit a copper-containing seed layer on the barrier surface There is no intervention layer placed between them. 16. The method of claim 15, wherein the plating bias has a potential that is more negative than a potential required to oxidize the barrier layer. 17. The method of claim 15 wherein the plating bias has a current density of between about 0.5 mA/cm2 and about 5 18. 如申請專利範圍第15項所述之方法，更包含： 在暴露該基材於該電化學電鍍液前先熱退火該阻障層。 19. 一種電化學電鍍一金屬層於一基材上的方法，包含以下 步驟： 提供一基材，該基材具有形成於基材内的一或更多個互 55 137643318. The method of claim 15, further comprising: thermally annealing the barrier layer prior to exposing the substrate to the electrochemical plating solution. 19. A method of electrochemically plating a metal layer onto a substrate, comprising the steps of: providing a substrate having one or more inter-substrate formed in the substrate 55 1376433 連特徵結構； 以保形方式（formally)沈積一阻障層於該基材以及 個或更多個互連特徵結構的暴露表面上，其中該阻障 有一包含一材料之阻障表面，該材料係選自由下列所 之群組：鈷、釕、鎢 '鈦，以及由該等元素所構成之 物；以及 將該基材暴露在一酸性電化學電鍍溶液，該酸性電 電鍍溶液包含有機添加劑且施以一電鍍偏壓穿過該 表面，藉以沈積一含銅種晶層於該阻障表面上而無一 層置於其間；以及 施加一電性偏壓穿過該基材表面，在該酸性電化學 溶液中以銅填充該一或更多個互連特徵結構。 2 0.如申請專利範圍第1 9項所述之方法，其中該電鍍 具有較氧化該阻障層所需電位更為負值之一電位。 21.如申請專利範圍第20項所述之方法，其中該電鍍 具有一電流密度，該電流密度介於約.0.5 mA/cm2與 mA/cm2 之間。 22. 如申請專利範圍第19項所述之方法，更包含： 在暴露該基材於該電化學電鍍液前先熱退火該阻障層 23. 如申請專利範圍第19項所述之方法，更包含： 該一 層具 組成 化合 化學 基材 干預 電鍍 偏壓 偏壓 約 5 56 1376433 在一無氧氣環境中熱退火該銅a feature structure; formally depositing a barrier layer on the exposed surface of the substrate and the one or more interconnect features, wherein the barrier has a barrier surface comprising a material, the material Is selected from the group consisting of cobalt, ruthenium, tungsten 'titanium, and materials composed of the elements; and exposing the substrate to an acidic electrochemical plating solution comprising an organic additive and Applying a plating bias through the surface to deposit a copper-containing seed layer on the barrier surface without a layer therebetween; and applying an electrical bias across the surface of the substrate during the acidification The one or more interconnect features are filled with copper in the solution. The method of claim 19, wherein the plating has a potential that is more negative than a potential required to oxidize the barrier layer. 21. The method of claim 20, wherein the plating has a current density between about 0.5 mA/cm2 and mA/cm2. 22. The method of claim 19, further comprising: thermally annealing the barrier layer 23 prior to exposing the substrate to the electrochemical plating solution. The method of claim 19, More include: The layer consists of a chemical compound substrate that interferes with the plating bias voltage of approximately 5 56 1376433. The copper is thermally annealed in an oxygen-free environment. 5757
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Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050274621A1 (en) * 2004-06-10 2005-12-15 Zhi-Wen Sun Method of barrier layer surface treatment to enable direct copper plating on barrier metal
US7972491B2 (en) * 2004-04-15 2011-07-05 Hitachi Metals, Ltd. Method for imparting hydrogen resistance to articles
US8058164B2 (en) * 2007-06-04 2011-11-15 Lam Research Corporation Methods of fabricating electronic devices using direct copper plating
EP2067879B1 (en) * 2007-07-31 2013-09-04 Nippon Mining & Metals Co., Ltd. Method for producing a PLATED MATERIAL HAVING a METAL THIN FILM FORMED BY ELECTROLESS PLATING
WO2009116347A1 (en) * 2008-03-19 2009-09-24 日鉱金属株式会社 Electronic member wherein barrier-seed layer is formed on base
JP2010080022A (en) * 2008-09-29 2010-04-08 Showa Denko Kk Method of manufacturing vertical magnetic recording medium
US20120261254A1 (en) 2011-04-15 2012-10-18 Reid Jonathan D Method and apparatus for filling interconnect structures
US8206569B2 (en) * 2009-02-04 2012-06-26 Applied Materials, Inc. Porous three dimensional copper, tin, copper-tin, copper-tin-cobalt, and copper-tin-cobalt-titanium electrodes for batteries and ultra capacitors
US20100203391A1 (en) * 2009-02-09 2010-08-12 Applied Materials, Inc. Mesoporous carbon material for energy storage
TWI469219B (en) * 2009-02-16 2015-01-11 Nat Univ Tsing Hua A method for reducing a roughness of a surface of a metal thin film
FR2949121A1 (en) * 2009-08-12 2011-02-18 Alchimer ELECTROLYTE AND METHOD FOR ELECTRODEPOSITION OF COPPER ON A BARRIER LAYER, AND SEMICONDUCTOR SUBSTRATE OBTAINED BY SUCH A METHOD
US20110094888A1 (en) * 2009-10-26 2011-04-28 Headway Technologies, Inc. Rejuvenation method for ruthenium plating seed
US20140103534A1 (en) * 2012-04-26 2014-04-17 Applied Materials, Inc. Electrochemical deposition on a workpiece having high sheet resistance
US9865501B2 (en) 2013-03-06 2018-01-09 Lam Research Corporation Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer
US9496145B2 (en) * 2014-03-19 2016-11-15 Applied Materials, Inc. Electrochemical plating methods
US20150299886A1 (en) * 2014-04-18 2015-10-22 Lam Research Corporation Method and apparatus for preparing a substrate with a semi-noble metal layer
US9469912B2 (en) 2014-04-21 2016-10-18 Lam Research Corporation Pretreatment method for photoresist wafer processing
US9472377B2 (en) 2014-10-17 2016-10-18 Lam Research Corporation Method and apparatus for characterizing metal oxide reduction
US10648096B2 (en) 2014-12-12 2020-05-12 Infineon Technologies Ag Electrolyte, method of forming a copper layer and method of forming a chip
US10903308B2 (en) * 2016-07-13 2021-01-26 Samsung Electronics Co., Ltd. Semiconductor device
CN108149292A (en) * 2016-12-02 2018-06-12 臻鼎科技股份有限公司 Copper clad laminate and preparation method thereof
WO2018125069A1 (en) * 2016-12-28 2018-07-05 Intel Corporation Methods of forming substrate interconnect structures for enhanced thin seed conduction
US10443146B2 (en) 2017-03-30 2019-10-15 Lam Research Corporation Monitoring surface oxide on seed layers during electroplating
US10930511B2 (en) * 2018-03-30 2021-02-23 Lam Research Corporation Copper electrodeposition sequence for the filling of cobalt lined features
TWI711724B (en) 2018-11-30 2020-12-01 台灣積體電路製造股份有限公司 Electrochemical plating system, method for performing electrochemical plating process, and method of forming semiconductor substrate
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
IT201900006740A1 (en) 2019-05-10 2020-11-10 Applied Materials Inc SUBSTRATE STRUCTURING PROCEDURES
IT201900006736A1 (en) 2019-05-10 2020-11-10 Applied Materials Inc PACKAGE MANUFACTURING PROCEDURES
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
US20230070489A1 (en) * 2021-09-09 2023-03-09 Applied Materials, Inc. Doped tantalum-containing barrier films

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4366035A (en) * 1979-04-24 1982-12-28 Engelhard Corporation Electrodeposition of gold alloys
US4867882A (en) * 1987-11-09 1989-09-19 Aluminum Company Of America Method for reducing the amount of anionic metal ligand complex in a solution
CA1338346C (en) * 1989-08-23 1996-05-28 Chanakya Misra Method for reducing the amount of anionic metal-ligand complex in a solution
DE3839602A1 (en) * 1988-11-24 1990-05-31 Henkel Kgaa PASTOESES, PHOSPHATE-FREE DETERGENT WITH REDUCED FOAM PRIORITY
JPH0781199B2 (en) * 1989-11-30 1995-08-30 大同メタル工業株式会社 Method and apparatus for surface treatment of intermediate product of half type slide bearing
US5200048A (en) * 1989-11-30 1993-04-06 Daido Metal Company Ltd. Electroplating apparatus for plating half bearings
US5246565A (en) * 1992-05-07 1993-09-21 The United States Of America As Represented By The United States Department Of Energy High adherence copper plating process
US6426673B2 (en) * 1997-07-30 2002-07-30 Programmable Silicon Solutions High performance integrated radio frequency circuit devices
US7244677B2 (en) * 1998-02-04 2007-07-17 Semitool. Inc. Method for filling recessed micro-structures with metallization in the production of a microelectronic device
TWI223678B (en) * 1998-03-20 2004-11-11 Semitool Inc Process for applying a metal structure to a workpiece, the treated workpiece and a solution for electroplating copper
US6565729B2 (en) * 1998-03-20 2003-05-20 Semitool, Inc. Method for electrochemically depositing metal on a semiconductor workpiece
US6197181B1 (en) * 1998-03-20 2001-03-06 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece
US6517894B1 (en) * 1998-04-30 2003-02-11 Ebara Corporation Method for plating a first layer on a substrate and a second layer on the first layer
EP1112125B1 (en) * 1998-06-30 2006-01-25 Semitool, Inc. Metallization structures for microelectronic applications and process for forming the structures
US6309969B1 (en) * 1998-11-03 2001-10-30 The John Hopkins University Copper metallization structure and method of construction
US6544399B1 (en) * 1999-01-11 2003-04-08 Applied Materials, Inc. Electrodeposition chemistry for filling apertures with reflective metal
EP1111096A3 (en) * 1999-12-15 2004-02-11 Shipley Company LLC Seed layer repair method
US6350364B1 (en) * 2000-02-18 2002-02-26 Taiwan Semiconductor Manufacturing Company Method for improvement of planarity of electroplated copper
US6551483B1 (en) * 2000-02-29 2003-04-22 Novellus Systems, Inc. Method for potential controlled electroplating of fine patterns on semiconductor wafers
US6344125B1 (en) * 2000-04-06 2002-02-05 International Business Machines Corporation Pattern-sensitive electrolytic metal plating
US20050006245A1 (en) * 2003-07-08 2005-01-13 Applied Materials, Inc. Multiple-step electrodeposition process for direct copper plating on barrier metals
KR100800531B1 (en) * 2000-06-30 2008-02-04 가부시키가이샤 에바라 세이사꾸쇼 Copper-plating liquid, plating method and plating apparatus
US6824665B2 (en) * 2000-10-25 2004-11-30 Shipley Company, L.L.C. Seed layer deposition
US6432821B1 (en) * 2000-12-18 2002-08-13 Intel Corporation Method of copper electroplating
JP2004533123A (en) * 2001-06-14 2004-10-28 マトソン テクノロジー インコーポレーテッド Barrier enhancement process for copper connections
WO2003060959A2 (en) * 2002-01-10 2003-07-24 Semitool, Inc. Method for applying metal features onto barrier layers using electrochemical deposition
US7109111B2 (en) * 2002-02-11 2006-09-19 Applied Materials, Inc. Method of annealing metal layers
US20040069651A1 (en) * 2002-10-15 2004-04-15 Applied Materials, Inc. Oxide treatment and pressure control for electrodeposition
US20040154926A1 (en) * 2002-12-24 2004-08-12 Zhi-Wen Sun Multiple chemistry electrochemical plating method
US6913791B2 (en) * 2003-03-03 2005-07-05 Com Dev Ltd. Method of surface treating titanium-containing metals followed by plating in the same electrolyte bath and parts made in accordance therewith
KR20060079144A (en) * 2003-06-18 2006-07-05 어플라이드 머티어리얼스, 인코포레이티드 Atomic layer deposition of barrier materials
US20050072682A1 (en) * 2003-10-07 2005-04-07 Kenneth Lore Process and apparatus for coating components of a shopping cart and a product
US7341946B2 (en) * 2003-11-10 2008-03-11 Novellus Systems, Inc. Methods for the electrochemical deposition of copper onto a barrier layer of a work piece
US7300869B2 (en) * 2004-09-20 2007-11-27 Lsi Corporation Integrated barrier and seed layer for copper interconnect technology
US20060251872A1 (en) * 2005-05-05 2006-11-09 Wang Jenn Y Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof

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