JP2006265735A - Electroplating method of substrate having fine via hole - Google Patents

Electroplating method of substrate having fine via hole Download PDF

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JP2006265735A
JP2006265735A JP2006124226A JP2006124226A JP2006265735A JP 2006265735 A JP2006265735 A JP 2006265735A JP 2006124226 A JP2006124226 A JP 2006124226A JP 2006124226 A JP2006124226 A JP 2006124226A JP 2006265735 A JP2006265735 A JP 2006265735A
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plating
current
via hole
substrate
conductive film
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Hiroyuki Kadota
裕行 門田
Hitoshi Yonemura
均 米村
Masataka Hoshino
雅孝 星野
Manabu Tomisaka
学 富坂
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Fujitsu Ltd
Denso Corp
Sony Corp
Hitachi Kyowa Engineering Co Ltd
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Fujitsu Ltd
Denso Corp
Sony Corp
Hitachi Kyowa Engineering Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electroplating method capable of filling metal into fine via holes without defects and its equipment. <P>SOLUTION: In electroplating to a semiconductor or compound substrate having fine wiring and via holes, a slight current is passed between the substrate and the anode electrode in such a manner the potential of a conductive film is made baser than the natural potential in order to prevent the chemical dissolution of the conductive film before the plating is started. Also, in the pulse electroplating method of the substrate having the via holes, a pulse electrolytic current is superposed while the slight DC current is conducted in such a manner that the potential of the conductive film and the plating film is made baser than the natural potential during the downtime of the plating current. The pulse electrolytic conditions set the ratio of the opening diameter and depth of the via holes and the conducting current density and the ratio between the conduction/downtime by the thickness or electric resistance of the conductive film formed on the substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体及び化合物基板上に電解めっきを施す電解めっき方法に関する。   The present invention relates to an electrolytic plating method for performing electrolytic plating on semiconductor and compound substrates.

従来、半導体及び化合物基板上への電解めっき方法として、基板表面に付けられた金属導電膜に給電電極を接触させて通電し、電解めっきをする方法が知られている。一般的に電解めっきのための通電方法には、直流電流印加が用いられる。   2. Description of the Related Art Conventionally, as a method for electrolytic plating on semiconductor and compound substrates, a method is known in which a power supply electrode is brought into contact with a metal conductive film attached to the surface of the substrate and energized to perform electrolytic plating. In general, direct current application is used as an energization method for electrolytic plating.

従来の方法で電解めっきを行なうと、微細なViaホールの中への金属イオンの供給が間に合わず、めっき膜の成長が金属イオンの供給に律速されることになり、欠陥無く金属を充填することができなかった。このようにViaホールへ充填する金属に未めっき部位などの欠陥が発生すると、その欠陥の大きさにより製品不良が発生してしまう。   When electrolytic plating is performed by the conventional method, the supply of metal ions into the minute via hole is not in time, and the growth of the plating film is limited by the supply of metal ions, so that the metal is filled without defects. I could not. When defects such as unplated parts occur in the metal filling the Via hole in this way, a product defect occurs due to the size of the defect.

本発明の目的は、微細なViaホールに欠陥無く金属を充填することができる電解めっき方法を提供することにある。   An object of the present invention is to provide an electrolytic plating method capable of filling a fine via hole with a metal without a defect.

本発明は、微細なViaホールが存在する半導体及び化合物基板上へ電解めっきを施す方法において、通電および休止を繰り返すパルス通電を用いた電解めっき、及びパルス通電の休止時間にめっき被膜の溶解を抑制するための微弱な電流を印加しながら電解めっきを行なうことを特徴とするものである。   The present invention relates to a method for performing electroplating on a semiconductor substrate and a compound substrate in which fine via holes exist, and electrolytic plating using pulse energization that repeats energization and pause, and suppresses dissolution of the plating film during the pause time of pulse energization. Electrolytic plating is performed while applying a weak current for the purpose.

本発明は、微細なViaホールに欠陥無く金属を充填するための電解めっきにおいて、Viaホール径と深さ径の比、Viaホール内の導電膜厚さ等の電解めっきに関与する各種条件に応じて、電流密度０.１〜２００ｍA/ｃｍ2、通電および休止時間をｍｓeｃ単位で任意に設定し、通電／休止時間比を１％〜４０％〔（通電時間／通電時間＋休止時間）×１００〕の範囲で任意に設定し、休止時間に導電膜およびめっき膜の電位が自然電位よりも卑になるように微弱電流を通電することで、Viaホールへの電解めっきによる欠陥のない金属充填を成し得る。 In the electroplating for filling a fine via hole with a metal without defect, the present invention depends on various conditions related to the electroplating such as the ratio of the via hole diameter to the depth diameter, the conductive film thickness in the via hole. The current density is 0.1 to 200 mA / cm 2 , the energization and rest time are arbitrarily set in msec, and the energization / rest time ratio is 1% to 40% [(energization time / energization time + rest time) × 100 In the rest period, a weak current is applied so that the electric potential of the conductive film and the plating film is lower than the natural potential, thereby filling the via hole with a defect-free metal by electrolytic plating. Can be achieved.

本発明は具体的には次に挙げる方法および装置を提供する。   Specifically, the present invention provides the following methods and apparatuses.

本発明によれば、半導体の３次元実装に必要な高アスペクト比のＳｉ等の基板
の微細Viaホールに欠陥なく電気抵抗の小さい銅などの金属を埋め込むことがで
きる。 According to the present invention, it is possible to embed a metal such as copper having a low electric resistance without defects in a fine via hole of a substrate such as Si having a high aspect ratio necessary for three-dimensional mounting of a semiconductor.

以下、本発明にかかる実施例を図面に基づいて説明する。   Embodiments of the present invention will be described below with reference to the drawings.

めっき液として硫酸銅５水塩２００ｇ/ｌ、硫酸５０ｇ/ｌ、塩素イオン５０ppmの基本液に添加剤として促進剤２．５ml/ｌ、抑制剤１０ml/ｌの市販High acid type硫酸銅めっき液を用い、図１の縦型浸漬式めっき装置にて電解めっきを行った。被めっき基体としてViaホール径と深さの比が約７のViaホールが存在する８インチSiウェハで、その表面をCuでスパッタリングしたウェハ１を用い、ウェハ保持治具２に装着の後、めっき液の循環しているめっき槽５へ投入する。その際、めっき液による導電膜の化学的溶解を防止するため、めっき液中における導電膜の電位が自然電位より卑な電位になるように微弱な電流を微弱電流用電源８から出力し、微弱電流電源陽極線１０および微弱電流電源陰極線９を介して通電しながらウェハ保持治具２を投入する。その後ウェハ保持治具２をめっき槽５のなかで固定してからめっき電源４よりめっき電流の出力を陽極線７および陰極線
６を介して開始し、電解めっきを行った。めっき電源４は本発明の請求項９にある、Viaホール径と深さの比の変化に応じてめっき電流密度およびめっき電流の通電／休止時間比を連続的に変化させながらめっき可能な電源を用いた。３は陽極電極である。 A commercially available high acid type copper sulfate plating solution of copper sulfate pentahydrate 200 g / l, sulfuric acid 50 g / l, chloride ion 50 ppm as a plating solution and an accelerator 2.5 ml / l and an inhibitor 10 ml / l as a plating solution. The electrolytic plating was performed using the vertical immersion plating apparatus shown in FIG. An 8-inch Si wafer having a Via hole with a Via hole diameter / depth ratio of about 7 as the substrate to be plated is mounted on the wafer holding jig 2 using the wafer 1 whose surface is sputtered with Cu, and then plated. The solution is put into the plating tank 5 where the liquid is circulating. At that time, in order to prevent chemical dissolution of the conductive film by the plating solution, a weak current is output from the weak current power source 8 so that the potential of the conductive film in the plating solution is lower than the natural potential. The wafer holding jig 2 is put in while energizing through the current power supply anode line 10 and the weak current power supply cathode line 9. Thereafter, the wafer holding jig 2 was fixed in the plating tank 5, and then the output of the plating current from the plating power source 4 was started via the anode line 7 and the cathode line 6 to perform electrolytic plating. The plating power source 4 is a power source capable of plating while continuously changing the plating current density and the energization / rest time ratio of the plating current according to the change in the ratio of the Via hole diameter and the depth. Using. 3 is an anode electrode.

本発明によるパルス電解電流および微弱直流電流の重畳電解めっきによる微細なViaホールへのめっき金属の充填度合いを確認するために実験を行った。   An experiment was conducted to confirm the degree of filling of the plated metal into the fine Via hole by the superposition electrolytic plating of the pulse electrolytic current and the weak direct current according to the present invention.

めっき条件は液温を２５℃で固定とし、電流密度を１、５、１０、２０、４０、６０、１００、１５０ｍA/ｃｍ2と条件を変えて電解めっきを行なった。微弱直流電流は休止時間に導電膜およびめっき膜の電位が自然電位よりも卑になるような電流値を採用し、０．５ｍA/ｃｍ2で固定とした。まためっき電流の通電／休止時間比は３％、６％、１０％、３０％、６０％、１００％と条件を変えて電解めっきを行った。 The plating conditions were such that the liquid temperature was fixed at 25 ° C., and the current density was 1, 5, 10, 20, 40, 60, 100, and 150 mA / cm 2, and the electroplating was performed under different conditions. The weak direct current was fixed at 0.5 mA / cm 2 with a current value such that the electric potential of the conductive film and the plating film became lower than the natural potential during the downtime. Further, the electroplating was carried out by changing the conditions of the energization / rest time of the plating current to 3%, 6%, 10%, 30%, 60%, and 100%.

図２は微細なViaホール内でのめっき金属の充填度合いにより発生する不良の形態を図示したものである。Viaホール２１に電解めっきにより金属２２を充填する際に発生する不良の形状には、Aに示す開口部閉塞による不めっき部２３の発生、Bに示すViaホール中心部分に残るシーム状の不良２４の発生、Cに示すViaホール内でランダムな位置にあるボイド状の不良２５などが挙げられる。なお、開口部閉塞による不めっき部２３の発生はめっき金属の充填率が５０％以下の重大な不良、Viaホール中心部分に残るシーム状の不良２４の発生はめっき金属の充填率が５０〜９０％の不良、Viaホール内でランダムな位置にあるボイド状の不良２５の発生はめっき金属の充填率が９１〜９９％の軽微な欠陥を示す。   FIG. 2 illustrates the form of a defect that occurs depending on the degree of filling of the plated metal in the fine Via hole. The defective shape that occurs when the via hole 21 is filled with the metal 22 by electrolytic plating includes the occurrence of a non-plated portion 23 due to the closing of the opening shown in A, and the seam-like defect 24 remaining in the central portion of the Via hole shown in B. Generation of voids, void-like defects 25 at random positions in the Via hole shown in C, and the like. Note that the occurrence of the non-plated portion 23 due to the opening blockage is a serious defect with a plating metal filling rate of 50% or less, and the occurrence of a seam-like defect 24 remaining in the center of the Via hole is a plating metal filling rate of 50 to 90. % Of voids and the occurrence of void-like defects 25 at random positions in the Via hole indicate minor defects with a plating metal filling rate of 91 to 99%.

図３に示すグラフは、各めっき条件でViaホールの電解めっきによる金属の充填を行った際の充填度合いを、完全充填若しくは図２に示すめっき金属の充填率により表したグラフである。   The graph shown in FIG. 3 is a graph showing the filling degree when the metal is filled by electrolytic plating of the Via hole under each plating condition by the complete filling or the filling rate of the plating metal shown in FIG.

めっき電流の通電／休止時間比が４０％以上の条件では、電流密度にもよるがViaホール内部のめっき金属充填より先に開口部が閉塞してしまい不良が発生するケースが多く見られた。Viaホール内部への金属イオンの供給は、金属イオンの拡散に律速される。そのためめっき電流の通電／休止時間比が大きなめっき条件、すなわちめっき電流の休止時間が短いめっき条件では、Viaホール内部への金属イオンの析出量が、拡散による金属イオンの供給量に対して圧倒的に大きくなってしまう。よって開口部に近い部分でのめっき金属の析出のみ優先的に進んでしまい開口部が閉塞する不良が発生することを示している。   Under conditions where the plating current energization / pause time ratio was 40% or more, although depending on the current density, there were many cases where the opening was closed before filling the plating metal inside the Via hole, resulting in defects. The supply of metal ions into the via hole is limited by the diffusion of metal ions. Therefore, in plating conditions with a large plating current energization / rest time ratio, that is, plating conditions with a short rest time of plating current, the amount of metal ions deposited in the via hole is overwhelming with the amount of metal ions supplied by diffusion. Will become bigger. Therefore, only the deposition of the plated metal in the portion close to the opening proceeds preferentially, which indicates that a defect in which the opening is blocked occurs.

まためっき電流の通電／休止時間比が４０％以下でも電流密度が大きくなると、シームまたはボイド状不良の発生が多く見られた。パルス電流により電解めっきを行なうと、拡散層の形成が抑制されて濃度分極が抑えられる。そのためより大きな結晶化過電圧、すなわちより大きな電流密度の使用が可能となる。しかしここでめっき液中に添加する添加剤について、使用する添加剤により作用する電流密度が異なってくる。またViaホール径と深さの比やその作用により、Viaホールの充填度合いも異なることとなる。シームまたはボイド状不良の発生は、Viaホール径と深さの比やViaホール内の導電膜厚さ等の電解めっきに関与する各種条件に応じて、めっき電流の通電／休止時間比や電流密度を最適化する必要があることを示している。   Further, when the current density increased even when the energization / rest time ratio of the plating current was 40% or less, many seam or void defects were observed. When electrolytic plating is performed with a pulse current, formation of a diffusion layer is suppressed and concentration polarization is suppressed. Therefore, it is possible to use a larger crystallization overvoltage, that is, a larger current density. However, the current density acting on the additive added to the plating solution varies depending on the additive used. In addition, the filling degree of the Via hole varies depending on the ratio of the diameter and depth of the Via hole and its effect. The occurrence of seam or void defects depends on the plating current energization / pause time ratio and current density depending on various conditions related to electroplating, such as the ratio of the diameter and depth of the via hole and the conductive film thickness in the via hole. Indicates that it needs to be optimized.

例として本実験に供したViaホール開口径１０μｍで深さ７０μｍ、Viaホール径と深さの比が７のViaホールについて、電流密度６０ｍA/ｃｍ2、めっき電流の通電／休止時間が６０msec／９４０msecの通電／休止時間比６％のめっき条件では充填率が９５％程度と良好なめっき金属の充填が得られた。さらに電流密度４０ｍA/ｃｍ2、めっき電流の通電／休止時間が３０msec／９７０msecの通電／休止時間比３％のめっき条件ではめっき金属の完全充填が達成された。しかし同じ電流密度４０ｍA/ｃｍ2でもめっき電流の通電／休止時間が６００msec／４００msecの通電／休止時間比６０％のめっき条件では充填率５０％以下の開口部閉塞による不めっき部が発生した。まためっき電流の通電／休止時間が３０msec／９７０msecの通電／休止時間比３％、電流密度３００ｍA/ｃｍ2のめっき条件でも充填率５０％以下の開口部閉塞による不めっき部が発生した。 As an example, for a Via hole having a Via hole opening diameter of 10 μm, a depth of 70 μm, and a Via hole diameter to depth ratio of 7 used in this experiment, the current density is 60 mA / cm 2 and the energization / pause time of the plating current is 60 msec / 940 msec. Under the plating conditions with the energization / rest time ratio of 6%, the filling rate was about 95%, and satisfactory plating metal filling was obtained. Furthermore, complete filling of the plating metal was achieved under the plating conditions of a current density of 40 mA / cm 2 , a plating current energization / pause time of 30 msec / 970 msec and an energization / pause time ratio of 3%. However, even at the same current density of 40 mA / cm 2 , an unplated portion due to opening blockage with a filling rate of 50% or less was generated under the plating condition of energization / pause time ratio of 60% with an energization / pause time of plating current of 600 msec / 400 msec. In addition, an unplated portion due to an opening blockage with a filling rate of 50% or less was generated even under a plating condition of an energization / pause time ratio of 3% with a plating current energization / pause time of 30 msec / 970 msec and a current density of 300 mA / cm 2 .

本発明の実施例において使用した電解めっき装置の全体構成図。The whole block diagram of the electroplating apparatus used in the Example of this invention. Viaホール内でのめっき金属の充填度合いにより発生する不良の形態を示す図。The figure which shows the form of the defect which generate | occur | produces with the filling degree of the plating metal in a Via hole. 電解めっきによる金属の充填を行った際の充填度合いを示すグラフ。The graph which shows the filling degree at the time of performing metal filling by electroplating.

符号の説明Explanation of symbols

１…給電電極板（陰）、２…ウェハ保持治具、３…電極（陽）、４…パルス用電源、５…めっき槽、６…陰極線、７…陽極線、８…微弱電流用電源、９…微弱電流電源陰極線、１０…微弱電流電源陽極線、２１…Viaホール、２２…充填めっき金属、２３…開口部閉塞による不めっき部、２４…Viaホール中心部分に残るシーム状の不良、２５…Viaホール内でランダムな位置にあるボイド状の不良。 DESCRIPTION OF SYMBOLS 1 ... Feed electrode plate (negative), 2 ... Wafer holding jig, 3 ... Electrode (positive), 4 ... Power supply for pulses, 5 ... Plating tank, 6 ... Cathode line, 7 ... Anode line, 8 ... Power supply for weak current, DESCRIPTION OF SYMBOLS 9 ... Weak current power source cathode line, 10 ... Weak current power source anode line, 21 ... Via hole, 22 ... Filling plating metal, 23 ... Unplating part by obstruction | occlusion of opening part, 24 ... Seam-like defect which remains in Via hole center part, 25 ... Void-like defects at random positions in the Via hole.

Claims (3)

微細配線およびをViaホール有する半導体あるいは化合物基板への電解めっきにおいて、基板とアノード電極間にめっき電解電流をめっき開始するまでの間に導電膜の化学的溶解を防止するため、めっき液中における導電膜の電位が自然電位より卑な電位になるように、微弱電流を流すことを特徴とするViaホール充填電解めっき方法。   In electroplating to semiconductor or compound substrates with fine wiring and via holes, in order to prevent chemical dissolution of the conductive film before the start of plating electrolysis current between the substrate and the anode electrode, the conductive in the plating solution A Via hole filling electroplating method, wherein a weak current is applied so that the potential of the film is lower than the natural potential. 導電膜の溶解を防止する電流は、直流であることを特徴とする請求項１記載のViaホール充填電解めっき方法。   2. The via hole filling electroplating method according to claim 1, wherein the current for preventing dissolution of the conductive film is a direct current. Viaホールを有する基板のパルス電解めっき方法において、めっき電流の休止時間に導電膜およびめっき膜の電位が自然電位よりも卑になるように微弱直流電流を通電しながらパルス電解電流を重畳することを特徴とするViaホール充填電解めっき方法。
In the pulse electroplating method for a substrate having a via hole, the pulse electrolysis current is superimposed while applying a weak DC current so that the potential of the conductive film and the plating film is lower than the natural potential during the rest period of the plating current. Via hole filling electroplating method.
JP2006124226A 2006-04-27 2006-04-27 Electroplating method of substrate having fine via hole Pending JP2006265735A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101039961B1 (en) * 2008-12-09 2011-06-09 엘지이노텍 주식회사 core substrate and method for fabricating the same
US9376758B2 (en) 2010-12-21 2016-06-28 Ebara Corporation Electroplating method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101039961B1 (en) * 2008-12-09 2011-06-09 엘지이노텍 주식회사 core substrate and method for fabricating the same
US9376758B2 (en) 2010-12-21 2016-06-28 Ebara Corporation Electroplating method

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