JP4282190B2 - Multilayer printed wiring board and method for manufacturing multilayer printed wiring board - Google Patents

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board Download PDF

Info

Publication number
JP4282190B2
JP4282190B2 JP35386899A JP35386899A JP4282190B2 JP 4282190 B2 JP4282190 B2 JP 4282190B2 JP 35386899 A JP35386899 A JP 35386899A JP 35386899 A JP35386899 A JP 35386899A JP 4282190 B2 JP4282190 B2 JP 4282190B2
Authority
JP
Japan
Prior art keywords
hole
diameter
resin
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP35386899A
Other languages
Japanese (ja)
Other versions
JP2001168531A (en
Inventor
元雄 浅井
東冬 王
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP35386899A priority Critical patent/JP4282190B2/en
Priority to US09/979,388 priority patent/US6828510B1/en
Priority to PCT/JP2000/003377 priority patent/WO2000076281A1/en
Priority to EP09156837A priority patent/EP2086299A1/en
Priority to EP09156841A priority patent/EP2086300A1/en
Priority to DE60031680T priority patent/DE60031680T2/en
Priority to EP06123074A priority patent/EP1744609B1/en
Priority to EP00931571A priority patent/EP1194022B1/en
Priority to MYPI20002406A priority patent/MY125537A/en
Priority to TW089110559A priority patent/TW471244B/en
Publication of JP2001168531A publication Critical patent/JP2001168531A/en
Priority to US10/921,525 priority patent/US7985930B2/en
Priority to US12/171,794 priority patent/US8288664B2/en
Application granted granted Critical
Publication of JP4282190B2 publication Critical patent/JP4282190B2/en
Priority to US12/694,322 priority patent/US8283573B2/en
Priority to US12/887,197 priority patent/US20110024164A1/en
Priority to US12/913,258 priority patent/US8288665B2/en
Priority to US13/089,378 priority patent/US8822828B2/en
Priority to US13/169,674 priority patent/US8745863B2/en
Priority to US13/169,736 priority patent/US8782882B2/en
Priority to US13/432,471 priority patent/US8822830B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Description

【０００１】
【発明の属する技術分野】
この発明は、ＩＣチップを載置するパッケージ基板として好適に用い得る多層プリント配線板及び当該多層プリント配線板の製造方法に関するものである。
【０００２】
【従来の技術】
パッケージ基板に多層ビルドアップ配線板が広く使用されている。該多層ビルドアップ配線板は、信号線、電源線及び接地線となるスルーホールを設けたコア基板に、配線を備える層間樹脂絶縁層を１層ずつビルドアップしていくことで形成されている。高周波数のＩＣチップでは、パッケージ基板に引き回される電源線及び接地線の高周波数特性を高めインピーダンスを下げないと、電源線を介しての電力供給が追いつかなくなると共に、接地線を介してのアースレベルが変動して誤動作の原因となる。高周波数に対応するパッケージ基板では、多数の接地線及び電源線を配置することで、インダクタンス分を並列接続したと同様な効果を得て波数特性を改善している。
【０００３】
スルーホールは、コア基板にドリルで通孔を穿設することにより形成されている。しかし、ドリルでは、微細なスルーホールを狭ピッチで形成することができず、現在必要とされる数の電源線及び接地線を配設することが困難になりつつある。このため、コア基板にレーザを用いて通孔を穿設することが研究されている。
【０００４】
【発明が解決しようとする課題】
しかしながら、内部にガラスクロス等の心材の配設され、厚さ約１mmのコア基板にレーザでスルーホールを形成するためには、１孔毎にレーザを長時間照射する必要があり、数百の通孔を穿設するためには加工時間が長くなり、製造コストが嵩む。一方、小径のスルーホールは、ヒートサイクル等に於いて断線が生じることがあり、既存のドリルによる大径のスルーホールと比較して信頼性が低かった。
【０００５】
本発明は、上述した課題を解決するためになされたものであり、その目的は、接地線及び電源線の高周波特性を改善し、電力供給不足に起因するＩＣチップの誤動作を防止させ得る多層プリント配線板及び該多層プリント配線板の製造方法を提供することにある。
【０００８】
【課題を解決するための手段】
請求項１は、上下面を接続するスルーホールを形成した樹脂製のコア基板に層間樹脂絶縁層と導体回路とを交互に積層してなる多層プリント配線板において
前記コア基板の中央部に小径のスルーホールを配設し、外周部に大径のスルーホールを配設し、
前記小径のスルーホールに、信号線よりも多く電源線及び接地線を配設し、前記大径のスルーホールに、電源線及び接地線よりも多く信号線を配設したことを技術的特徴とする。
【００１０】
請求項１の発明では、コア基板の中央部に小径のスルーホールを配設し、外周部に大径のスルーホールを配設するため、中央部の配線密度を高めることができる。中央部の小径のスルーホールを電源線及び接地線とすることで、多数の電源線及び接地線を配設できるとともに、ＩＣチップから外部基板までの配線長を短縮できる。このため、ＩＣチップへの電源線及び接地線のインダクタンス分が低減し、ＩＣチップの誤動作を防止することが可能となる。なお、この場合における中央部とは、ＩＣチップの直下として置き換えることも可能である。
【００１３】
請求項３は、少なくとも以下の（Ａ）〜（Ｂ）の工程を備えることを特徴とする多層プリント配線板の製造方法にある：
（Ａ）樹脂製のコア基板の中央部にレーザを照射しスルーホールとなる小径の通孔を形成する工程と、
（Ｂ）前記コア基板の外周部にドリルにより大径のスルーホールとなる通孔を形成する工程を備え、
前記小径の通孔に小径のスルーホールを形成し、前記大径の通孔に大径のスルーホールを形成し、
前記小径のスルーホールに、信号線よりも多く電源線及び接地線を配設し、前記大径のスルーホールに、電源線及び接地線よりも多く信号線を配設する。
【００１５】
請求項３の発明では、コア基板の中央部に小径のスルーホールをレーザ又はドリルで形成し、外周部に大径のスルーホールをドリル又はレーザで形成するため、中央部の配線密度の自由度の高いコア基板を廉価に形成することができる。中央部の小径のスルーホールを電源線及び接地線とすることで、多数の電源線及び接地線を配設できるとともに、ＩＣチップから外部基板までの配線長を短縮できる。このため、ＩＣチップへの電源線及び接地線のインダクタンス分が低減し、ＩＣチップの誤動作を防止することが可能となる。更に、接続不良の発生する蓋然性の低い大径のスルーホールを主として信号線として用い、接続不良の発生する蓋然性の高い小径のスルーホールを主として電源線及び接地線として用いるため、当該電源線及び接地線側のスルーホールに断線が生じても、多層プリント配線板が正常動作を継続できる。
【００１６】
【発明の実施の形態】
以下、本発明の実施形態に係る多層プリント配線板及びその製造方法について図を参照して説明する。
先ず、本発明の第１実施形態に係る多層プリント配線板の構成について、パッケージ基板として用いられる多層プリント配線板１０の断面図を示す図７、及び、該多層プリント配線板にＩＣチップを搭載しドータボードへ取り付けた状態を示す図８を参照して説明する。
【００１７】
図８に示すように多層プリント配線板１０では、コア基板３０の中央側に小径（１００μｍ）のスルーホール３６Ａ、外周側に大径（３００μｍ）のスルーホール３６Ｂが形成され、該コア基板３０の両面には導体回路３４が形成されている。また、該コア基板３０の上には、バイアホール６０及び導体回路５８の形成された下層側層間樹脂絶縁層５０が配設されている。該下層層間樹脂絶縁層５０の上には、バイアホール１６０及び導体回路１５８が形成された上層層間樹脂絶縁層１５０が配置されている。上層層間樹脂絶縁層１５０の上には、ソルダーレジスト層７０が配設されている。
【００１８】
多層プリント配線板１０の上面には、ソルダーレジスト層７０の開口に、ＩＣチップへの接続用の半田バンプ７６Ｓ、７６Ｖ、７６Ｇが配設される。一方、パッケージ基板の底面には、ソルダーレジスト層７０の開口に、ドータボードへの接続用の半田バンプ７６Ｓ、７６Ｖ、７６Ｇが配設されている。
【００１９】
ＩＣチップ９０には、信号用パッド９２Ｓと、電源用パッド９２Ｖと、接地用パッド９２Ｇとが配設されている。信号用パッド９２Ｓは、信号用の半田バンプ７６Ｓを介して、層間樹脂絶縁層１５０のバイアホール１６０及び層間樹脂絶縁層５０のバイアホール６０を通りコア基板３０の外周側の大径スルーホール３６Ｂに接続される。そして、該大径スルーホール３６Ｂから、下面側のバイアホール６０、１６０を介して、信号用半田バンプ７６Ｓからドータボード９４側の信号用パッド９６Ｓへ接続される。
【００２０】
一方、ＩＣチップ９０の電源用パッド９２Ｖは、電源用の半田バンプ７６Ｖ、上面のバイアホール１６０、６０を介して、コア基板３０の中央側の小径スルーホール３６Ａに接続される。そして、該小径スルーホール３６Ａから、下面側のバイアホール６０、１６０を介して、電源用半田バンプ７６Ｖからドータボード９４側の電源用パッド９６Ｖへ接続される。同様に、ＩＣチップ９０の接地用パッド９２Ｇは、接地用の半田バンプ７６Ｇ、上面のバイアホール１６０、６０を介して、コア基板３０の中央側の小径スルーホール３６Ａに接続される。そして、該小径スルーホール３６Ａから、下面側のバイアホール６０、１６０を介して、接地用半田バンプ７６Ｇからドータボード９４側の接地用パッド９６Ｇへ接続される。
【００２１】
このＩＣチップとコア基板との配線の取り回しを図９（Ａ）に示し、コア基板３０の上面を図９（Ｂ）に示す。上述した図８は、図示の便宜上、スルーホール３６Ａ、３６Ｂの数を減らして示してあった点に注意されたい。
図９（Ｂ）に示すように、コア基板３０の中央部に小径スルーホール３６Ａが配設され、基板外周側に大径スルーホール３６Ｂが配設される。そして、図９（Ａ）に示すように、ＩＣチップ９０の電源パッド９２Ｖ及び接地パッド９２Ｇからの線が、コア基板３０の小径スルーホール３６Ａに主として配設される。そして、ＩＣチップ９０の信号用パッド９２Ｓからの線が、コア基板の大径スルーホール３６Ｂに主として配設される。後述するように小径スルーホール３６Ａは、レーザにより形成され、大径スルーホール３６Ｂは、ドリルにより形成することが望ましい。この代わりに、小径スルーホール３６Ａ及び大径スルーホール３６Ｂを共にレーザ、又は、ドリルで形成することもできる。
【００２２】
本実施形態では、コア基板３０の中央部に小径スルーホール３６Ａをレーザで形成し、外周部に大径のスルーホール３６Ｂをドリルで形成するため、中央部の配線密度の高いコア基板を廉価に形成することができる。中央部の小径スルーホール３６Ａを電源線及び接地線とすることで、多数の電源線及び接地線を配設できるとともに、ＩＣチップ９０からドータボード９４までの配線長を短縮できる。このため、ＩＣチップへの電源線及び接地線のインダクタンス分が低減し、電力を瞬時に供給し、アースレベルの変動を防ぎ、ＩＣチップの誤動作を防止することが可能となる。更に、接続不良の発生する蓋然性の低い大径スルーホール３６Ｂを主として信号線として用い、接続不良の発生する蓋然性の高い小径スルーホール３６Ａを主として電源線及び接地線として用いるため、当該電源線及び接地線側のスルーホールに断線が生じても、多層プリント配線板が正常動作を継続できる。
【００２３】
以下、図７及び図８に示す多層プリント配線板１０の製造方法について図を参照して説明する。
ここでは先ず、コア基板３０及び層間樹脂絶縁層５０に通孔を穿設する炭酸ガスレーザの概略構成について、図１０を参照して説明する。
実施態様に係るレーザ装置としては、三菱電機製のＭＬ５０５ＧＴを用いる。また、ＣＯ2レーザ発信器１８０としては、三菱電機製のＭＬ５００３Ｄ２を用いる。
【００２４】
レーザ発振器１８０から出た光は、基板上の焦点を鮮明にするための転写用マスク１８２を経由してガルバノヘッド１７０へ入射する。ガルバノヘッド１７０は、レーザ光をＸ方向にスキャンするガルバノミラー１７４ＸとＹ方向にスキャンするガルバノミラー１７４Ｙとの２枚で１組のガルバノミラーから構成されており、このミラー１７４Ｘ、１７４Ｙは制御用のモータ１７２Ｘ、１７２Ｙにより駆動される。モータ１７２Ｘ、１７２Ｙは図示しない制御装置からの制御指令に応じて、ミラー１７４Ｘ、１７４Ｙの角度を調整すると共に、内蔵しているエンコーダからの検出信号を該コンピュータ側へ送出するよう構成されている。
【００２５】
レーザ光は、ガルバノミラー１７４Ｘ、１７４Ｙを経由してそれぞれＸ−Ｙ方向にスキャンされてｆ−θレンズ１７６を通り、コア基板３０にスルーホール用通孔３３Ｂを形成する。コア基板３０は、Ｘ−Ｙ方向に移動するＸ−Ｙテーブル１９０に載置されている。
【００２６】
引き続き、本発明の第１実施形態に係る多層プリント配線板の製造工程について図１乃至図６を参照して説明する。この第１実施形態では、多層プリント配線板をセミアディティブ方により形成する。
【００２７】
(1)図１（Ａ）に示すように厚さ０．８mmのガラスエポキシ樹脂またはＢＴ（ビスマレイミドトリアジン）樹脂からなる基板３０の両面に１８μｍの銅箔３２がラミネートされている銅張積層板３０Ａを出発材料とした。まず、この銅張積層板３０ＡをＮａＯＨ（１０ｇ／ｌ）、ＮａＣｌＯ2 （４０ｇ／ｌ）、Ｎａ3 ＰＯ4 （６ｇ／ｌ）を含む水溶液を黒化浴（酸化浴）とする黒化処理、および、ＮａＯＨ（１０ｇ／ｌ）、ＮａＢＨ4 （６ｇ／ｌ）を含む水溶液を還元浴とする還元処理を行い、銅箔３２の全表面に粗化面３２βを形成する（図１（Ｂ）参照）。ここでは、黒化還元処理で粗化面を形成したが、後述するエッチング、又は、無電解めっきにより粗化面を設けることもできる。
【００２８】
(2)次に、基板３０を図１０を参照して上述した炭酸レーザ装置のＸ−Ｙテーブル１９０に載置し、波長１０．４μｍのＣＯ2 ガスレーザにて、ビーム径５ｍｍ、トップハットモード、パルス幅５０μ秒、１０ショットの条件で、直径１００μｍの通孔３３Ａを３００μｍピッチで基板３０の中央に穿設する（図１（Ｃ）及び図９（Ｂ）参照）。
【００２９】
(3)そして、ドリル９８にてコア基板３０の外周部に直径３００μｍの通孔３３Ｂを６００μｍピッチで穿設する（図１（Ｄ）及び図９（Ｂ）参照）。
【００３０】
その後、無電解めっき液に浸漬して、通孔３３Ａ、３３Ｂの側壁に銅めっき膜を析出することでスルーホール３６Ａ、３６Ｂを形成してから（図２（Ａ））、常法に従いパターン状にエッチングにより基板の両面に内層銅パターン（下層導体回路）３４を形成する（図２（Ｂ））。
【００３１】
(4)下層導体回路３４を形成した基板を水洗いし、乾燥した後、エッチング液を基板の両面にスプレイで吹きつけて、下層導体回路３４の表面とスルーホール３６Ａ、３６Ｂのランド３６ａ表面と内壁とをエッチングすることにより、下層導体回路３４の全表面に粗化面３４βと、スルーホール３６Ａ、３６Ｂのランド３６ａ及び内壁に粗化面３６βを形成した（図２（Ｃ）参照）。黒化、還元処理で粗化面を形成することができる。この場合には、ＮａＯＨ（１０ｇ／ｌ）、ＮａＣｌＯ2 （４０ｇ／ｌ）、Ｎａ3 ＰＯ4 （６ｇ／ｌ）を含む水溶液を黒化浴（酸化浴）とする黒化処理、および、ＮａＯＨ（１０ｇ／ｌ）、ＮａＢＨ4 （６ｇ／ｌ）を含む水溶液を還元浴とする還元処理を行う。
【００３２】
なお、第二銅錯体と有機酸塩、過酸化水素と硫酸からなるエッチング液に浸漬、あるいはスプレーすることで粗化面を形成することもできる。また、無電解めっきにより粗化面を形成することもできる。無電解めっきにより粗化面を形成する場合には、導体回路３４を形成した基板３０にアルカリ脱脂してソフトエッチングして、次いで、塩化パラジウウムと有機酸からなる触媒溶液で処理して、Ｐｄ触媒を付与し、この触媒を活性化した後、硫酸銅３．２×１０−２ｍｏｌ／ｌ、硫酸ニッケル３．９×１０−３ｍｏｌ／ｌ、錯化剤５．４×１０−２ｍｏｌ／ｌ、次亜りん酸ナトリウム３．３×１０−１ｍｏｌ／ｌ、ホウ酸５．０×１０−１ｍｏｌ／ｌ、界面活性剤（日信化学工業製、サーフィール４６５）０．１ｇ／ｌ、ＰＨ＝９からなる無電解めっき液に浸積し、浸漬１分後に、４秒当たり１回に割合で縦、および、横振動させて、導体回路３４及びスルーホール３６のランド３６ａ表面にＣｕ−Ｎｉ−Ｐからなる針状合金の被覆層と粗化層を設ける。
【００３３】
(5)シクロオレフィン系樹脂あるいはエポキシ系樹脂を主成分とする樹脂充填材４０を、基板の両面に印刷機を用いて塗布することにより、下層導体回路３４間またはスルーホール３６Ａ、３６Ｂ内に充填し、加熱乾燥を行った。即ち、この工程により、樹脂充填材４０が下層導体回路３４の間あるいはスルーホール３６Ａ、３６Ｂ内に充填される（図２（Ｄ）参照）。
【００３４】
(6)上記(5)の処理を終えた基板の片面を、ベルト研磨紙（三共理化学社製）を用いたベルトサンダー研磨により、下層導体回路３４の表面やスルーホール３６Ａ、３６Ｂのランド３６ａ表面に樹脂充填材４０が残らないように研磨し、ついで、上記ベルトサンダー研磨による傷を取り除くためのバフ研磨を行った。このような一連の研磨を基板の他方の面についても同様に行った。そして、充填した樹脂充填材４０を加熱硬化させた（図３（Ａ）参照）。
【００３５】
このようにして、スルーホール３６等に充填された樹脂充填材４０の表層部および下層導体回路３４上面の粗化層３４βを除去して基板両面を平滑化し、樹脂充填材４０と下層導体回路３４の側面とが粗化面３４βを介して強固に密着し、またスルーホール３６の内壁面と樹脂充填材４０とが粗化面３６βを介して強固に密着した配線基板を得る。
【００３６】
(7)次に、上記(6)の処理を終えた基板の両面に、上記(４) で用いたエッチング液と同じエッチング液をスプレイで吹きつけ、一旦平坦化された下層導体回路３４の表面とスルーホール３６のランド３６ａ表面とをエッチングすることにより、下層導体回路３４の全表面に粗化面３４βを、スルーホールのランド３６ａ表面に粗化層３６βを形成した（図３（Ｂ）参照）。なお、この工程ではエッチングにより粗化面を形成しているが、この代わりに、無電解めっきにより粗化層を形成することもできる。
【００３７】
(8)次に、上記工程を経た基板の両面に、厚さ５０μｍの熱硬化型シクロオレフィン系樹脂シートを温度５０〜１５０℃まで昇温しながら圧力５ｋｇ／ｃｍ2 で真空圧着ラミネートし、シクロオレフィン系樹脂からなる層間樹脂絶縁層５０を設ける（図３（Ｃ）参照）。なお、真空圧着時の真空度は、１０ｍｍＨｇに調整する。
【００３８】
(9) 次に、波長１０．４μｍのＣＯ2 ガスレーザにて、ビーム径５ｍｍ、トップハットモード、パルス幅１５μ秒、マスクの穴径０．５ｍｍ、５ショットの条件でシクロオレフィン系樹脂からなる層間樹脂絶縁層５０に直径８０μｍのバイアホール用開口４８を設けた（図３（Ｄ）参照）。この後、酸素プラズマを用いてデスミア処理を行った。
【００３９】
(10) 次に、日本真空技術株式会社製のＳＶ−４５４０を用いてプラズマ処理を行い、層間樹脂絶縁層５０の表面を粗化した（図４（Ａ）参照）。この際、不活性ガスとしてはアルゴンガスを使用し、電力２００Ｗ、ガス圧０．６Ｐａ、温度７０℃の条件で、２分間プラズマ処理を実施した。
【００４０】
(11) 次に、同じ装置を用い、内部のアルゴンガスを交換した後、Ｎｉスパッタ後、Ｃｕスパッタを、気圧０．６Ｐａ、温度８０℃、電力２００Ｗ、時間５分間の条件で行い、Ｎｉ−Ｃｕ合金層５２をポリオレフィン系層間樹脂絶縁層５０の表面に形成した。このとき、形成されたＮｉ／Ｃｕ金属層５２の厚さは、Ｃｉ層（０．０５μｍ）とＣｕ層（０．１５μｍ）との０．２μｍであった（図４（Ｂ）参照）。
【００４１】
(12)上記処理を終えた基板の両面に、市販の感光性ドライフィルムを貼り付け、フォトマスクフィルムを載置して、１００ｍＪ／ｃｍ2 で露光した後、０．８％炭酸ナトリウムで現像処理し、厚さ１５μｍのめっきレジスト５４のパターンを形成した（図４（Ｃ）参照）。
【００４２】
(13)次に、以下の条件で電気めっきを施して、厚さ１５μｍの電気めっき膜５６を形成した（図５（Ａ）参照）。なお、この電気めっき膜５６により、後述する工程で導体回路５８となる部分の厚付けおよびバイアホール６０となる部分のめっき充填等が行われたことになる。なお、電気めっき水溶液中の添加剤は、アトテックジャパン社製のカパラシドＨＬである。
【００４３】
〔電気めっき水溶液〕
硫酸 ２．２４ ｍｏｌ／ｌ
硫酸銅 ０．２６ ｍｏｌ／ｌ
添加剤 １９．５ ｍｌ／ｌ
〔電気めっき条件〕
電流密度 １ Ａ／ｄｍ2
時間 ６５ 分
温度 ２２±２ ℃
【００４４】
(14)ついで、めっきレジスト５４を５％ＮａＯＨで剥離除去した後、そのめっきレジスト５４の下に存在していたＮｉ−Ｃｕ合金層５２を硝酸および硫酸と過酸化水素との混合液を用いるエッチングにて溶解除去し、電気銅めっき膜５６等からなる厚さ１６μｍの導体回路５８（バイアホール６０を含む）を形成した（図５（Ｂ）参照）。
【００４５】
(15)続いて、上記(5) 〜(13)の工程を繰り返すことにより、さらに上層の層間樹脂絶縁層１５０、導体回路１５８及びバイアホール１６０を形成した（図５（Ｃ）参照）。
【００４６】
(16)次に、ジエチレングリコールジメチルエーテル（ＤＭＤＧ）に６０重量％の濃度になるように溶解させた、クレゾールノボラック型エポキシ樹脂（日本化薬社製）のエポキシ基５０％をアクリル化した感光性付与のオリゴマー（分子量：４０００）４６．６７重量部、メチルエチルケトンに溶解させた８０重量％のビスフェノールＡ型エポキシ樹脂（油化シェル社製、商品名：エピコート１００１）１５重量部、イミダゾール硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）１．６重量部、感光性モノマーである多官能アクリルモノマー（日本化薬社製、商品名：Ｒ６０４）３重量部、同じく多価アクリルモノマー（共栄化学社製、商品名：ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ社製、商品名：Ｓ−６５）０．７１重量部を容器にとり、攪拌、混合して混合組成物を調製し、この混合組成物に対して光重合開始剤としてベンゾフェノン（関東化学社製）２．０重量部、光増感剤としてのミヒラーケトン（関東化学社製）０．２重量部を加えて、粘度を２５℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物（有機樹脂絶縁材料）を得た。
なお、粘度測定は、Ｂ型粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｒｐｍの場合はローターＮｏ．４、６ｒｐｍの場合はローターＮｏ．３によった。
【００４７】
(17)次に、多層配線基板の両面に、上記ソルダーレジスト組成物を２０μｍの厚さで塗布し、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、ソルダーレジスト開口部のパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト層に密着させて１０００ｍＪ／ｃｍ2 の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、２００μｍの直径の開口７１を形成した。
そして、さらに、８０℃で１時間、１００℃で１時間、１２０℃で１時間、１５０℃で３時間の条件でそれぞれ加熱処理を行ってソルダーレジスト層を硬化させ、はんだパッド部分が開口した、その厚さが２０μｍのソルダーレジスト層（有機樹脂絶縁層）７０を形成した（図６（Ａ））。ソルダーレジストを半硬化した樹脂フィルムを張り付け、露光・現像あるいはレーザで半田パッドを開口させてもよい。
【００４８】
(18)次に、ソルダーレジスト層（有機樹脂絶縁層）７０を形成した基板を、塩化ニッケル（２．３×１０-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（２．８×１０-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．６×１０-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無電解ニッケルめっき液に２０分間浸漬して、開口７１に厚さ５μｍのニッケルめっき層７２を形成した（図６（Ｂ））。さらに、その基板をシアン化金カリウム（７．６×１０-3ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．２×１０-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（１．７×１０-1ｍｏｌ／ｌ）を含む無電解めっき液に８０℃の条件で７．５分間浸漬して、ニッケルめっき層７２上に、厚さ０．０３μｍの金めっき層７４を形成した。
【００４９】
(19)この後、ソルダーレジスト層７０の開口にはんだペーストを印刷して、２００℃でリフローすることにより半田バンプ（はんだ体）７６Ｓ、７６Ｖ、７６Ｇを形成し、多層プリント配線板１０を完成する（図７参照）。
(20)最後に、多層プリント配線板１０の半田バンプ７６Ｓ、７６Ｖ、７６Ｇにパッド９２Ｓ、９２Ｖ、９２Ｇ対応するようＩＣチップ９０を載置し、リフローを行うことでＩＣチップ９０を取り付ける。そして、当該パッケージ基板１０をドータボード９４に載置し、リフローを行うことで当該ドータボードへ載置する（図８）。
【００５０】
引き続き、本発明の第２実施形態に係る多層プリント配線板及びその製造方法について説明する。
図１７は、パッケージ基板に適用した第２実施形態に係る多層プリント配線板の断面を示している。この第２実施形態の多層プリント配線板１１０は、図７を参照して上述した第１実施形態と同様である。但し、第１実施形態では、多層プリント配線板の下面に半田バンプ７６Ｓ、７６Ｖ、７６Ｇが配設されたが、この第２実施形態では、導電性接続ピン７８が配設されている。
【００５１】
引き続き、第２実施形態の多層プリント配線板の製造方法について説明する。ここではまず、Ａ．層間樹脂絶縁層用樹脂フィルムの作製、及び、Ｂ．樹脂充填材の調製について説明する。
Ａ．層間樹脂絶縁層用樹脂フィルムの作製
ビスフェノールＡ型エポキシ樹脂（エポキシ当量４６９、油化シェルエポキシ社製エピコート１００１）３０重量部、クレゾールノボラック型エポキシ樹脂（エポキシ当量２１５、大日本インキ化学工業社製 エピクロンＮ−６７３）４０重量部、トリアジン構造含有フェノールノボラック樹脂（フェノール性水酸基当量１２０、大日本インキ化学工業社製 フェノライトＫＡ−７０５２）３０重量部をエチルジグリコールアセテート２０重量部、ソルベントナフサ２０重量部に攪拌しながら加熱溶解させ、そこへ末端エポキシ化ポリブタジエンゴム（ナガセ化成工業社製 デナレックスＲ−４５ＥＰＴ）１５重量部と２−フェニル−４、５−ビス（ヒドロキシメチル）イミダゾール粉砕品１．５重量部、微粉砕シリカ２重量部、シリコン系消泡剤０．５重量部を添加しエポキシ樹脂組成物を調製した。
得られたエポキシ樹脂組成物を厚さ３８μｍのＰＥＴフィルム上に乾燥後の厚さが５０μｍとなるようにロールコーターを用いて塗布した後、８０〜１２０℃で１０分間乾燥させることにより、層間樹脂絶縁層用樹脂フィルムを作製した。
【００５２】
Ｂ．樹脂充填材の調製
ビスフェノールＦ型エポキシモノマー（油化シェル社製、分子量：３１０、ＹＬ９８３Ｕ）１００重量部、表面にシランカップリング剤がコーティングされた平均粒径が１．６μｍで、最大粒子の直径が１５μｍ以下のＳｉＯ2 球状粒子（アドテック社製、ＣＲＳ １１０１−ＣＥ）１７０重量部およびレベリング剤（サンノプコ社製 ペレノールＳ４）１．５重量部を容器にとり、攪拌混合することにより、その粘度が２３±１℃で４５〜４９Ｐａ・ｓの樹脂充填材を調製した。
なお、硬化剤として、イミダゾール硬化剤（四国化成社製、２Ｅ４ＭＺ−ＣＮ）６．５重量部を用いた。
【００５３】
多層プリント配線板の製造方法
(1) 厚さ０．８ｍｍのガラスエポキシ樹脂またはＢＴ（ビスマレイミドトリアジン）樹脂からなる基板３０の両面に１８μｍの銅箔３２がラミネートされている銅張積層板３０Ａを出発材料とした（図１１（Ａ）参照）。まず、この銅張積層板３０ＡをＮａＯＨ（１０ｇ／ｌ）、ＮａＣｌＯ2 （４０ｇ／ｌ）、Ｎａ3 ＰＯ4 （６ｇ／ｌ）を含む水溶液を黒化浴（酸化浴）とする黒化処理、および、ＮａＯＨ（１０ｇ／ｌ）、ＮａＢＨ4 （６ｇ／ｌ）を含む水溶液を還元浴とする還元処理を行い、銅箔３２の全表面に粗化面３２βを形成した（図１１（Ｂ）参照）。
【００５４】
(2)次に、基板３０を図１０を参照して上述した炭酸レーザ装置のテーブルに載置し、炭酸ガスレーザを照射することで、直径１００μｍの通孔３３Ａを３００μｍピッチで基板３０の中央に穿設する（図１１（Ｃ）及び図９（Ｂ）参照）。
【００５５】
(3)そして、ドリル９８にてコア基板３０の外周部に直径３００μｍの通孔３３Ｂを６００μｍピッチで穿設する（図１１（Ｄ）及び図９（Ｂ）参照）。
その後、無電解めっき液に浸漬して、通孔３３Ａ、３３Ｂの側壁に銅めっき膜を析出することでスルーホール３６Ａ、３６Ｂを形成してから（図１２（Ａ））、常法に従いパターン状にエッチングにより基板の両面に内層銅パターン（下層導体回路）３４を形成した（図１２（Ｂ））。
【００５６】
(4)下層導体回路３４を形成した基板を水洗いし、乾燥した後、エッチング液を基板の両面にスプレイで吹きつけて、下層導体回路３４の表面とスルーホール３６Ａ、３６Ｂのランド３６ａ表面と内壁とをエッチングすることにより、下層導体回路３４の全表面に粗化面３４βを、スルーホール３６Ａ、３６Ｂのランド３６ａ表面及び内壁に粗化層３６βを形成した（図１２（Ｃ）参照）。エッチング液として、イミダゾール銅（II）錯体１０重量部、グリコール酸７重量部、塩化カリウム５重量部およびイオン交換水７８重量部を混合したものを使用した。
【００５７】
(5)上記Ｂにて記載した樹脂充填材を整調した後、下記の方法により調整後２４時間以内に、スルーホール３６Ａ、３６Ｂ、及び、基板３０の片面の導体回路非形成部と導体回路３４の外縁部とに樹脂充填材４０の層を形成した（図１２（Ｄ）参照）。
すなわち、まず、スキージを用いてスルーホール３６Ａ、３６Ｂ内に樹脂充填材４０を押し込んだ後、１００℃、２０分の条件で乾燥させた。次に、導体回路非形成部に相当する部分が開口したマスクを基板上に載置し、スキージを用いて凹部となっている導体回路非形成部に樹脂充填材４０の層を形成し、１００℃、２０分の条件で乾燥させた。
【００５８】
(6) 上記(5) の処理を終えた基板の片面を、＃６００のベルト研磨紙（三共理化学製）を用いたベルトサンダー研磨により、内層銅パターン４の表面やスルーホール３６Ａ、３６Ｂのランド３６ａ表面に樹脂充填材４０が残らないように研磨し、次いで、上記ベルトサンダー研磨による傷を取り除くためのバフ研磨を行った。このような一連の研磨を基板の他方の面についても同様に行った。
次いで、１００℃で１時間、１５０℃で１時間の加熱処理を行って樹脂充填材４０を硬化した。
【００５９】
このようにして、スルーホール３６Ａ、３６Ｂや導体回路非形成部に形成された樹脂充填材４０の表層部および下層導体回路３４の表面を平坦化し、樹脂充填材４０と下層導体回路３４の側面とが粗化面３４βを介して強固に密着し、またスルーホール３６Ａ、３６Ｂの内壁面と樹脂充填材４０とが粗化面３６βを介して強固に密着した絶縁性基板を得た（図１３（Ａ）参照）。すなわち、この工程により、樹脂充填材４０の表面と下層導体回路３４の表面とが同一平面となる。
【００６０】
(7) 上記基板を水洗、酸性脱脂した後、ソフトエッチングし、次いで、エッチング液を基板の両面にスプレイで吹きつけて、下層導体回路３４の表面とスルーホール３６Ａ、３６Ｂのランド３６ａ表面と内壁とをエッチングすることにより、下層導体回路３４の全表面に粗化面３４βを、スルーホールのランド３６ａ表面に粗化層３６βを形成した（図１３（Ｂ）参照）。
エッチング液としては、イミダゾール銅（ＩＩ）錯体１０重量部、グリコール酸７重量部、塩化カリウム５重量部からなるエッチング液（メック社製、メックエッチボンド）を使用した。
【００６１】
(8) 基板の両面に、上記Ａで作製した基板より少し大きめの層間樹脂絶縁層用樹脂フィルムを基板上に載置し、圧力４ｋｇｆ／ｃｍ2 、温度８０℃、圧着時間１０秒の条件で仮圧着して裁断した後、さらに、以下の方法により真空ラミネーター装置を用いて貼り付けることにより層間樹脂絶縁層５０を形成した（図１３（Ｃ）参照）。すなわち、層間樹脂絶縁層用樹脂フィルムを基板上に、真空度０．５Ｔｏｒｒ、圧力４ｋｇｆ／ｃｍ2 、温度８０℃、圧着時間６０秒の条件で本圧着し、その後、１７０℃で３０分間熱硬化させた。
【００６２】
(9) 層間樹脂絶縁層５０上に、厚さ１．２ｍｍの貫通孔４９ａが形成されたマスク４９を載置する。そして、波長１０．４μｍのＣＯ2 ガスレーザにて、ビーム径４．０ｍｍ、トップハットモード、パルス幅５．０μ秒、マスクの貫通孔の径１．０ｍｍ、１ショットの条件で、層間樹脂絶縁層５０に直径８０μｍのバイアホール用開口４８を形成した（図１３（Ｄ）参照）。
【００６３】
(10) バイアホール用開口４８を形成した基板３０を、６０ｇ／ｌの過マンガン酸を含む８０℃の溶液に１０分間浸漬し、層間樹脂絶縁層５０の表面に存在するエポキシ樹脂粒子を溶解除去することにより、バイアホール用開口４８の内壁を含む層間樹脂絶縁層５０の表面を粗面とした（図１４（Ａ）参照）。
【００６４】
(11) 次に、上記処理を終えた基板を、中和溶液（シプレイ社製）に浸漬してから水洗いした。さらに、粗面化処理（粗化深さ３μｍ）した該基板の表面に、パラジウム触媒を付与することにより、層間樹脂絶縁層５０の表面およびバイアホール用開口４８の内壁面に触媒核を付着させた。
【００６５】
(12)次に、以下の組成の無電解銅めっき水溶液中に基板を浸漬して、粗面全体に厚さ０．６〜３．０μｍの無電解銅めっき膜５１を形成した（図１４（Ｂ）参照）。
〔無電解めっき水溶液〕
ＮｉＳＯ4 ０．００３ ｍｏｌ／ｌ
酒石酸 ０．２００ ｍｏｌ／ｌ
硫酸銅 ０．０３０ ｍｏｌ／ｌ
ＨＣＨＯ ０．０５０ ｍｏｌ／ｌ
ＮａＯＨ ０．１００ ｍｏｌ／ｌ
α、α′−ビピリジル ４０ ｍｇ／ｌ
ポリエチレングリコール（ＰＥＧ） ０．１０ ｇ／ｌ
〔無電解めっき条件〕
３５℃の液温度で４０分
【００６６】
(13)市販の感光性ドライフィルムを無電解銅めっき膜５１に貼り付け、マスクを載置して、１００ｍＪ／ｃｍ2 で露光し、０．８％炭酸ナトリウム水溶液で現像処理することにより、厚さ３０μｍのめっきレジスト５４を設けた（図１４（Ｃ）参照）。
【００６７】
(14)ついで、基板を５０℃の水で洗浄して脱脂し、２５℃の水で水洗後、さらに硫酸で洗浄してから、以下の条件で電解銅めっきを施し、厚さ２０μｍの電解銅めっき膜５６を形成した（図１５（Ａ）参照）。
〔電解めっき水溶液〕
硫酸 ２．２４ ｍｏｌ／ｌ
硫酸銅 ０．２６ ｍｏｌ／ｌ
添加剤 １９．５ ｍｌ／ｌ
（アトテックジャパン社製、カパラシドＨＬ）
〔電解めっき条件〕
電流密度 １ Ａ／ｄｍ2
時間 ６５ 分
温度 ２２±２ ℃
【００６８】
(15)めっきレジスト５４を５％ＮａＯＨで剥離除去した後、そのめっきレジスト５４下の無電解めっき膜５１を硫酸と過酸化水素の混合液でエッチング処理して溶解除去し、無電解銅めっき膜５１と電解銅めっき膜５６からなる厚さ１８μｍの導体回路（バイアホール６０を含む）５８を形成した（図１５（Ｂ）参照）。
【００６９】
(16)(7) と同様の処理を行い、第二銅錯体と有機酸とを含有するエッチング液によって、粗化面６２を形成した（図１５（Ｃ）参照）。
【００７０】
(17)上記 (8)〜(16)の工程を繰り返すことにより、さらに上層の層間樹脂絶縁層１６０、導体回路１５８及びバイアホール１６０を形成し、多層配線板を得た（図１６（Ａ）参照）。
【００７１】
(18)次に、多層配線基板の両面に、第１実施形態と同様のソルダーレジスト組成物を２０μｍの厚さで塗布し、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、ソルダーレジスト開口部のパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト層に密着させて１０００ｍＪ／ｃｍ2 の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、２００μｍの直径の開口７１を形成した。
そしてさらに、８０℃で１時間、１００℃で１時間、１２０℃で１時間、１５０℃で３時間の条件でそれぞれ加熱処理を行ってソルダーレジスト層を硬化させ、開口を有し、その厚さが２０μｍのソルダーレジストパターン層７０を形成した（図１６（Ｂ））。上記ソルダーレジスト組成物としては、市販のソルダーレジスト組成物やソルダーレジストの樹脂フィルムを使用することもできる。
【００７２】
(19)次に、ソルダーレジスト層７０を形成した基板を、塩化ニッケル（２．３×１０-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（２．８×１０-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．６×１０-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無電解ニッケルめっき液に２０分間浸漬して、開口７１に厚さ５μｍのニッケルめっき層７２を形成した。さらに、その基板をシアン化金カリウム（７．６×１０-3ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．２×１０-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（１．７×１０-1ｍｏｌ／ｌ）を含む無電解金めっき液に８０℃の条件で７．５分間浸漬して、ニッケルめっき層７２上に、厚さ０．０３μｍの金めっき層７４を形成した（図１６（Ｃ））。
【００７３】
(20)この後、基板のＩＣチップを載置する面のソルダーレジスト層７０の開口に、スズ−鉛を含有するはんだペーストを印刷し、さらに他方の面のソルダーレジスト層７０の開口にスズ−アンチモンを含有するはんだペーストを印刷した後、２００℃でリフローすることにより上面にはんだバンプ７６Ｓ、７６Ｖ、７６Ｇを設けた。そして、下面に導電性接続ピン７８を配設し、プリント基板１１０を製造した（図１７参照）。
【００７４】
引き続き、本発明の第３実施形態について説明する。上述した第１、第２実施形態では、銅貼り積層板に貫通孔３３Ａ、３３Ｂを穿設した。これに対して、第３実施形態では、銅貼り積層板に樹脂層を形成した後、貫通孔３３Ａ、３４Ｂを形成する。
【００７５】
この第３実施形態のコア基板の形成方法について、図１８を参照して説明する。
(1) 厚さ０．８ｍｍのガラスエポキシ樹脂、ＢＴ、ＦＲ−４，ＦＲ−５樹脂からなる基板３０の両面に１８μｍの銅箔３２がラミネートされている銅張積層板３０Ａを出発材料とした（図１８（Ａ）参照）。常法に従いパターン状にエッチングして基板の両面に内層銅パターン（下層導体回路）３１を形成した（図１８（Ｂ））。
【００７６】
(2)次に、基板３０の両面に後述するＡＢＦ樹脂絶縁フィルムを張り付け、樹脂層３５を形成する（図１８（Ｃ））。
(3)基板３０を第１実施形態と同様な炭酸レーザ装置のテーブルに載置し、炭酸ガスレーザを照射することで、直径１００μｍの通孔３３Ａを３００μｍピッチで基板３０の中央に穿設する（図１８（Ｄ）参照）。
【００７７】
(3)そして、ドリル９８にてコア基板３０の外周部に直径３００μｍの通孔３３Ｂを６００μｍピッチで穿設する（図１８（Ｅ）参照）。
(4)その後、無電解めっき液に浸漬して、通孔３３Ａ、３３Ｂの側壁に銅めっき膜を析出することでスルーホール３６Ａ、３６Ｂを形成してから、エッチングを行い導体回路３４を形成する（図１８（Ｆ）参照）。以降の工程は上述した第１、第２実施形態と同様であるため、図示及び説明を省略する。
【００７８】
なお、上記ＡＢＦ樹脂フィルムとしては、難溶性樹脂、可溶性粒子、硬化剤、その他の成分が含有されている。それぞれについて以下に説明する。
【００７９】
本発明の製造方法において使用する樹脂フィルムは、酸または酸化剤に可溶性の粒子（以下、可溶性粒子という）が酸または酸化剤に難溶性の樹脂（以下、難溶性樹脂という）中に分散したものである。
なお、本発明で使用する「難溶性」「可溶性」という語は、同一の酸または酸化剤からなる溶液に同一時間浸漬した場合に、相対的に溶解速度の早いものを便宜上「可溶性」と呼び、相対的に溶解速度の遅いものを便宜上「難溶性」と呼ぶ。
【００８０】
上記可溶性粒子としては、例えば、酸または酸化剤に可溶性の樹脂粒子（以下、可溶性樹脂粒子）、酸または酸化剤に可溶性の無機粒子（以下、可溶性無機粒子）、酸または酸化剤に可溶性の金属粒子（以下、可溶性金属粒子）等が挙げられる。これらの可溶性粒子は、単独で用いても良いし、２種以上併用してもよい。
【００８１】
上記可溶性粒子の形状は特に限定されず、球状、破砕状等が挙げられる。また、上記可溶性粒子の形状は、一様な形状であることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができるからである。
【００８２】
上記可溶性粒子の平均粒径としては、０．１〜１０μｍが望ましい。この粒径の範囲であれば、２種類以上の異なる粒径のものを含有してもよい。すなわち、平均粒径が０．１〜０．５μｍの可溶性粒子と平均粒径が１〜３μｍの可溶性粒子とを含有する等である。これにより、より複雑な粗化面を形成することができ、導体回路との密着性にも優れる。なお、本発明において、可溶性粒子の粒径とは、可溶性粒子の一番長い部分の長さである。
【００８３】
上記可溶性樹脂粒子としては、熱硬化性樹脂、熱可塑性樹脂等からなるものが挙げられ、酸あるいは酸化剤からなる溶液に浸漬した場合に、上記難溶性樹脂よりも溶解速度が速いものであれば特に限定されない。
上記可溶性樹脂粒子の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等からなるものが挙げられ、これらの樹脂の一種からなるものであってもよいし、２種以上の樹脂の混合物からなるものであってもよい。
【００８４】
また、上記可溶性樹脂粒子としては、ゴムからなる樹脂粒子を用いることもできる。上記ゴムとしては、例えば、ポリブタジエンゴム、エポキシ変性、ウレタン変性、（メタ）アクリロニトリル変性等の各種変性ポリブタジエンゴム、カルボキシル基を含有した（メタ）アクリロニトリル・ブタジエンゴム等が挙げられる。これらのゴムを使用することにより、可溶性樹脂粒子が酸あるいは酸化剤に溶解しやすくなる。つまり、酸を用いて可溶性樹脂粒子を溶解する際には、強酸以外の酸でも溶解することができ、酸化剤を用いて可溶性樹脂粒子を溶解する際には、比較的酸化力の弱い過マンガン酸塩でも溶解することができる。また、クロム酸を用いた場合でも、低濃度で溶解することができる。そのため、酸や酸化剤が樹脂表面に残留することがなく、後述するように、粗化面形成後、塩化パラジウム等の触媒を付与する際に、触媒が付与されなたかったり、触媒が酸化されたりすることがない。
【００８５】
上記可溶性無機粒子としては、例えば、アルミニウム化合物、カルシウム化合物、カリウム化合物、マグネシウム化合物およびケイ素化合物からなる群より選択される少なくとも一種からなる粒子等が挙げられる。
【００８６】
上記アルミニウム化合物としては、例えば、アルミナ、水酸化アルミニウム等が挙げられ、上記カルシウム化合物としては、例えば、炭酸カルシウム、水酸化カルシウム等が挙げられ、上記カリウム化合物としては、炭酸カリウム等が挙げられ、上記マグネシウム化合物としては、マグネシア、ドロマイト、塩基性炭酸マグネシウム等が挙げられ、上記ケイ素化合物としては、シリカ、ゼオライト等が挙げられる。これらは単独で用いても良いし、２種以上併用してもよい。
【００８７】
上記可溶性金属粒子としては、例えば、銅、ニッケル、鉄、亜鉛、鉛、金、銀、アルミニウム、マグネシウム、カルシウムおよびケイ素からなる群より選択される少なくとも一種からなる粒子等が挙げられる。また、これらの可溶性金属粒子は、絶縁性を確保するために、表層が樹脂等により被覆されていてもよい。
【００８８】
上記可溶性粒子を、２種以上混合して用いる場合、混合する２種の可溶性粒子の組み合わせとしては、樹脂粒子と無機粒子との組み合わせが望ましい。両者とも導電性が低くいため樹脂フィルムの絶縁性を確保することができるとともに、難溶性樹脂との間で熱膨張の調整が図りやすく、樹脂フィルムからなる層間樹脂絶縁層にクラックが発生せず、層間樹脂絶縁層と導体回路との間で剥離が発生しないからである。
【００８９】
上記難溶性樹脂としては、層間樹脂絶縁層に酸または酸化剤を用いて粗化面を形成する際に、粗化面の形状を保持できるものであれば特に限定されず、例えば、熱硬化性樹脂、熱可塑性樹脂、これらの複合体等が挙げられる。また、これらの樹脂に感光性を付与した感光性樹脂であってもよい。感光性樹脂を用いることにより、層間樹脂絶縁層に露光、現像処理を用いてバイアホール用開口を形成することできる。
これらのなかでは、熱硬化性樹脂を含有しているものが望ましい。それにより、めっき液あるいは種々の加熱処理によっても粗化面の形状を保持することができるからである。
【００９０】
上記難溶性樹脂の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等が挙げられる。これらの樹脂は単独で用いてもよいし、２種以上を併用してもよい。さらには、１分子中に、２個以上のエポキシ基を有するエポキシ樹脂がより望ましい。前述の粗化面を形成することができるばかりでなく、耐熱性等にも優れてるため、ヒートサイクル条件下においても、金属層に応力の集中が発生せず、金属層の剥離などが起きにくいからである。
【００９１】
上記エポキシ樹脂としては、例えば、クレゾールノボラック型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、アルキルフェノールノボラック型エポキシ樹脂、ビフェノールＦ型エポキシ樹脂、ナフタレン型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、フェノール類とフェノール性水酸基を有する芳香族アルデヒドとの縮合物のエポキシ化物、トリグリシジルイソシアヌレート、脂環式エポキシ樹脂等が挙げられる。これらは、単独で用いてもよく、２種以上を併用してもよい。それにより、耐熱性等に優れるものとなる。
【００９２】
本発明で用いる樹脂フィルムにおいて、上記可溶性粒子は、上記難溶性樹脂中にほぼ均一に分散されていることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができ、樹脂フィルムにバイアホールやスルーホールを形成しても、その上に形成する導体回路の金属層の密着性を確保することができるからである。また、粗化面を形成する表層部だけに可溶性粒子を含有する樹脂フィルムを用いてもよい。それによって、樹脂フィルムの表層部以外は酸または酸化剤にさらされることがないため、層間樹脂絶縁層を介した導体回路間の絶縁性が確実に保たれる。
【００９３】
上記樹脂フィルムにおいて、難溶性樹脂中に分散している可溶性粒子の配合量は、樹脂フィルムに対して、３〜４０重量％が望ましい。可溶性粒子の配合量が３重量％未満では、所望の凹凸を有する粗化面を形成することができない場合があり、４０重量％を超えると、酸または酸化剤を用いて可溶性粒子を溶解した際に、樹脂フィルムの深部まで溶解してしまい、樹脂フィルムからなる層間樹脂絶縁層を介した導体回路間の絶縁性を維持できず、短絡の原因となる場合がある。
【００９４】
上記樹脂フィルムは、上記可溶性粒子、上記難溶性樹脂以外に、硬化剤、その他の成分等を含有していることが望ましい。
上記硬化剤としては、例えば、イミダゾール系硬化剤、アミン系硬化剤、グアニジン系硬化剤、これらの硬化剤のエポキシアダクトやこれらの硬化剤をマイクロカプセル化したもの、トリフェニルホスフィン、テトラフェニルホスフォニウム・テトラフェニルボレート等の有機ホスフィン系化合物等が挙げられる。
【００９５】
上記硬化剤の含有量は、樹脂フィルムに対して０．０５〜１０重量％であることが望ましい。０．０５重量％未満では、樹脂フィルムの硬化が不十分であるため、酸や酸化剤が樹脂フィルムに侵入する度合いが大きくなり、樹脂フィルムの絶縁性が損なわれることがある。一方、１０重量％を超えると、過剰な硬化剤成分が樹脂の組成を変性させることがあり、信頼性の低下を招いたりしてしまうことがある。
【００９６】
上記その他の成分としては、例えば、粗化面の形成に影響しない無機化合物あるいは樹脂等のフィラーが挙げられる。上記無機化合物としては、例えば、シリカ、アルミナ、ドロマイト等が挙げられ、上記樹脂としては、例えば、ポリイミド樹脂、ポリアクリル樹脂、ポリアミドイミド樹脂、ポリフェニレン樹脂、メラニン樹脂、オレフィン系樹脂等が挙げられる。これらのフィラーを含有させることによって、熱膨脹係数の整合や耐熱性、耐薬品性の向上などを図りプリント配線板の性能を向上させることができる。
【００９７】
また、上記樹脂フィルムは、溶剤を含有していてもよい。上記溶剤としては、例えば、アセトン、メチルエチルケトン、シクロヘキサノン等のケトン類、酢酸エチル、酢酸ブチル、セロソルブアセテートやトルエン、キシレン等の芳香族炭化水素等が挙げられる。これらは単独で用いてもよいし、２種類以上併用してもよい。
【００９８】
なお、上述した実施形態では、中央部に小径のスルーホールを配設し、外周部に大径スルーホールを配設したが、本発明は、これに限定されず、配線密度を高める必要がある箇所に小径のスルーホールを適宜配設することができる。
【００９９】
[比較例１]
コア基板のスルーホールをレーザにより全て径１００μｍで形成した以外には第１実施形態と同様である。
[比較例２]
コア基板のスルーホールをドリルにより全て径３００μｍで形成した以外には第１実施形態と同様である。
[比較例３]
コア基板のスルーホールをレーザにより全て径１００μｍで形成した以外には第２実施形態と同様である。
[比較例４]
コア基板のスルーホールをドリルにより全て径３００μｍで形成した以外には第２実施形態と同様である。
【０１００】
１ＧＨｚの高周波数ＩＣチップをそれぞれ第１、第２、第３実施形態の多層プリント配線板、及び、比較例１，２、３、４の多層プリント配線板に実装し、比較試験を行った。
その結果、比較例２、４では、ＩＣチップのエラーが頻繁に発生した。これは、電源線及びアース線の数が少ないため、電源の供給が追いつかなくなっていることによるものと推測される。
これに対して、第１、第２、第３実施形態の多層プリント配線板、比較例１、３は安定した動作を提供できた。但し、比較例１、３の多層プリント配線板は、全てのスルーホールをレーザで形成するため、第１〜第３実施形態の多層プリント配線板に対して、製造コストが非常に高くなっているし、スルーホールの断線する確率が高くなる。
【図面の簡単な説明】
【図１】図１（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係る多層プリント配線板の製造工程図である。
【図２】図２（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係る多層プリント配線板の製造工程図である。
【図３】図３（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係る多層プリント配線板の製造工程図である。
【図４】図４（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１実施形態に係る多層プリント配線板の製造工程図である。
【図５】図５（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１実施形態に係る多層プリント配線板の製造工程図である。
【図６】図６（Ａ）、（Ｂ）は、本発明の第１実施形態に係る多層プリント配線板の製造工程図である。
【図７】本発明の第１実施形態に係る多層プリント配線板の断面図である。
【図８】本発明の第１実施形態に係る多層プリント配線板の断面図である。
【図９】図９（Ａ）は、コア基板内の配線取り回しを示す説明図であり、図９（Ｂ）は、コア基板の平面図である。
【図１０】開口を形成する炭酸ガスレーザ装置の説明図である。
【図１１】図１１（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係る多層プリント配線板の製造工程図である。
【図１２】図１２（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係る多層プリント配線板の製造工程図である。
【図１３】図１３（Ａ）、（Ｂ）、（Ｃ）は、本発明の第２実施形態に係る多層プリント配線板の製造工程図である。
【図１４】図１４（Ａ）、（Ｂ）、（Ｃ）は、本発明の第２実施形態に係る多層プリント配線板の製造工程図である。
【図１５】図１５（Ａ）、（Ｂ）、（Ｃ）は、本発明の第２実施形態に係る多層プリント配線板の製造工程図である。
【図１６】図１６（Ａ）、（Ｂ）、（Ｃ）は、本発明の第２実施形態に係る多層プリント配線板の製造工程図である。
【図１７】本発明の第２実施形態に係る多層プリント配線板の断面図である。
【図１８】本発明の第３実施形態に係る多層プリント配線板のコア基板の断面図である。
【符号の説明】
３０ コア基板
３３Ａ、３３Ｂ 通孔
３４ 導体回路
３６Ａ 小径バイアホール
３６Ｂ 大径スルーホール
４０ 樹脂充填材
５０ 層間樹脂絶縁層
５８ 導体回路
６０ バイアホール
７０ ソルダーレジスト層
７６Ｓ、７６Ｖ、７６Ｇ 半田バンプ
１５０ 層間樹脂絶縁層
１５８ 導体回路
１６０ バイアホール[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer printed wiring board that can be suitably used as a package substrate on which an IC chip is placed, and a method for manufacturing the multilayer printed wiring board.
[0002]
[Prior art]
Multilayer build-up wiring boards are widely used for package substrates. The multilayer build-up wiring board is formed by building up an interlayer resin insulating layer including wiring one by one on a core substrate provided with through holes serving as signal lines, power supply lines, and ground lines. In a high-frequency IC chip, unless the impedance of the power line and ground line routed around the package board is increased and the impedance is lowered, power supply through the power line cannot be caught up and The ground level may fluctuate and cause malfunction. In a package substrate corresponding to a high frequency, by arranging a large number of ground lines and power supply lines, the same effect as when the inductance components are connected in parallel is obtained, and the wave number characteristics are improved.
[0003]
The through hole is formed by drilling a through hole in the core substrate with a drill. However, in a drill, it is difficult to form fine through holes at a narrow pitch, and it is becoming difficult to arrange the number of power lines and ground lines that are required at present. For this reason, research has been conducted on drilling through holes in the core substrate using a laser.
[0004]
[Problems to be solved by the invention]
However, in order to form a through-hole with a laser on a core substrate having a thickness of about 1 mm with a core material such as a glass cloth inside, it is necessary to irradiate the laser for each hole for a long time. In order to make the through-hole, the processing time becomes long and the manufacturing cost increases. On the other hand, the small-diameter through hole may be disconnected in a heat cycle or the like, and the reliability is low as compared with the large-diameter through hole formed by an existing drill.
[0005]
The present invention has been made to solve the above-described problems, and an object of the present invention is to improve the high-frequency characteristics of the ground line and the power supply line and to prevent malfunction of the IC chip due to insufficient power supply. It is providing the manufacturing method of a wiring board and this multilayer printed wiring board.
[0008]
[Means for Solving the Problems]
Claim 1Formed through holes to connect the upper and lower surfacesResinIn multilayer printed wiring boards in which interlayer resin insulation layers and conductor circuits are alternately laminated on the core substrate
  A small-diameter through hole is provided at the center of the core substrate, and a large-diameter through hole is provided at the outer periphery.,
More power lines and ground lines are arranged in the small-diameter through holes than signal lines, and more signal lines are arranged in the large-diameter through holes than power lines and ground lines.This is a technical feature.
[0010]
  Claim1In this invention, since the small-diameter through hole is disposed in the central portion of the core substrate and the large-diameter through hole is disposed in the outer peripheral portion, the wiring density in the central portion can be increased. By using the small-diameter through hole in the center as a power line and a ground line, a large number of power lines and ground lines can be provided, and the wiring length from the IC chip to the external substrate can be shortened. For this reason, the inductance of the power supply line and the ground line to the IC chip is reduced, and malfunction of the IC chip can be prevented. Note that the central portion in this case can be replaced directly below the IC chip.
[0013]
  Claim3Is a method for producing a multilayer printed wiring board comprising at least the following steps (A) to (B):
(A)ResinLaser irradiation at the center of the core substrateShiForming a small-diameter through hole to be a through hole;
(B) Outer peripheral portion of the core substrateInThe process of forming a through-hole that becomes a large-diameter through hole with a drillPreparation,
  Forming a small diameter through hole in the small diameter through hole, forming a large diameter through hole in the large diameter through hole;
More power lines and ground lines are arranged in the small-diameter through holes than signal lines, and more signal lines are arranged in the large-diameter through holes than power lines and ground lines.
[0015]
  Claim3In the present invention, a small-diameter through hole is formed in the center portion of the core substrate with a laser or a drill, and a large-diameter through hole is formed in the outer peripheral portion with a drill or a laser. The substrate can be formed at a low cost. By using the small-diameter through hole in the center as a power line and a ground line, a large number of power lines and ground lines can be provided, and the wiring length from the IC chip to the external substrate can be shortened. For this reason, the inductance of the power supply line and the ground line to the IC chip is reduced, and malfunction of the IC chip can be prevented. Furthermore, since large-diameter through holes with low probability of poor connection are mainly used as signal lines, and small-diameter through holes with high probability of poor connection are mainly used as power lines and ground lines, the power line and ground Even if a break occurs in the through hole on the line side, the multilayer printed wiring board can continue normal operation.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a multilayer printed wiring board and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
First, regarding the configuration of the multilayer printed wiring board according to the first embodiment of the present invention, FIG. 7 showing a sectional view of the multilayer printed wiring board 10 used as a package substrate, and an IC chip mounted on the multilayer printed wiring board. A description will be given with reference to FIG. 8 showing a state of being attached to the daughter board.
[0017]
As shown in FIG. 8, in the multilayer printed wiring board 10, a small-diameter (100 μm) through-hole 36 </ b> A is formed on the center side of the core substrate 30, and a large-diameter (300 μm) through-hole 36 </ b> B is formed on the outer peripheral side. Conductor circuits 34 are formed on both sides. On the core substrate 30, a lower-layer interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are formed is disposed. On the lower interlayer resin insulation layer 50, an upper interlayer resin insulation layer 150 in which via holes 160 and conductor circuits 158 are formed is disposed. A solder resist layer 70 is disposed on the upper interlayer resin insulation layer 150.
[0018]
On the upper surface of the multilayer printed wiring board 10, solder bumps 76S, 76V, and 76G for connection to the IC chip are disposed in the opening of the solder resist layer 70. On the other hand, solder bumps 76S, 76V, and 76G for connection to the daughter board are disposed in the opening of the solder resist layer 70 on the bottom surface of the package substrate.
[0019]
The IC chip 90 is provided with a signal pad 92S, a power supply pad 92V, and a grounding pad 92G. The signal pad 92S passes through the via hole 160 of the interlayer resin insulating layer 150 and the via hole 60 of the interlayer resin insulating layer 50 via the signal solder bumps 76S and into the large-diameter through hole 36B on the outer peripheral side of the core substrate 30. Connected. The large-diameter through hole 36B is connected to the signal pad 96S on the daughter board 94 side from the signal solder bump 76S via the via holes 60 and 160 on the lower surface side.
[0020]
On the other hand, the power supply pad 92 </ b> V of the IC chip 90 is connected to the small-diameter through hole 36 </ b> A on the center side of the core substrate 30 via the power supply solder bump 76 </ b> V and the via holes 160 and 60 on the upper surface. The small diameter through hole 36A is connected to the power supply pad 96V on the daughter board 94 side from the power supply solder bump 76V through the via holes 60 and 160 on the lower surface side. Similarly, the grounding pad 92G of the IC chip 90 is connected to the small-diameter through hole 36A on the center side of the core substrate 30 through the grounding solder bump 76G and the via holes 160 and 60 on the upper surface. The small diameter through hole 36A is connected to the grounding pad 96G on the daughter board 94 side from the grounding solder bump 76G through the via holes 60 and 160 on the lower surface side.
[0021]
The wiring arrangement between the IC chip and the core substrate is shown in FIG. 9A, and the upper surface of the core substrate 30 is shown in FIG. 9B. It should be noted that FIG. 8 described above is illustrated with a reduced number of through holes 36A and 36B for convenience of illustration.
As shown in FIG. 9B, a small-diameter through hole 36A is disposed at the center of the core substrate 30, and a large-diameter through hole 36B is disposed on the outer peripheral side of the substrate. 9A, lines from the power supply pad 92V and the ground pad 92G of the IC chip 90 are mainly disposed in the small-diameter through hole 36A of the core substrate 30. The line from the signal pad 92S of the IC chip 90 is mainly disposed in the large-diameter through hole 36B of the core substrate. As will be described later, it is desirable that the small diameter through hole 36A is formed by a laser, and the large diameter through hole 36B is formed by a drill. Alternatively, both the small diameter through hole 36A and the large diameter through hole 36B can be formed by a laser or a drill.
[0022]
In the present embodiment, the small diameter through hole 36A is formed in the center portion of the core substrate 30 with a laser, and the large diameter through hole 36B is formed in the outer peripheral portion with a drill. Can be formed. By using the small-diameter through hole 36A in the center as a power supply line and a ground line, a large number of power supply lines and ground lines can be provided, and the wiring length from the IC chip 90 to the daughter board 94 can be shortened. For this reason, the inductance of the power supply line and the ground line to the IC chip is reduced, power is instantaneously supplied, fluctuation of the ground level can be prevented, and malfunction of the IC chip can be prevented. Further, since the large-diameter through hole 36B having a low probability of connection failure is mainly used as a signal line, and the small-diameter through hole 36A having a high probability of connection failure is mainly used as a power line and a ground line, the power line and ground Even if a break occurs in the through hole on the line side, the multilayer printed wiring board can continue normal operation.
[0023]
Hereinafter, the manufacturing method of the multilayer printed wiring board 10 shown in FIG.7 and FIG.8 is demonstrated with reference to figures.
Here, first, a schematic configuration of a carbon dioxide laser in which through holes are formed in the core substrate 30 and the interlayer resin insulating layer 50 will be described with reference to FIG.
As the laser device according to the embodiment, ML505GT manufactured by Mitsubishi Electric is used. As the CO2 laser transmitter 180, ML5003D2 manufactured by Mitsubishi Electric is used.
[0024]
The light emitted from the laser oscillator 180 enters the galvano head 170 via a transfer mask 182 for making the focal point on the substrate clear. The galvano head 170 is composed of a pair of galvano mirrors, a galvano mirror 174X that scans laser light in the X direction and a galvano mirror 174Y that scans in the Y direction. It is driven by motors 172X and 172Y. The motors 172X and 172Y are configured to adjust the angles of the mirrors 174X and 174Y according to a control command from a control device (not shown) and to send a detection signal from a built-in encoder to the computer side.
[0025]
The laser light is scanned in the XY directions via the galvanometer mirrors 174X and 174Y, passes through the f-θ lens 176, and forms the through hole 33B for the through hole in the core substrate 30. The core substrate 30 is placed on an XY table 190 that moves in the XY direction.
[0026]
Subsequently, the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the multilayer printed wiring board is formed by a semi-additive method.
[0027]
(1) A copper clad laminate in which 18 μm copper foil 32 is laminated on both surfaces of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm as shown in FIG. 30A was the starting material. First, this copper clad laminate 30A is made of NaOH (10 g / l), NaClO.2 (40 g / l), NaThree POFour Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBHFour A reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath is performed to form a roughened surface 32β on the entire surface of the copper foil 32 (see FIG. 1B). Here, the roughened surface is formed by the blackening reduction treatment, but the roughened surface can also be provided by etching described later or electroless plating.
[0028]
(2) Next, the substrate 30 is placed on the XY table 190 of the carbonic acid laser device described above with reference to FIG.2 A gas laser is used to drill through holes 33A having a diameter of 100 μm in the center of the substrate 30 at a pitch of 300 μm under the conditions of a beam diameter of 5 mm, a top hat mode, a pulse width of 50 μsec, and 10 shots (FIGS. 1C and 9). (See (B)).
[0029]
(3) Then, through holes 33B having a diameter of 300 μm are formed at a pitch of 600 μm in the outer peripheral portion of the core substrate 30 with a drill 98 (see FIGS. 1D and 9B).
[0030]
Thereafter, the through-holes 36A and 36B are formed by immersing in an electroless plating solution and depositing a copper plating film on the side walls of the through holes 33A and 33B (FIG. 2A), and then in a pattern according to a conventional method. Then, an inner layer copper pattern (lower conductor circuit) 34 is formed on both sides of the substrate by etching (FIG. 2B).
[0031]
(4) The substrate on which the lower conductor circuit 34 is formed is washed with water and dried, and then an etching solution is sprayed on both sides of the substrate to spray the surface of the lower conductor circuit 34 and the surfaces of the lands 36a and inner walls of the through holes 36A and 36B. The roughened surface 34β was formed on the entire surface of the lower conductor circuit 34, and the roughened surface 36β was formed on the lands 36a and inner walls of the through holes 36A and 36B (see FIG. 2C). A roughened surface can be formed by blackening or reduction treatment. In this case, NaOH (10 g / l), NaClO2 (40 g / l), NaThree POFour Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBHFour Reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath is performed.
[0032]
The roughened surface can also be formed by dipping or spraying in an etching solution comprising cupric complex and organic acid salt, hydrogen peroxide and sulfuric acid. Further, the roughened surface can be formed by electroless plating. In the case of forming a roughened surface by electroless plating, the substrate 30 on which the conductor circuit 34 is formed is subjected to alkali degreasing and soft etching, and then treated with a catalyst solution composed of paradium chloride and an organic acid to obtain a Pd catalyst. After activating this catalyst, copper sulfate 3.2 × 10-2mol / l, nickel sulfate 3.9 × 10-3mol / l, complexing agent 5.4 × 10-2mol / l, sodium hypophosphite 3.3 × 10-1mol / l, boric acid 5.0 × 10-1It is immersed in an electroless plating solution consisting of mol / l, a surfactant (manufactured by Nissin Chemical Industry, Surfir 465) 0.1 g / l, PH = 9, and once every 4 seconds after immersion Then, a needle-like alloy coating layer and a roughening layer made of Cu-Ni-P are provided on the surfaces of the lands 36a of the conductor circuit 34 and the through hole 36 by longitudinal and lateral vibration.
[0033]
(5) A resin filler 40 mainly composed of cycloolefin resin or epoxy resin is applied to both sides of the substrate using a printing machine, thereby filling the space between the lower conductor circuits 34 or the through holes 36A and 36B. And dried by heating. That is, by this step, the resin filler 40 is filled between the lower conductor circuits 34 or into the through holes 36A and 36B (see FIG. 2D).
[0034]
(6) The surface of the lower conductor circuit 34 and the surface of the land 36a of the through holes 36A and 36B are polished on one side of the substrate after the processing of (5) above by belt sander polishing using belt polishing paper (manufactured by Sankyo Rikagaku). Then, the resin filler 40 was polished so as not to remain, and then buffed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. Then, the filled resin filler 40 was cured by heating (see FIG. 3A).
[0035]
In this way, the surface layer portion of the resin filler 40 filled in the through holes 36 and the like and the roughened layer 34β on the upper surface of the lower conductor circuit 34 are removed to smooth both surfaces of the substrate, and the resin filler 40 and the lower conductor circuit 34 are smoothed. A wiring substrate is obtained in which the side surface of the through hole 36 is firmly adhered via the roughened surface 34β, and the inner wall surface of the through hole 36 and the resin filler 40 are firmly adhered via the roughened surface 36β.
[0036]
(7) Next, the same etching solution as that used in (4) above is sprayed on both surfaces of the substrate after the processing in (6) above, and the surface of the lower conductor circuit 34 once flattened is sprayed. And the surface of the land 36a of the through hole 36 are etched to form the roughened surface 34β on the entire surface of the lower conductor circuit 34 and the roughened layer 36β on the surface of the land 36a of the through hole (see FIG. 3B). ). In this step, the roughened surface is formed by etching, but a roughened layer can also be formed by electroless plating instead.
[0037]
(8) Next, a pressure of 5 kg / cm is applied to both sides of the substrate that has undergone the above-described process while the temperature of a 50 μm-thick thermosetting cycloolefin resin sheet is raised to a temperature of 50 to 150 ° C.2 And an interlayer resin insulation layer 50 made of cycloolefin resin is provided (see FIG. 3C). Note that the degree of vacuum during vacuum bonding is adjusted to 10 mmHg.
[0038]
(9) Next, CO with a wavelength of 10.4 μm2 A via hole opening 48 having a diameter of 80 μm is formed in the interlayer resin insulating layer 50 made of cycloolefin resin under the conditions of a gas laser with a beam diameter of 5 mm, a top hat mode, a pulse width of 15 μs, a mask hole diameter of 0.5 mm, and a 5-shot. (See FIG. 3D). Thereafter, desmear treatment was performed using oxygen plasma.
[0039]
(10) Next, plasma processing was performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. to roughen the surface of the interlayer resin insulation layer 50 (see FIG. 4A). At this time, argon gas was used as an inert gas, and plasma treatment was performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C.
[0040]
(11) Next, using the same apparatus, after replacing the argon gas inside, after Ni sputtering, Cu sputtering was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, time 5 minutes, Ni— A Cu alloy layer 52 was formed on the surface of the polyolefin-based interlayer resin insulation layer 50. At this time, the thickness of the formed Ni / Cu metal layer 52 was 0.2 μm between the Ci layer (0.05 μm) and the Cu layer (0.15 μm) (see FIG. 4B).
[0041]
(12) A commercially available photosensitive dry film is pasted on both surfaces of the substrate after the above treatment, and a photomask film is placed thereon, and 100 mJ / cm.2 Then, it was developed with 0.8% sodium carbonate to form a pattern of plating resist 54 having a thickness of 15 μm (see FIG. 4C).
[0042]
(13) Next, electroplating was performed under the following conditions to form an electroplated film 56 having a thickness of 15 μm (see FIG. 5A). In addition, with this electroplating film 56, the thickness of the portion that becomes the conductor circuit 58 and the plating filling of the portion that becomes the via hole 60 are performed in the steps described later. The additive in the electroplating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0043]
[Electroplating aqueous solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
[Electroplating conditions]
Current density 1 A / dm2
65 minutes
Temperature 22 ± 2 ° C
[0044]
(14) Next, after removing the plating resist 54 with 5% NaOH, the Ni—Cu alloy layer 52 existing under the plating resist 54 is etched using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide. The conductive circuit 58 (including the via hole 60) having a thickness of 16 μm made of the electrolytic copper plating film 56 and the like was formed (see FIG. 5B).
[0045]
(15) Subsequently, by repeating the above steps (5) to (13), an upper interlayer resin insulation layer 150, a conductor circuit 158 and a via hole 160 were formed (see FIG. 5C).
[0046]
(16) Next, a photosensitizing agent obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight: 4000), 15 parts by weight of 80% by weight of bisphenol A type epoxy resin (trade name: Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (Shikoku Chemicals) Manufactured, product name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Nippon Kayaku Co., Ltd., product name: R604) as a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd.) , Trade name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by Sannopco, trade name: S-65) 0.71 layer An amount part is placed in a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photopolymerization initiator and Michler's ketone as a photosensitizer are mixed with this mixed composition. (Kanto Chemical Co., Ltd.) 0.2 parts by weight was added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity measurement was performed using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.). In the case of 4 or 6 rpm, the rotor No. 3 according.
[0047]
(17) Next, the solder resist composition is applied to both sides of the multilayer wiring board in a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist is applied. A photomask with a thickness of 5 mm on which the pattern of the opening is drawn is brought into close contact with the solder resist layer and 1000 mJ / cm2 And an opening 71 having a diameter of 200 μm was formed.
Further, the solder resist layer was cured by heating at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to open the solder pad portion. A solder resist layer (organic resin insulating layer) 70 having a thickness of 20 μm was formed (FIG. 6A). A resin film in which the solder resist is semi-cured may be attached, and the solder pad may be opened by exposure / development or laser.
[0048]
(18) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is made of nickel chloride (2.3 × 10-1mol / l), sodium hypophosphite (2.8 × 10-1mol / l), sodium citrate (1.6 × 10-1The nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71 by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l) (FIG. 6B). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6-3mol / l), ammonium chloride (1.9 × 10-1mol / l), sodium citrate (1.2 × 10-1mol / l), sodium hypophosphite (1.7 × 10-1The gold plating layer 74 having a thickness of 0.03 μm was formed on the nickel plating layer 72 by immersing in an electroless plating solution containing 1 mol / l) at 80 ° C. for 7.5 minutes.
[0049]
(19) Thereafter, a solder paste is printed in the opening of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps (solder bodies) 76S, 76V, 76G, and the multilayer printed wiring board 10 is completed. (See FIG. 7).
(20) Finally, the IC chip 90 is mounted on the solder bumps 76S, 76V, and 76G of the multilayer printed wiring board 10 so as to correspond to the pads 92S, 92V, and 92G, and the IC chip 90 is attached by performing reflow. Then, the package substrate 10 is placed on the daughter board 94 and placed on the daughter board by performing reflow (FIG. 8).
[0050]
Subsequently, a multilayer printed wiring board and a method for manufacturing the same according to a second embodiment of the present invention will be described.
FIG. 17 shows a cross section of a multilayer printed wiring board according to the second embodiment applied to a package substrate. The multilayer printed wiring board 110 of the second embodiment is the same as that of the first embodiment described above with reference to FIG. However, in the first embodiment, the solder bumps 76S, 76V, and 76G are disposed on the lower surface of the multilayer printed wiring board. However, in the second embodiment, the conductive connection pins 78 are disposed.
[0051]
Next, a method for manufacturing the multilayer printed wiring board according to the second embodiment will be described. Here, first, A. B. Production of a resin film for an interlayer resin insulation layer; The preparation of the resin filler will be described.
A. Preparation of resin film for interlayer resin insulation layer
30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy Co., Ltd.), 40 parts by weight of cresol novolac type epoxy resin (epoxy equivalent 215, Epiklon N-673 manufactured by Dainippon Ink & Chemicals, Inc.), triazine 30 parts by weight of a structure-containing phenol novolak resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 manufactured by Dainippon Ink & Chemicals, Inc.) was dissolved in 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha with stirring. Thereto, terminal epoxidized polybutadiene rubber (Nagase Kasei Kogyo Denarex R-45EPT) 15 parts by weight, 2-phenyl-4,5-bis (hydroxymethyl) imidazole pulverized product 1.5 parts by weight, finely pulverized silica 2 parts by weight , Silicon Added to prepare an epoxy resin composition agent 0.5 parts by weight.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer was produced.
[0052]
B. Preparation of resin filler
100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), SiO having an average particle diameter of 1.6 μm and a maximum particle diameter of 15 μm or less coated with a silane coupling agent on the surface2 170 parts by weight of spherical particles (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Perenol S4, manufactured by San Nopco) are placed in a container and mixed by stirring. A 49 Pa · s resin filler was prepared.
As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.
[0053]
Manufacturing method of multilayer printed wiring board
(1) A copper-clad laminate 30A in which 18 μm copper foil 32 is laminated on both surfaces of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm is used as a starting material (FIG. 11). (See (A)). First, this copper clad laminate 30A is made of NaOH (10 g / l), NaClO.2 (40 g / l), NaThree POFour Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBHFour Reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath was performed to form a roughened surface 32β on the entire surface of the copper foil 32 (see FIG. 11B).
[0054]
(2) Next, the substrate 30 is placed on the table of the carbonic acid laser device described above with reference to FIG. 10 and irradiated with a carbon dioxide gas laser, whereby the through holes 33A having a diameter of 100 μm are formed at the center of the substrate 30 at a pitch of 300 μm. Drill (see FIGS. 11C and 9B).
[0055]
(3) Then, through holes 33B having a diameter of 300 μm are formed at a pitch of 600 μm in the outer peripheral portion of the core substrate 30 with a drill 98 (see FIGS. 11D and 9B).
Then, after immersing in an electroless plating solution and depositing a copper plating film on the side walls of the through holes 33A and 33B to form the through holes 36A and 36B (FIG. 12A), a pattern is formed according to a conventional method. Then, an inner layer copper pattern (lower conductor circuit) 34 was formed on both sides of the substrate by etching (FIG. 12B).
[0056]
(4) The substrate on which the lower conductor circuit 34 is formed is washed with water and dried, and then an etching solution is sprayed on both sides of the substrate to spray the surface of the lower conductor circuit 34 and the surfaces of the lands 36a and inner walls of the through holes 36A and 36B. And a roughened surface 34β was formed on the entire surface of the lower conductor circuit 34, and a roughened layer 36β was formed on the surfaces and inner walls of the lands 36a of the through holes 36A and 36B (see FIG. 12C). As an etching solution, a mixture of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride and 78 parts by weight of ion-exchanged water was used.
[0057]
(5) After adjusting the resin filler described in B above, within 24 hours after adjustment by the following method, the through-holes 36A and 36B and the conductor circuit non-forming portion on one side of the substrate 30 and the conductor circuit 34 A layer of the resin filler 40 was formed on the outer edge portion (see FIG. 12D).
That is, first, the resin filler 40 was pushed into the through holes 36A and 36B using a squeegee, and then dried at 100 ° C. for 20 minutes. Next, a mask having an opening corresponding to the conductor circuit non-forming portion is placed on the substrate, and a layer of the resin filler 40 is formed on the conductor circuit non-forming portion, which is a recess, using a squeegee. Drying was performed at 20 ° C. for 20 minutes.
[0058]
(6) The surface of the inner layer copper pattern 4 and the land of the through holes 36A and 36B are polished on one side of the substrate after the processing of (5) by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Polishing was performed so that the resin filler 40 did not remain on the surface 36a, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.
Next, heat treatment was performed at 100 ° C. for 1 hour and 150 ° C. for 1 hour to cure the resin filler 40.
[0059]
In this way, the surface layer portion of the resin filler 40 and the surface of the lower conductor circuit 34 formed in the through holes 36A and 36B and the conductor circuit non-forming portion are flattened, and the resin filler 40 and the side surfaces of the lower conductor circuit 34 are Was firmly adhered via the roughened surface 34β, and the inner wall surfaces of the through holes 36A and 36B and the resin filler 40 were firmly adhered via the roughened surface 36β (FIG. 13 (FIG. 13)). A)). That is, by this step, the surface of the resin filler 40 and the surface of the lower conductor circuit 34 are flush with each other.
[0060]
(7) After washing the substrate with water and acid degreasing, soft etching is performed, and then an etching solution is sprayed on both sides of the substrate to spray the surface of the lower layer conductor circuit 34, the surface of the land 36a and the inner wall of the through holes 36A and 36B. And the roughened surface 34β was formed on the entire surface of the lower conductor circuit 34, and the roughened layer 36β was formed on the surface of the land 36a of the through hole (see FIG. 13B).
As an etchant, an etchant (MEC Etch Bond, manufactured by MEC Co.) consisting of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used.
[0061]
(8) A resin film for an interlayer resin insulation layer that is slightly larger than the substrate prepared in A above is placed on both sides of the substrate, and the pressure is 4 kgf / cm.2 After being temporarily crimped and cut under the conditions of a temperature of 80 ° C. and a crimping time of 10 seconds, an interlayer resin insulation layer 50 was formed by further bonding using a vacuum laminator device by the following method (FIG. 13C). reference). That is, a resin film for an interlayer resin insulation layer is placed on a substrate with a degree of vacuum of 0.5 Torr and a pressure of 4 kgf / cm.2 The film was subjected to main pressure bonding under conditions of a temperature of 80 ° C. and a pressure bonding time of 60 seconds, and then thermally cured at 170 ° C. for 30 minutes.
[0062]
(9) A mask 49 having a through hole 49a having a thickness of 1.2 mm is placed on the interlayer resin insulation layer 50. And CO of wavelength 10.4 μm2 Using a gas laser, a via hole opening with a diameter of 80 μm in the interlayer resin insulation layer 50 under the conditions of a beam diameter of 4.0 mm, a top hat mode, a pulse width of 5.0 μs, a mask through-hole diameter of 1.0 mm, and one shot. 48 was formed (see FIG. 13D).
[0063]
(10) The substrate 30 on which the via hole opening 48 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 50. Thus, the surface of the interlayer resin insulating layer 50 including the inner wall of the via hole opening 48 was roughened (see FIG. 14A).
[0064]
(11) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and then washed with water. Furthermore, a catalyst catalyst is attached to the surface of the interlayer resin insulation layer 50 and the inner wall surface of the via hole opening 48 by applying a palladium catalyst to the surface of the substrate that has been roughened (roughening depth: 3 μm). It was.
[0065]
(12) Next, the substrate was immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 51 having a thickness of 0.6 to 3.0 μm over the entire rough surface (FIG. 14 ( B)).
[Electroless plating aqueous solution]
NiSOFour                   0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature
[0066]
(13) A commercially available photosensitive dry film is affixed to the electroless copper plating film 51, a mask is placed, and 100 mJ / cm2 Then, a plating resist 54 having a thickness of 30 μm was provided by developing with a 0.8% aqueous sodium carbonate solution (see FIG. 14C).
[0067]
(14) Next, the substrate is washed with 50 ° C. water and degreased, washed with 25 ° C. water and further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions to obtain an electrolytic copper having a thickness of 20 μm. A plating film 56 was formed (see FIG. 15A).
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside HL)
[Electrolytic plating conditions]
Current density 1 A / dm2
65 minutes
Temperature 22 ± 2 ° C
[0068]
(15) After stripping and removing the plating resist 54 with 5% NaOH, the electroless plating film 51 under the plating resist 54 is etched and removed with a mixed solution of sulfuric acid and hydrogen peroxide to remove the electroless copper plating film. A conductor circuit (including via hole 60) 58 having a thickness of 18 μm formed of 51 and an electrolytic copper plating film 56 was formed (see FIG. 15B).
[0069]
(16) The same treatment as in (7) was performed, and a roughened surface 62 was formed with an etching solution containing a cupric complex and an organic acid (see FIG. 15C).
[0070]
(17) By repeating the steps (8) to (16) above, an upper interlayer resin insulation layer 160, a conductor circuit 158 and a via hole 160 were further formed to obtain a multilayer wiring board (FIG. 16A). reference).
[0071]
(18) Next, a solder resist composition similar to that of the first embodiment is applied to both surfaces of the multilayer wiring board at a thickness of 20 μm, and dried at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes. Then, a photomask having a thickness of 5 mm on which the pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer and 1000 mJ / cm.2 And an opening 71 having a diameter of 200 μm was formed.
Further, the solder resist layer is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. A 20 μm solder resist pattern layer 70 was formed (FIG. 16B). As the solder resist composition, a commercially available solder resist composition or a resin film of a solder resist can be used.
[0072]
(19) Next, the substrate on which the solder resist layer 70 is formed is nickel chloride (2.3 × 10-1mol / l), sodium hypophosphite (2.8 × 10-1mol / l), sodium citrate (1.6 × 10-1The nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71 by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6-3mol / l), ammonium chloride (1.9 × 10-1mol / l), sodium citrate (1.2 × 10-1mol / l), sodium hypophosphite (1.7 × 10-1The gold plating layer 74 having a thickness of 0.03 μm was formed on the nickel plating layer 72 by immersing in an electroless gold plating solution containing (mol / l) at 80 ° C. for 7.5 minutes (FIG. 16C )).
[0073]
(20) Thereafter, a solder paste containing tin-lead is printed in the opening of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed, and further, the tin-lead is formed in the opening of the solder resist layer 70 on the other surface. After printing the solder paste containing antimony, solder bumps 76S, 76V, and 76G were provided on the upper surface by reflowing at 200 ° C. And the conductive connection pin 78 was arrange | positioned in the lower surface, and the printed circuit board 110 was manufactured (refer FIG. 17).
[0074]
Subsequently, a third embodiment of the present invention will be described. In the first and second embodiments described above, the through holes 33A and 33B are formed in the copper-clad laminate. On the other hand, in 3rd Embodiment, after forming a resin layer in a copper bonding laminated board, through-hole 33A, 34B is formed.
[0075]
A method of forming the core substrate according to the third embodiment will be described with reference to FIG.
(1) The starting material is a copper clad laminate 30A in which a 18 μm copper foil 32 is laminated on both surfaces of a substrate 30 made of glass epoxy resin having a thickness of 0.8 mm, BT, FR-4, and FR-5 resin. (See FIG. 18A). Etching into a pattern according to a conventional method formed inner layer copper patterns (lower conductor circuits) 31 on both surfaces of the substrate (FIG. 18B).
[0076]
(2) Next, an ABF resin insulating film, which will be described later, is attached to both surfaces of the substrate 30 to form a resin layer 35 (FIG. 18C).
(3) The substrate 30 is placed on the table of the carbonic acid laser device similar to that in the first embodiment, and irradiated with a carbon dioxide gas laser, the through holes 33A having a diameter of 100 μm are formed in the center of the substrate 30 at a pitch of 300 μm ( (See FIG. 18D).
[0077]
(3) Then, through holes 33B having a diameter of 300 μm are drilled at a pitch of 600 μm in the outer peripheral portion of the core substrate 30 with a drill 98 (see FIG. 18E).
(4) Then, after immersing in an electroless plating solution and depositing a copper plating film on the side walls of the through holes 33A and 33B to form the through holes 36A and 36B, etching is performed to form the conductor circuit 34. (See FIG. 18F). Since the subsequent steps are the same as those in the first and second embodiments described above, illustration and description are omitted.
[0078]
The ABF resin film contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.
[0079]
The resin film used in the production method of the present invention is a resin film in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a poorly soluble resin). It is.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0080]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0081]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0082]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0083]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. And it may consist of a mixture of two or more kinds of resins.
[0084]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified and other modified polybutadiene rubbers, carboxyl group-containing (meth) acrylonitrile / butadiene rubbers, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0085]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0086]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate and the like. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0087]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0088]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0089]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0090]
Specific examples of the hardly soluble resin include an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0091]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0092]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0093]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0094]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0095]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0096]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, dolomite, and the like. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0097]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0098]
In the above-described embodiment, the small-diameter through hole is disposed in the central portion and the large-diameter through hole is disposed in the outer peripheral portion. However, the present invention is not limited to this, and it is necessary to increase the wiring density. A small-diameter through hole can be appropriately disposed at the location.
[0099]
[Comparative Example 1]
This is the same as in the first embodiment, except that all the through holes in the core substrate are formed with a laser having a diameter of 100 μm.
[Comparative Example 2]
This is the same as in the first embodiment except that all the through holes of the core substrate are formed with a diameter of 300 μm by a drill.
[Comparative Example 3]
This is the same as in the second embodiment except that all the through holes of the core substrate are formed with a laser having a diameter of 100 μm.
[Comparative Example 4]
This is the same as in the second embodiment except that all the through holes of the core substrate are formed with a diameter of 300 μm by a drill.
[0100]
A high frequency IC chip of 1 GHz was mounted on the multilayer printed wiring boards of the first, second, and third embodiments and the multilayer printed wiring boards of Comparative Examples 1, 2, 3, and 4, respectively, and a comparative test was performed.
As a result, in Comparative Examples 2 and 4, IC chip errors frequently occurred. This is presumably due to the fact that the supply of power cannot keep up because the number of power lines and ground lines is small.
In contrast, the multilayer printed wiring boards of the first, second, and third embodiments and Comparative Examples 1 and 3 were able to provide stable operation. However, the multilayer printed wiring boards of Comparative Examples 1 and 3 have a very high manufacturing cost compared to the multilayer printed wiring boards of the first to third embodiments because all the through holes are formed by laser. In addition, the probability that the through hole is disconnected increases.
[Brief description of the drawings]
FIGS. 1A, 1B, 1C, and 1D are manufacturing process diagrams of a multilayer printed wiring board according to a first embodiment of the present invention.
2A, 2B, 2C, and 2D are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention. FIG.
3A, 3B, 3C, and 3D are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
4A, 4B, and 4C are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention. FIG.
5A, 5B, and 5C are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
6A and 6B are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.
FIG. 8 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.
FIG. 9A is an explanatory diagram showing wiring routing in the core substrate, and FIG. 9B is a plan view of the core substrate.
FIG. 10 is an explanatory diagram of a carbon dioxide laser device that forms an opening.
11A, 11B, 11C, and 11D are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.
12A, 12B, 12C, and 12D are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.
13A, 13B, and 13C are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.
14A, 14B, and 14C are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.
15A, 15B, and 15C are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.
16A, 16B, and 16C are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.
FIG. 17 is a cross-sectional view of a multilayer printed wiring board according to the second embodiment of the present invention.
FIG. 18 is a cross-sectional view of a core substrate of a multilayer printed wiring board according to the third embodiment of the present invention.
[Explanation of symbols]
30 core substrate
33A, 33B Through hole
34 Conductor circuit
36A Small diameter via hole
36B large diameter through hole
40 Resin filler
50 Interlayer resin insulation layer
58 Conductor circuit
60 Bahia Hall
70 Solder resist layer
76S, 76V, 76G Solder bump
150 Interlayer resin insulation layer
158 Conductor circuit
160 Viahole

Claims (3)

上下面を接続するスルーホールを形成した樹脂製のコア基板に層間樹脂絶縁層と導体回路とを交互に積層してなる多層プリント配線板において
前記コア基板の中央部に小径のスルーホールを配設し、外周部に大径のスルーホールを配設し、
前記小径のスルーホールに、信号線よりも多く電源線及び接地線を配設し、前記大径のスルーホールに、電源線及び接地線よりも多く信号線を配設したことを特徴とする多層プリント配線板。 It arranged small-diameter through hole in a central portion of the core substrate in a multilayer printed wiring board made of a resin core substrate formed with through holes for connecting the upper and lower surfaces formed by laminating an interlayer resin insulating layers and conductor circuits alternately And a large-diameter through hole on the outer periphery ,
A multilayer having a larger number of power lines and ground lines than the signal lines disposed in the small-diameter through hole, and a larger number of signal lines disposed than the power line and the ground line in the large-diameter through hole. Printed wiring board. 前記小径のスルーホールはレーザにより設けられた通孔に形成され、前記大径のスルーホールは、ドリルにより設けられた通孔に形成されていることを特徴とする請求項１の多層プリント配線板。2. The multilayer printed wiring board according to claim 1, wherein the small-diameter through hole is formed in a through hole provided by a laser, and the large-diameter through hole is formed in a through hole provided by a drill. . 少なくとも以下の（Ａ）〜（Ｂ）の工程を備えることを特徴とする多層プリント配線板の製造方法：
（Ａ）樹脂製のコア基板の中央部にレーザを照射しスルーホールとなる小径の通孔を形成する工程と、
（Ｂ）前記コア基板の外周部にドリルにより大径のスルーホールとなる通孔を形成する工程を備え、
前記小径の通孔に小径のスルーホールを形成し、前記大径の通孔に大径のスルーホールを形成し、
前記小径のスルーホールに、信号線よりも多く電源線及び接地線を配設し、前記大径のスルーホールに、電源線及び接地線よりも多く信号線を配設したことを特徴とする多層プリント配線板の製造方法。A method for producing a multilayer printed wiring board comprising at least the following steps (A) to (B):
(A) a step of irradiating a laser to a central portion of a resin core substrate to form a small-diameter through hole that becomes a through hole;
(B) a step of forming a through hole serving as a large-diameter through-hole with a drill on the outer periphery of the core substrate,
Forming a small diameter through hole in the small diameter through hole, forming a large diameter through hole in the large diameter through hole;
A multilayer having a larger number of power lines and ground lines than the signal lines disposed in the small-diameter through hole, and a larger number of signal lines disposed than the power line and the ground line in the large-diameter through hole. Manufacturing method of printed wiring board.
JP35386899A 1999-06-02 1999-12-14 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board Expired - Lifetime JP4282190B2 (en)

Priority Applications (19)

Application Number Priority Date Filing Date Title
JP35386899A JP4282190B2 (en) 1999-12-14 1999-12-14 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
US09/979,388 US6828510B1 (en) 1999-06-02 2000-05-25 Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
PCT/JP2000/003377 WO2000076281A1 (en) 1999-06-02 2000-05-25 Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
EP09156837A EP2086299A1 (en) 1999-06-02 2000-05-25 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
EP09156841A EP2086300A1 (en) 1999-06-02 2000-05-25 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
DE60031680T DE60031680T2 (en) 1999-06-02 2000-05-25 MULTILAYER, PRINTED PCB AND MANUFACTURING METHOD FOR A MULTILAYER, PRINTED PCB
EP06123074A EP1744609B1 (en) 1999-06-02 2000-05-25 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
EP00931571A EP1194022B1 (en) 1999-06-02 2000-05-25 Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
MYPI20002406A MY125537A (en) 1999-06-02 2000-05-30 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board.
TW089110559A TW471244B (en) 1999-06-02 2000-05-31 Multilayer printed circuit board and method of manufacturing multilayer printed circuit board
US10/921,525 US7985930B2 (en) 1999-06-02 2004-08-19 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US12/171,794 US8288664B2 (en) 1999-06-02 2008-07-11 Multi-layer printed circuit board and method of manufacturing multilayer printed circuit board
US12/694,322 US8283573B2 (en) 1999-06-02 2010-01-27 Multi-layer printed circuit board and method of manufacturing multilayer printed circuit board
US12/887,197 US20110024164A1 (en) 1999-06-02 2010-09-21 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US12/913,258 US8288665B2 (en) 1999-06-02 2010-10-27 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US13/089,378 US8822828B2 (en) 1999-06-02 2011-04-19 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US13/169,674 US8745863B2 (en) 1999-06-02 2011-06-27 Method of manufacturing multi-layer printed circuit board
US13/169,736 US8782882B2 (en) 1999-06-02 2011-06-27 Method of manufacturing multi-layer printed circuit board
US13/432,471 US8822830B2 (en) 1999-06-02 2012-03-28 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35386899A JP4282190B2 (en) 1999-12-14 1999-12-14 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JP2001168531A JP2001168531A (en) 2001-06-22
JP4282190B2 true JP4282190B2 (en) 2009-06-17

Family

ID=18433770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35386899A Expired - Lifetime JP4282190B2 (en) 1999-06-02 1999-12-14 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP4282190B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159734A (en) * 2010-01-29 2011-08-18 Kyocer Slc Technologies Corp Wiring board
JP2015191991A (en) * 2014-03-28 2015-11-02 京セラサーキットソリューションズ株式会社 wiring board

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101131759B1 (en) * 2003-04-07 2012-04-06 이비덴 가부시키가이샤 Multilayer printed wiring board
KR101014576B1 (en) 2004-02-24 2011-02-16 이비덴 가부시키가이샤 Substrate for mounting semiconductor
JP2006216713A (en) 2005-02-02 2006-08-17 Ibiden Co Ltd Multilayer printed wiring board
JP2012212867A (en) 2011-03-30 2012-11-01 Ibiden Co Ltd Printed wiring board and manufacturing method of the same
JP2013236039A (en) * 2012-05-11 2013-11-21 Renesas Electronics Corp Semiconductor device
JP2014110293A (en) * 2012-11-30 2014-06-12 Ibiden Co Ltd Printed wiring board for semiconductor element mounting and manufacturing method of the same
US20180240778A1 (en) * 2017-02-22 2018-08-23 Intel Corporation Embedded multi-die interconnect bridge with improved power delivery

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159734A (en) * 2010-01-29 2011-08-18 Kyocer Slc Technologies Corp Wiring board
JP2015191991A (en) * 2014-03-28 2015-11-02 京セラサーキットソリューションズ株式会社 wiring board

Also Published As

Publication number Publication date
JP2001168531A (en) 2001-06-22

Similar Documents

Publication Publication Date Title
WO2000076281A1 (en) Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
JP4508380B2 (en) Manufacturing method of multilayer printed wiring board
JP4282190B2 (en) Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
JP2001015931A (en) Multilayer printed wiring board and manufacture thereof
JP2003101244A (en) Multilayer printed wiring board and method of manufacturing the same
JP4863557B2 (en) Manufacturing method of multilayer printed wiring board
JP4278806B2 (en) Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
JP4707273B2 (en) Manufacturing method of multilayer printed wiring board
JP3916946B2 (en) Method for evaluating electrolytic plating solution and method for producing multilayer printed wiring board
JP4360737B2 (en) Printed wiring board and printed wiring board manufacturing method
JP4605888B2 (en) Multilayer printed wiring board and method for producing multilayer printed wiring board
JP4698046B2 (en) Multilayer printed circuit board
JP2002204057A (en) Multilayer printed wiring board and method of manufacturing the same
JP4817516B2 (en) Multilayer printed wiring board
JP4514308B2 (en) Manufacturing method of multilayer printed wiring board
JP2002047594A (en) Electroplating solution, method for producing multilayer printed circuit board using the same solution and multilayer printed circuit board
JP3219396B2 (en) Manufacturing method of multilayer printed wiring board
JP4666332B2 (en) Manufacturing method of multilayer printed wiring board
JP4748889B2 (en) Manufacturing method of multilayer printed wiring board
JP4428783B2 (en) Method for manufacturing printed wiring board
JP4484350B2 (en) Method for manufacturing printed wiring board
JP2000328256A (en) Electroless plating liquid and production of printed wiring board using the same
JP4518660B2 (en) Manufacturing method of multilayer printed wiring board
JP2003008221A (en) Multilayer printed wiring board and method of manufacturing the same
JP3219395B2 (en) Manufacturing method of multilayer printed wiring board

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20050901

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061122

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081216

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090205

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090317

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090317

R150 Certificate of patent or registration of utility model

Ref document number: 4282190

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120327

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130327

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140327

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term