JP4257357B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4257357B2 JP4257357B2 JP2006261823A JP2006261823A JP4257357B2 JP 4257357 B2 JP4257357 B2 JP 4257357B2 JP 2006261823 A JP2006261823 A JP 2006261823A JP 2006261823 A JP2006261823 A JP 2006261823A JP 4257357 B2 JP4257357 B2 JP 4257357B2
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- contact
- etching
- insulating film
- opening
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000005530 etching Methods 0.000 claims description 79
- 238000000034 method Methods 0.000 claims description 47
- 230000008021 deposition Effects 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 description 33
- 239000011229 interlayer Substances 0.000 description 20
- 238000001459 lithography Methods 0.000 description 20
- 239000007789 gas Substances 0.000 description 18
- 239000010410 layer Substances 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 238000002508 contact lithography Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Description
2…素子分離領域
3…ゲート絶縁膜
4…ゲート電極
5…シリコン窒化膜
6…ゲート層間絶縁膜
7…第1のコンタクト
8…絶縁膜
9…配線
10…配線層間絶縁膜
11…反射防止膜
12…レジスト
13…径小コンタクトパターン
14…大面積トレンチパターン
15…デポジション
16…第2のコンタクト
17…大面積トレンチ
Claims (4)
- 半導体基板上に形成された積層構造中の絶縁膜に開口幅の小さい第1開口部と開口幅の大きい第2開口部とを有するレジストマスクを形成するステップと、
前記第1開口部において前記絶縁膜を貫通する第1孔が形成されるようにエッチングする第1エッチングステップと、
第1孔内部、第2開口部下の前記絶縁膜に形成された凹部の底面及び側面、並びにレジストマスク上面にデポジション膜を形成するステップと
前記第2開口部において前記絶縁膜が露出するように前記凹部底面上及びレジストマスク上面上から前記デポジション膜をエッチングする第2エッチングステップと、
前記第2開口部において露出した前記絶縁膜を貫通する第2孔が形成されるようにエッチングする第3エッチングステップと
を具備し、
前記第1エッチングステップは、前記第1開口部におけるエッチングレートに比べて前記第2開口部におけるエッチングレートが小さい条件で行われる
半導体装置の製造方法。 - 請求項1において、
前記第1開口部の開口幅は100nm以下である
半導体装置の製造方法。 - 請求項1又は2において、
前記第2開口部の開口幅は1μm以上である
半導体装置の製造方法。 - 請求項1から3のいずれか1項において、
前記積層構造は、前記半導体基板と前記絶縁膜との間に形成された他の絶縁膜と、前記他の絶縁膜に形成されたコンタクトと、前記絶縁膜中に形成された配線層とを含み、
前記第1開口部は、前記配線層において配線が存在しない位置に対応して設けられ、
前記第1孔は、前記コンタクトに接続する
半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006261823A JP4257357B2 (ja) | 2006-09-27 | 2006-09-27 | 半導体装置の製造方法 |
US11/902,917 US7537990B2 (en) | 2006-09-27 | 2007-09-26 | Method of manufacturing semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006261823A JP4257357B2 (ja) | 2006-09-27 | 2006-09-27 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008085006A JP2008085006A (ja) | 2008-04-10 |
JP4257357B2 true JP4257357B2 (ja) | 2009-04-22 |
Family
ID=39225503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006261823A Expired - Fee Related JP4257357B2 (ja) | 2006-09-27 | 2006-09-27 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7537990B2 (ja) |
JP (1) | JP4257357B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6486137B2 (ja) | 2015-02-16 | 2019-03-20 | キヤノン株式会社 | 半導体装置の製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09134888A (ja) | 1995-11-10 | 1997-05-20 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPH10321724A (ja) | 1997-03-19 | 1998-12-04 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP4013308B2 (ja) | 1998-01-21 | 2007-11-28 | ヤマハ株式会社 | 配線形成方法 |
US6177340B1 (en) * | 1999-02-18 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure |
US6368974B1 (en) * | 1999-08-02 | 2002-04-09 | United Microelectronics Corp. | Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching |
KR100759602B1 (ko) * | 2000-05-12 | 2007-09-17 | 동경 엘렉트론 주식회사 | 자기 정렬 콘택트 에칭 방법 |
JP2003158179A (ja) | 2001-11-22 | 2003-05-30 | Rohm Co Ltd | 半導体装置およびその製造方法 |
KR100670662B1 (ko) * | 2003-11-28 | 2007-01-17 | 주식회사 하이닉스반도체 | 반도체소자 제조 방법 |
JP4331070B2 (ja) * | 2004-08-06 | 2009-09-16 | 株式会社東芝 | 半導体記憶装置 |
-
2006
- 2006-09-27 JP JP2006261823A patent/JP4257357B2/ja not_active Expired - Fee Related
-
2007
- 2007-09-26 US US11/902,917 patent/US7537990B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008085006A (ja) | 2008-04-10 |
US20080076250A1 (en) | 2008-03-27 |
US7537990B2 (en) | 2009-05-26 |
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