JP4224056B2 - 基板検査方法、プリント配線板および電子回路装置 - Google Patents
基板検査方法、プリント配線板および電子回路装置 Download PDFInfo
- Publication number
- JP4224056B2 JP4224056B2 JP2005369481A JP2005369481A JP4224056B2 JP 4224056 B2 JP4224056 B2 JP 4224056B2 JP 2005369481 A JP2005369481 A JP 2005369481A JP 2005369481 A JP2005369481 A JP 2005369481A JP 4224056 B2 JP4224056 B2 JP 4224056B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- blind via
- printed wiring
- wiring board
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/091—Locally and permanently deformed areas including dielectric material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1178—Means for venting or for letting gases escape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1377—Protective layers
- H05K2203/1394—Covering open PTHs, e.g. by dry film resist or by metal disc
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Length Measuring Devices By Optical Means (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Description
ブラインドビアホールを形成したプリント配線板に熱を加えたときに、ブラインドビアホールに、クラック、ピンホール、めっき不良など不具合箇所があると、この不具合箇所から、絶縁材を含む基材中のガスが流出する。本発明は、このビアホール内に流れ出たガスを捉え、利用することによって、導通検査で見過ごされてしまうブラインドビアホールの不良を容易に検出できるようにしたものである。
Claims (10)
- プリント配線板に形成されたブラインドビアホールの開口部に皮膜を形成し、前記プリント配線板を加熱した後の前記皮膜の形状変化から前記ブラインドビアホールの成形不良を判定することを特徴とする基板検査方法。
- 前記皮膜は前記ブラインドビアホールを設けたテストクーポンに形成されることを特徴とする請求項1記載の基板検査方法。
- 前記テストクーポンに前記ブラインドビアホールを複数設け、前記各ブラインドビアホール上の前記皮膜の形状変化により、前記プリント配線板に形成されたすべてのブラインドビアホールの成形不良を判定することを特徴とする請求項2記載の基板検査方法。
- 前記皮膜に、ドライフイルム若しくは他の耐熱性フイルム材若しくは耐熱性シート材を用いた請求項3記載の基板検査方法。
- 前記皮膜に、耐熱性接着剤若しくは耐熱性半硬化樹脂を用いた請求項3記載の基板検査方法。
- 前記皮膜に、半田皮膜若しくは他の金属皮膜を用いた請求項3記載の基板検査方法。
- ブラインドビアホールの開口部を皮膜で覆ったテストクーポンを具備したことを特徴とするプリント配線板。
- 前記テストクーポンに、複数のブラインドビアホールを設けたことを特徴とする請求項7記載のプリント配線板。
- 前記皮膜に、耐熱性フイルム材若しくは耐熱性半硬化樹脂若しくは金属皮膜を用いた請求項7記載のプリント配線板。
- ブラインドビアホールの開口部を皮膜で覆ったテストクーポンを設けたプリント配線板をリフロー処理し、前記皮膜で覆われた前記テストクーポンを品質管理パターンとして具備することを特徴とする電子回路装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005369481A JP4224056B2 (ja) | 2005-12-22 | 2005-12-22 | 基板検査方法、プリント配線板および電子回路装置 |
US11/635,407 US20070144775A1 (en) | 2005-12-22 | 2006-12-06 | Substrate inspection method, printed-wiring board, and electronic circuit device |
CN2006101707551A CN1988770B (zh) | 2005-12-22 | 2006-12-22 | 基板检查方法、印刷线路板、以及电子电路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005369481A JP4224056B2 (ja) | 2005-12-22 | 2005-12-22 | 基板検査方法、プリント配線板および電子回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007173543A JP2007173543A (ja) | 2007-07-05 |
JP4224056B2 true JP4224056B2 (ja) | 2009-02-12 |
Family
ID=38185357
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005369481A Active JP4224056B2 (ja) | 2005-12-22 | 2005-12-22 | 基板検査方法、プリント配線板および電子回路装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20070144775A1 (ja) |
JP (1) | JP4224056B2 (ja) |
CN (1) | CN1988770B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008311584A (ja) * | 2007-06-18 | 2008-12-25 | Elpida Memory Inc | 半導体パッケージの実装構造 |
JP2011003642A (ja) * | 2009-06-17 | 2011-01-06 | Toshiba Corp | 欠陥検査方法 |
JP6064478B2 (ja) * | 2012-09-19 | 2017-01-25 | 富士通株式会社 | プリント配線板、クラック予知装置およびクラック予知方法 |
CN104064487B (zh) * | 2013-03-19 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | 一种硅通孔质量检测方法 |
CN105758891B (zh) * | 2015-07-17 | 2019-03-05 | 生益电子股份有限公司 | 一种pcb的性能检测方法 |
JP6778585B2 (ja) * | 2016-11-02 | 2020-11-04 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
CN106596581B (zh) * | 2016-11-18 | 2019-04-30 | 哈尔滨工业大学 | 测量表面形貌检测多层薄膜层间内部缺陷的方法 |
JP6661681B2 (ja) * | 2018-03-02 | 2020-03-11 | ファナック株式会社 | 回路基板及びその製造方法 |
CN109470699A (zh) * | 2018-10-15 | 2019-03-15 | 北京工业大学 | 一种tsv电镀铜填充效果的测试方法 |
-
2005
- 2005-12-22 JP JP2005369481A patent/JP4224056B2/ja active Active
-
2006
- 2006-12-06 US US11/635,407 patent/US20070144775A1/en not_active Abandoned
- 2006-12-22 CN CN2006101707551A patent/CN1988770B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1988770A (zh) | 2007-06-27 |
JP2007173543A (ja) | 2007-07-05 |
US20070144775A1 (en) | 2007-06-28 |
CN1988770B (zh) | 2012-05-09 |
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