JP4211606B2 - Manufacturing method of multilayer ceramic electronic component and electronic apparatus - Google Patents

Manufacturing method of multilayer ceramic electronic component and electronic apparatus Download PDF

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Publication number
JP4211606B2
JP4211606B2 JP2003530475A JP2003530475A JP4211606B2 JP 4211606 B2 JP4211606 B2 JP 4211606B2 JP 2003530475 A JP2003530475 A JP 2003530475A JP 2003530475 A JP2003530475 A JP 2003530475A JP 4211606 B2 JP4211606 B2 JP 4211606B2
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ceramic sheet
electronic component
ceramic
groove
multilayer ceramic
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JPWO2003026856A1 (en
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宗之 沢田
英則 勝村
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はチップ部品、半導体等を実装する平面精度に優れた積層セラミック電子部品の製造方法及びその電子部品を用いた電子機器に関する。
【０００２】
【従来の技術】
従来の積層セラミック電子部品の製造方法について説明する。まずガラスセラミック粉末に有機バインダーおよび可塑剤などを混合して第１のセラミックシートが得られる。次に第１のセラミックシートの表面に導体パターンが形成され、第１のセラミックシートが積層される。その後、第１のセラミックシートの上下に、第１のセラミックシートの焼成温度で焼結しない第２のセラミックシートが積層されて積層体が得られる。次にこの積層体の表面の第１のセラミックシートにスリットが形成された後に第１のセラミックシートの焼成温度で焼成され、焼結していない第２のセラミックシートが除去される。次いでスリットで積層体が分割され、積層セラミック電子部品が得られる。
【０００３】
この積層セラミック電子部品が、表面に電極パターンを有する回路基板に実装され電子機器が製造される。
【０００４】
上記積層セラミック電子部品においては、焼成時第２のセラミックシートは焼結せず殆ど収縮しないので、焼結により収縮しようとする第１のセラミックシートを拘束する。従って、第１のセラミックシートの収縮を抑制でき、平面精度に優れた積層セラミック電子部品を生産性良く得ることができる。
【０００５】
【発明が解決しようとする課題】
しかし上記方法によると、積層セラミック電子部品の端部は鋭角となる。従って、この電子部品が回路基板に実装される時に回路基板に撓みが発生すると、回路基板にこの端部が接触することにより、積層セラミック電子部品に割れや欠けが発生し、特性が劣化する。
【０００６】
【課題を解決するための手段】
第１のセラミックシートが第１のセラミックシートよりも高い焼結温度を有する第２のセラミックシートで挟まれて積層体が得られる。積層体に第１のセラミックシートに至る溝が、第２のセラミックシートが第１のセラミックシートの溝の上端部を被覆するように形成される。第１のセラミックシートが焼結しかつ第２のセラミックシートが焼結しない温度で積層体が焼成される。第２のセラミックシートが除去され、溝で積層体が分割されて、積層セラミック電子部品が製造される。
【０００７】
この方法により、平面精度を確保しつつ、耐衝撃性に優れた積層セラミック電子部品が製造される。
【０００８】
【発明の実施の形態】
（実施の形態１）
図１〜図４は本発明の実施の形態１における積層セラミック電子部品の製造工程を説明するための要部拡大断面図、図５は積層セラミック電子部品の断面図である。第１のセラミックシート１１はＡｌ2Ｏ3，ＣａＯ−ＢａＯ−ＳｉＯ2系ガラス等を用いて作製される。第２のセラミックシート１２は第１のセラミックシート１１の焼結温度よりも高い焼結温度を有し、Ａｌ2Ｏ3を用いて作製される。導体パターン１３はＡｇあるいはＡｇ−Ｐｔを用いて形成される。積層体にはスリット状の溝１４ａとＶ字状の溝１４ｂが設けられる。
【０００９】
図６は実施の形態１における電子機器の側面図である。表面に電極パターン６３を有する回路基板６４に図５に示す積層セラミック電子部品６０が実装される。
【００１０】
以下実施の形態１における積層セラミック電子部品の製造方法について説明する。
【００１１】
まず第１のセラミックシート１１と導体パターン１３とが交互に積層され、この上下面が第２のセラミックシート１２で挟み込まれて一体化された積層体が作製される。第１のセラミックシート１１と第２のセラミックシート１２の少なくとも一方の間には導体パターン１３が存在する。
【００１２】
次に、図１に示すようにカッター刃などで第１のセラミックシート１１に至るスリット状の溝１４ａが積層体の表面の所定の位置に形成され、続いて図２に示すように断面がＶ字状の金型で溝１４ａを押し開くようにして溝１４ｂが形成される。この時、金型の先端は第１のセラミックシート１１に到達する。溝１４ａ，１４ｂの形成後は、第２のセラミックシート１２が第１のセラミックシート１１の溝１４ａの内部上方の部分を被覆する。そして、第１のセラミックシート１１の溝１４ａを形成する部分の上端は曲面状に面取りされる。
【００１３】
またこの溝に対向するように、積層体裏面にも同様の溝１４ａ，１４ｂが設けられる。その後、この積層体がプレスされて、図３に示すように溝１４ｂが小さくなる。
【００１４】
そしてこの状態のまま、第１のセラミックシート１１及び導体パターン１３が焼結され、かつ第２のセラミックシート１２が焼結されないように積層体が焼成される。このとき、第２のセラミックシート１２は焼結されないのでほとんど収縮しない。従って、焼結する第１のセラミックシート１１が収縮するのを抑制され、平面精度に優れた焼結体が得られる。第１のセラミックシート１１の溝１４ｂの部分は自由度が他の部分よりも大きいので収縮し、溝１４ｂは再び図４に示すように大きくなる。
【００１５】
次に、第２のセラミックシート１２のみが除去される。第２のセラミックシート１２は未焼結なので、容易に除去できる。
【００１６】
次いで、導体パターン１３を有する表面にＩＣ６１やコンデンサ６２などが導体パターン１３に接続され、溝１４ａ，１４ｂで積層体が分割され、図５に示すような積層セラミック電子部品６０が得られる。
【００１７】
積層セラミック電子部品６０は、平面精度に優れているだけでなく端部が曲面状に面取りされるので、衝撃に強く優れた強度を有する。
【００１８】
積層セラミック電子部品６０が図６に示すように、表面の電極パターン６３を有する回路基板６４に実装されることにより、例えば携帯電話などの各種電子機器が製造される。
【００１９】
例えば電子機器に衝撃が加わり、回路基板６４に撓みが発生した場合、積層セラミック電子部品６０は端部が曲面状に面取りされるので、回路基板６４に接触したとしても回路基板６４の損傷を防止できる。
【００２０】
なお、溝１４ａ，１４ｂは別の方法で形成されてもよい。断面がＶ字状の金型が積層体表面の所定の位置に押し付けられて、断面がＶ字状の溝が形成される。この時、金型の先端が第１のセラミックシート１１に到達し、第２のセラミックシート１２が第１のセラミックシート１１の溝の内部上方を被覆する。第１のセラミックシート１１の溝を形成する部分の上端は曲面状に面取りされる。次にこの溝を更に深くするように、カッター刃などでスリット状の溝が設けられる。
【００２１】
導体パターン１３は導体パターンを含む抵抗体パターン等の回路パターンでもよい。
【００２２】
（実施の形態２）
まず実施の形態１と同様にして形成された積層体は、溝１４ａ，１４ｂが形成された後、実施の形態１と同様に焼成される。ただし、第１のセラミックシート１１と第２のセラミックシート１２との間に導体パターン１３が形成されない。
【００２３】
次に第２のセラミックシート１２が除去された後、焼結体の表面に金属ペーストが塗布され、焼き付けられることにより導体パターン１３が形成される。その後、この導体パターン１３の上にＩＣやコンデンサなどの電子部品が実装される。その後、溝１４ａ，１４ｂで積層体が分割され、積層セラミック電子部品６０が得られる。そして電子部品６０は回路基板に実装され、電子機器が製造される。
【００２４】
実施の形態２においても実施の形態１と同様に、得られた積層セラミック電子部品は平面精度に優れているだけでなく端部が曲面状に面取りされるので、衝撃に強く優れた強度を有する。また回路基板に実装後、撓みが発生したとしても積層セラミック電子部品６０は端部が曲面状に面取りされるので、回路基板６４に接触したとしても損傷を防止できる。
【００２５】
実施の形態２と実施の形態１とは、積層セラミック電子部品６０の表面の導体パターン１３が積層体の焼成前あるいは焼成後に形成されるかだけが異なる。
【００２６】
表面の導体パターン１３の形成に熱処理工程を含む場合、実施の形態１においては、熱処理工程が一度で済むので実施の形態２よりも生産性に優れる。
【００２７】
（実施の形態３）
図７は実施の形態３における積層セラミック電子部品の製造工程を説明するための要部拡大断面図である。実施の形態１，２と同様の構成要素については同番号を付して説明を省略する。
【００２８】
まず実施の形態１と同様に第１のセラミックシート１１と導体パターン１３を交互に積層され、上、下面を第２のセラミックシート１２が挟み込んだ積層体が作製され、溝１４ａ，１４ｂが表、裏面に設けられる。
【００２９】
次に、図７に示すようにこの積層体の上、下面の溝１４ａ，１４ｂを覆うように第２のセラミックシート１２と同様の材質の第３のセラミックシート１５が圧着される。この時、積層体は外周から加圧されるため、実施の形態１と同様に溝１４ａは最初に形成した時よりも小さくなる。
【００３０】
その後、この積層体が、第１のセラミックシート１１及び導体パターン１３が焼結しかつ第２と第３のセラミックシート１２、１５が未焼結となるように焼成される。この結果、実施の形態１と同様に溝１４ａは再び大きくなる。
【００３１】
次に第２と第３のセラミックシート１２、１５が除去され、積層体の表面にＩＣやコンデンサ等の電子部品が実装された後、溝１４ａ，１４ｂで積層体を分割され、図５に示すような積層セラミック電子部品が得られる。
【００３２】
実施の形態３においては、端部が曲面状に面取りされ、溝１４ａ，１４ｂを形成した後に第３のセラミックシート１５で積層体の上、下面が圧着される。これにより、焼成時の第１のセラミックシート１１の収縮をされに抑制できるので実施の形態１よりも平面精度に優れた積層セラミック電子部品を得ることができる。
【００３３】
実施の形態３においては積層セラミック電子部品表面の導体パターンは、実施の形態１のように焼成前、あるいは実施の形態２のように焼成後に形成されてもよい。
【００３４】
実施の形態１〜３においては、第２のセラミックシート１２が第１のセラミックシート１１の端部を被覆するように溝１４ａが設けられることにより、積層セラミック電子部品の端部を曲面状に面取りできる。
【００３５】
また従来の積層セラミック電子部品においては端部を曲面状に面取りするためには焼成後研磨する必要がある。電子部品が表面に導体パターン１３を有する場合、研磨により導体パターン１３が損傷する場合があるので端部を曲面にできない。この電子部品が回路基板に実装されると、基板に撓みが発生した場合端部が回路基板に接触し、積層セラミック電子部品が損傷することがある。導体パターン１３の代りに抵抗体パターンを有する電子部品では損傷により特性が劣化する。
【００３６】
Ｖ字状の溝１４ａとスリット状の溝１４ｂからなる断面がＹ字状の分割用の溝は、Ｖ字状の型で形成された部分よりも、刃で形成された部分の方が長い。これにより第１のセラミックシート１１の収縮を抑制しつつ、焼成後に積層体は容易に分割できる。
【００３７】
実施の形態１〜３ではこれらの溝は積層体の表、裏面に設けられるが、溝はいずれか一方の面にのみ設けられても焼成後積層体は容易に分割できる。溝は、積層体が回路基板に実装される際の基板に対向する面に形成され、撓みにより電子部品が損傷するのを防止することが好ましい。
【００３８】
さらに、第２のセラミックシート１２は、平面精度に優れた積層セラミック電子部品を得るため、焼成時に第１のセラミックシート１１が収縮するのを抑制する。第１及び第２のセラミックシート１１，１２の両方に分割用の溝が設けられると、それだけ第１のセラミックシート１１の自由度が大きくなる。これにより第１のセラミックシート１１は溝を大きくする方向に収縮しやすくなり、積層セラミック電子部品の形状精度が悪くなる恐れが有る。分割用の溝が設けられた後に積層体が加圧されて溝１４ａが圧縮され、見かけ上溝１４ａが小さくなる。これにより焼成時、第１のセラミックシートが収縮したとしても、前もって溝１４ａが圧縮されているので、元の状態、即ち所望の形状の焼結された積層体を得ることができる。
【００３９】
【発明の効果】
本発明によると、第１のセラミックシートとこれを挟むこれよりも高い焼結温度を有する第２のセラミックシートとを有する積層体の表面に、第１のセラミックシートに至るように溝が形成される。これにより、端部が曲面状に面取りされる耐衝撃性に優れた積層セラミック電子部品を得ることができる。
【図面の簡単な説明】
【図１】 本発明の実施の形態１における積層セラミック電子部品の要部拡大断面図
【図２】 実施の形態１における積層セラミック電子部品の要部拡大断面図
【図３】 実施の形態１における積層セラミック電子部品の要部拡大断面図
【図４】 実施の形態１における積層セラミック電子部品の要部拡大断面図
【図５】 本発明の実施の形態１，２における積層セラミック電子部品の断面図
【図６】 実施の形態１，２における電子機器の側面図
【図７】 本発明の実施の形態３における積層セラミック電子部品の要部拡大断面図
【符号の説明】
１１ 第１のセラミックシート
１２ 第２のセラミックシート
１３ 導体パターン
１４ａ 溝
１４ｂ 溝
１５ 第３のセラミックシート
６０ 積層セラミック電子部品
６１ ＩＣ
６２ コンデンサ
６３ 電極パターン
６４ 回路基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a multilayer ceramic electronic component excellent in planar accuracy for mounting a chip component, a semiconductor or the like, and an electronic apparatus using the electronic component.
[0002]
[Prior art]
A conventional method for manufacturing a multilayer ceramic electronic component will be described. First, an organic binder and a plasticizer are mixed with glass ceramic powder to obtain a first ceramic sheet. Next, a conductor pattern is formed on the surface of the first ceramic sheet, and the first ceramic sheet is laminated. Thereafter, a second ceramic sheet that is not sintered at the firing temperature of the first ceramic sheet is laminated above and below the first ceramic sheet to obtain a laminate. Next, after a slit is formed in the first ceramic sheet on the surface of the laminate, it is fired at the firing temperature of the first ceramic sheet, and the unsintered second ceramic sheet is removed. Next, the laminated body is divided by slits to obtain a laminated ceramic electronic component.
[0003]
This multilayer ceramic electronic component is mounted on a circuit board having an electrode pattern on its surface to manufacture an electronic device.
[0004]
In the multilayer ceramic electronic component, since the second ceramic sheet is not sintered and hardly contracted during firing, the first ceramic sheet to be contracted by sintering is restrained. Therefore, shrinkage of the first ceramic sheet can be suppressed, and a multilayer ceramic electronic component having excellent planar accuracy can be obtained with high productivity.
[0005]
[Problems to be solved by the invention]
However, according to the above method, the end of the multilayer ceramic electronic component has an acute angle. Therefore, when the circuit board is bent when the electronic component is mounted on the circuit board, the end portion comes into contact with the circuit board, so that the multilayer ceramic electronic component is cracked or chipped, and the characteristics are deteriorated.
[0006]
[Means for Solving the Problems]
The first ceramic sheet is sandwiched between the second ceramic sheets having a higher sintering temperature than the first ceramic sheet to obtain a laminate. A groove reaching the first ceramic sheet is formed in the laminate so that the second ceramic sheet covers the upper end of the groove of the first ceramic sheet. The laminate is fired at a temperature at which the first ceramic sheet is sintered and the second ceramic sheet is not sintered. The second ceramic sheet is removed, and the multilayer body is divided by the grooves to produce a multilayer ceramic electronic component.
[0007]
By this method, a multilayer ceramic electronic component excellent in impact resistance is manufactured while ensuring planar accuracy.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
1 to 4 are enlarged cross-sectional views of main parts for explaining the manufacturing process of the multilayer ceramic electronic component according to Embodiment 1 of the present invention, and FIG. The first ceramic sheet 11 is produced using Al 2 O 3 , CaO—BaO—SiO 2 glass or the like. The second ceramic sheet 12 has a sintering temperature higher than the sintering temperature of the first ceramic sheet 11, and is produced using Al 2 O 3 . The conductor pattern 13 is formed using Ag or Ag-Pt. The laminated body is provided with slit-shaped grooves 14a and V-shaped grooves 14b.
[0009]
FIG. 6 is a side view of the electronic device according to the first embodiment. A multilayer ceramic electronic component 60 shown in FIG. 5 is mounted on a circuit board 64 having an electrode pattern 63 on the surface.
[0010]
A method for manufacturing the multilayer ceramic electronic component according to Embodiment 1 will be described below.
[0011]
First, the first ceramic sheets 11 and the conductor patterns 13 are alternately laminated, and the upper and lower surfaces are sandwiched between the second ceramic sheets 12 to produce an integrated laminate. A conductor pattern 13 exists between at least one of the first ceramic sheet 11 and the second ceramic sheet 12.
[0012]
Next, as shown in FIG. 1, a slit-like groove 14a reaching the first ceramic sheet 11 with a cutter blade or the like is formed at a predetermined position on the surface of the laminate, and subsequently the cross section is V as shown in FIG. The groove 14b is formed by pushing the groove 14a open with a letter-shaped mold. At this time, the tip of the mold reaches the first ceramic sheet 11. After the formation of the grooves 14a and 14b, the second ceramic sheet 12 covers the upper part of the interior of the groove 14a of the first ceramic sheet 11. And the upper end of the part which forms the groove | channel 14a of the 1st ceramic sheet | seat 11 is chamfered in curved surface shape.
[0013]
Similar grooves 14a and 14b are also provided on the back surface of the laminate so as to face the grooves. Thereafter, this laminate is pressed, and the groove 14b becomes smaller as shown in FIG.
[0014]
In this state, the laminate is fired so that the first ceramic sheet 11 and the conductor pattern 13 are sintered and the second ceramic sheet 12 is not sintered. At this time, since the second ceramic sheet 12 is not sintered, it hardly shrinks. Therefore, shrinkage of the first ceramic sheet 11 to be sintered is suppressed, and a sintered body having excellent planar accuracy can be obtained. Since the portion of the groove 14b of the first ceramic sheet 11 has a greater degree of freedom than the other portions, it shrinks, and the groove 14b becomes larger again as shown in FIG.
[0015]
Next, only the second ceramic sheet 12 is removed. Since the second ceramic sheet 12 is unsintered, it can be easily removed.
[0016]
Next, an IC 61, a capacitor 62, and the like are connected to the conductor pattern 13 on the surface having the conductor pattern 13, and the multilayer body is divided by the grooves 14a and 14b to obtain a multilayer ceramic electronic component 60 as shown in FIG.
[0017]
The multilayer ceramic electronic component 60 is not only excellent in plane accuracy, but also has an endurance that is chamfered in a curved shape, and thus has excellent strength against impact.
[0018]
As shown in FIG. 6, the multilayer ceramic electronic component 60 is mounted on a circuit board 64 having a surface electrode pattern 63, whereby various electronic devices such as a mobile phone are manufactured.
[0019]
For example, when an impact is applied to the electronic device and the circuit board 64 is bent, the end of the multilayer ceramic electronic component 60 is chamfered in a curved shape, so that the circuit board 64 is prevented from being damaged even if it contacts the circuit board 64. it can.
[0020]
The grooves 14a and 14b may be formed by another method. A mold having a V-shaped cross section is pressed against a predetermined position on the surface of the laminated body to form a groove having a V-shaped cross section. At this time, the tip of the mold reaches the first ceramic sheet 11, and the second ceramic sheet 12 covers the upper part of the groove of the first ceramic sheet 11. The upper end of the part forming the groove of the first ceramic sheet 11 is chamfered into a curved surface. Next, a slit-like groove is provided by a cutter blade or the like so as to further deepen the groove.
[0021]
The conductor pattern 13 may be a circuit pattern such as a resistor pattern including a conductor pattern.
[0022]
(Embodiment 2)
First, the laminate formed in the same manner as in the first embodiment is fired in the same manner as in the first embodiment after the grooves 14a and 14b are formed. However, the conductor pattern 13 is not formed between the first ceramic sheet 11 and the second ceramic sheet 12.
[0023]
Next, after the second ceramic sheet 12 is removed, a metal paste is applied to the surface of the sintered body and baked to form the conductor pattern 13. Thereafter, electronic parts such as an IC and a capacitor are mounted on the conductor pattern 13. Thereafter, the multilayer body is divided by the grooves 14a and 14b, and the multilayer ceramic electronic component 60 is obtained. The electronic component 60 is mounted on a circuit board, and an electronic device is manufactured.
[0024]
In the second embodiment, similarly to the first embodiment, the obtained multilayer ceramic electronic component is not only excellent in plane accuracy, but also has an edge that is chamfered in a curved shape, so that it is strong against impact and has excellent strength. . In addition, even if bending occurs after mounting on the circuit board, the end of the multilayer ceramic electronic component 60 is chamfered in a curved shape, so that damage can be prevented even if it contacts the circuit board 64.
[0025]
The second embodiment is different from the first embodiment only in whether the conductive pattern 13 on the surface of the multilayer ceramic electronic component 60 is formed before or after firing the multilayer body.
[0026]
In the case where the formation of the conductive pattern 13 on the surface includes a heat treatment step, the first embodiment is superior in productivity to the second embodiment because the heat treatment step is only required once.
[0027]
(Embodiment 3)
FIG. 7 is an enlarged cross-sectional view of a main part for explaining a manufacturing process of the multilayer ceramic electronic component in the third embodiment. Constituent elements similar to those in the first and second embodiments are denoted by the same reference numerals and description thereof is omitted.
[0028]
First, similarly to the first embodiment, the first ceramic sheet 11 and the conductor pattern 13 are alternately laminated, and a laminate in which the upper and lower surfaces are sandwiched by the second ceramic sheet 12 is produced, and the grooves 14a and 14b are displayed. Provided on the back side.
[0029]
Next, as shown in FIG. 7, a third ceramic sheet 15 made of the same material as that of the second ceramic sheet 12 is pressure-bonded so as to cover the grooves 14a and 14b on the upper and lower surfaces of the laminate. At this time, since the laminated body is pressurized from the outer periphery, the groove 14a becomes smaller than when it is first formed as in the first embodiment.
[0030]
Thereafter, the laminate is fired so that the first ceramic sheet 11 and the conductor pattern 13 are sintered and the second and third ceramic sheets 12 and 15 are unsintered. As a result, the groove 14a becomes larger again as in the first embodiment.
[0031]
Next, after the second and third ceramic sheets 12 and 15 are removed and electronic parts such as ICs and capacitors are mounted on the surface of the laminate, the laminate is divided by grooves 14a and 14b, as shown in FIG. Such a multilayer ceramic electronic component can be obtained.
[0032]
In the third embodiment, the end portions are chamfered in a curved shape, and after the grooves 14a and 14b are formed, the upper and lower surfaces of the laminated body are pressure-bonded by the third ceramic sheet 15. Thereby, since the shrinkage | contraction of the 1st ceramic sheet | seat 11 at the time of baking can be suppressed, the multilayer ceramic electronic component excellent in planar accuracy than Embodiment 1 can be obtained.
[0033]
In the third embodiment, the conductor pattern on the surface of the multilayer ceramic electronic component may be formed before firing as in the first embodiment or after firing as in the second embodiment.
[0034]
In the first to third embodiments, the end portion of the multilayer ceramic electronic component is chamfered into a curved surface by providing the groove 14 a so that the second ceramic sheet 12 covers the end portion of the first ceramic sheet 11. it can.
[0035]
Further, in the conventional multilayer ceramic electronic component, in order to chamfer the end portion into a curved surface, it is necessary to polish after firing. When the electronic component has the conductor pattern 13 on the surface, the conductor pattern 13 may be damaged by polishing, so that the end cannot be curved. When this electronic component is mounted on a circuit board, when the board is bent, the end portion may contact the circuit board, and the multilayer ceramic electronic component may be damaged. In an electronic component having a resistor pattern instead of the conductor pattern 13, the characteristics deteriorate due to damage.
[0036]
A dividing groove having a Y-shaped cross section composed of a V-shaped groove 14a and a slit-shaped groove 14b has a longer portion formed by a blade than a portion formed by a V-shaped mold. Thereby, the laminated body can be easily divided after firing while suppressing the shrinkage of the first ceramic sheet 11.
[0037]
In Embodiments 1 to 3, these grooves are provided on the front and back surfaces of the laminate, but even if the grooves are provided only on one of the surfaces, the laminate can be easily divided after firing. The groove is preferably formed on a surface facing the substrate when the laminated body is mounted on the circuit substrate, and prevents the electronic component from being damaged by bending.
[0038]
Furthermore, the second ceramic sheet 12 suppresses the shrinkage of the first ceramic sheet 11 during firing in order to obtain a multilayer ceramic electronic component having excellent planar accuracy. If the dividing grooves are provided in both the first and second ceramic sheets 11 and 12, the degree of freedom of the first ceramic sheet 11 increases accordingly. As a result, the first ceramic sheet 11 tends to shrink in the direction of increasing the groove, and the shape accuracy of the multilayer ceramic electronic component may be deteriorated. After the dividing grooves are provided, the laminate is pressed to compress the grooves 14a, and the grooves 14a are apparently reduced. As a result, even if the first ceramic sheet contracts during firing, the groove 14a is compressed in advance, so that a sintered laminate in the original state, that is, a desired shape can be obtained.
[0039]
【The invention's effect】
According to the present invention, the groove is formed on the surface of the laminate having the first ceramic sheet and the second ceramic sheet having a higher sintering temperature sandwiching the first ceramic sheet so as to reach the first ceramic sheet. The Thereby, it is possible to obtain a multilayer ceramic electronic component excellent in impact resistance whose end is chamfered in a curved shape.
[Brief description of the drawings]
1 is an enlarged cross-sectional view of a main part of a multilayer ceramic electronic component according to a first embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of a main part of the multilayer ceramic electronic component according to a first embodiment. FIG. 4 is an enlarged cross-sectional view of the main part of the multilayer ceramic electronic component according to the first embodiment. 6 is a side view of an electronic device according to the first and second embodiments. FIG. 7 is an enlarged cross-sectional view of a main part of a multilayer ceramic electronic component according to a third embodiment of the present invention.
11 First ceramic sheet 12 Second ceramic sheet 13 Conductive pattern 14a Groove 14b Groove 15 Third ceramic sheet 60 Multilayer ceramic electronic component 61 IC
62 Capacitor 63 Electrode Pattern 64 Circuit Board

Claims (1)

第１のセラミックシートを前記第１のセラミックシートよりも高い焼結温度を有する第２のセラミックシートで挟み積層体を得る工程と、前記積層体の第１面に前記第１のセラミックシートに至る溝を形成する工程と、前記溝により分離された前記第２のセラミックシートの端部を前記第１のセラミックシートの上面よりも下にくるように前記溝の部分にＶ字状の型を押し付ける工程と、前記第１のセラミックシートが焼結しかつ前記第２のセラミックシートが焼結しない温度で前記積層体を焼成する工程と、前記第２のセラミックシートを除去する工程と、前記溝で前記積層体を分割する工程とを備えた、積層セラミック電子部品の製造方法。Sandwiching the first ceramic sheet with a second ceramic sheet having a sintering temperature higher than that of the first ceramic sheet to obtain a laminated body, and reaching the first ceramic sheet on the first surface of the laminated body Forming a groove and pressing a V-shaped mold against the groove so that the end of the second ceramic sheet separated by the groove is below the upper surface of the first ceramic sheet A step of firing the laminate at a temperature at which the first ceramic sheet is sintered and the second ceramic sheet is not sintered; and the second ceramic sheet is removed; and A method for manufacturing a multilayer ceramic electronic component, comprising the step of dividing the multilayer body.
JP2003530475A 2001-09-20 2002-08-30 Manufacturing method of multilayer ceramic electronic component and electronic apparatus Expired - Fee Related JP4211606B2 (en)

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JP2001286815 2001-09-20
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