JP4202389B2 - バイポーラ半導体構成要素、特にバイポーラ・トランジスタ、および対応するバイポーラ半導体構成要素の製造方法 - Google Patents
バイポーラ半導体構成要素、特にバイポーラ・トランジスタ、および対応するバイポーラ半導体構成要素の製造方法 Download PDFInfo
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Description
図2は、非特許文献1に開示している周知のDPSAトランジスタの略図である。
ティー.エフ.マイスター(T.F.Meister)他著、「アイイーディーエム テクニカル ダイジェスト」(IEDM Technical Digest) 1995年、739〜741ページ ティー.エイチ.ニン(T.H.Ning)他著、「高性能および低電力遅延VLSI用の自己整合バイポーラ・トランジスタ」(Self−Aligned Bipolar Transistor for High−Performance and Low−Power−Delay VLSI)、1981年の電子デバイスに関するIEEE議事録(IEEE Transactions on Electron Devices)、第ED−28巻、9号、1010〜1013ページ
ある好ましい態様によれば、第1の半導体領域は、その下に第2の導電型の関連するコレクタ領域が予め形成されるバイポーラ・トランジスタのベース領域である。第2の半導体領域は、関連するエミッタ領域である。
他の好ましい態様によれば、半導体構成要素はDPSAトランジスタである。
図面中の同じ参照符号は、同一または同じような動作をする要素である。
fTは遷移周波数であり、
τfは遷移時間であり、
RCはコレクタ抵抗であり、
REはエミッタ抵抗であり、
CBCはベース・コレクタ間容量であり、
CBEはベース・エミッタ間容量であり、
ICはコレクタ電流であり、
UTは熱電圧である。
選択的SiGeベース・エピタキシーにより製造したDPSAトランジスタの周知の製造方法は、すでに説明したように、例えば、独国特許第19958062明細書に記載されている。選択的ベース堆積からスタートする図の実施形態を理解するために最も重要な製造ステップについて以下に説明する。
内部スペーサを含む二重ポリシリコン自己整合トランジスタに基づいて本発明による方法を説明してきたが、この方法は原理的には薄いスペーサを含むすべての構成要素にも適している方法である。
34…ベース・キャップ層、90…窒化膜マスク、M…フォトマスク、100…中間誘電体、96,97,98…接点、110…接点配線、95…シリサイド。
Claims (12)
- バイポーラ半導体構成要素の製造方法であって、
半導体基板(1)上に第1の導電型(p)の第1の半導体領域(32,34)を形成するステップと、
前記半導体領域(32,34)上に前記第1の導電型(p+)の端子領域(40)を形成するステップと、
前記端子領域(40)上に第1の絶縁領域(35”)を形成するステップと、
前記半導体領域(32,34)の少なくとも一部を露出するために、前記第1の絶縁領域(35”)および端子領域(40)内にウィンドウ(F)を形成するステップと、
前記端子領域(40)を絶縁するために、前記ウィンドウ(F)内の側壁スペーサ(80)を形成するステップと、
前記側壁スペーサ(80)および前記周囲の第1の絶縁領域(35”)の一部をカバーするために、第2の導電型(n+)の第2の半導体領域(60)を形成するステップと、
前記端子領域(40)と前記第2の半導体領域(60)との間にギャップ(LS)を形成するために、前記周囲の第1の絶縁領域(35”)および前記側壁スペーサ(80)を除去するステップと、
前記ギャップ(LS)内に気体または真空雰囲気を導入するステップと、
前記ギャップ(LS)内に気体または真空雰囲気を導入した状態で、第2の絶縁領域(100)により前記ギャップ(LS)を封鎖するステップとを含む方法。 - 前記半導体構成要素はバイポーラ・トランジスタである請求項1に記載の方法。
- 前記バイポーラ・トランジスタはDPSAトランジスタである請求項1又は2に記載の方法。
- 前記第1の半導体領域(32,34)が、その下に前記第2の導電型(n−)のコレクタ領域(25)が予め形成されるバイポーラ・トランジスタのベース領域であり、前記第2の半導体領域(60)はエミッタ領域であることを特徴とする、請求項2または3に記載の方法。
- 前記第1の絶縁領域(35”)および前記側壁スペーサ(80)が同じ半導体材料から形成されており、前記第1および第2の半導体領域(40;60)から同じエッチング・プロセスにより選択的に除去されることを特徴とする、請求項1乃至4のいずれか一項に記載の方法。
- 前記第1の絶縁領域(35”)および前記側壁スペーサ(80)は酸化シリコンから形成されている請求項5に記載の方法。
- 前記第2の絶縁領域(100)が、絶縁材料の等角でない堆積および平面化により形成されることを特徴とする、請求項1乃至5の何れか一項に記載の方法。
- バイポーラ半導体構成要素であって、
半導体基板(1)上の第1の導電型(p)の第1の半導体領域(32,34)と、
前記半導体領域(32,34)と接続している前記第1の導電型(p+)の端子領域(40)と、
前記端子領域(40)内のウィンドウ(F)と、
前記ウィンドウ(F)内に位置し、かつ、部分的には前記周囲の端子領域(40)上に位置する前記第2の導電型(n+)の第2の半導体領域(60)と、
前記端子領域(40)と前記第2の半導体領域(60)との間のギャップ(LS)と、
等角でなく堆積されかつ平面化されて前記ギャップを封鎖する絶縁材料と、
封鎖されたギャップ内の気体または真空雰囲気とを備える半導体構成要素。 - 前記半導体構成要素はバイポーラ・トランジスタである請求項8に記載の半導体構成要素。
- 前記バイポーラ・トランジスタはDPSAトランジスタである請求項9に記載の半導体構成要素。
- 前記半導体構成要素の接続のために少なくとも一つの金属線(110)が、等角でなく堆積されかつ平面化されて前記ギャップを封鎖する絶縁材料(100)上に設けられている請求項9に記載の半導体構成要素。
- 前記第1の半導体領域(32,34)が、その下に前記第2の導電型(n−)のコレクタ領域(25)が予め形成されるバイポーラ・トランジスタのベース領域であり、前記第2の半導体領域(60)が前記エミッタ領域であることを特徴とする、請求項8乃至11のいずれか一項に記載の半導体構成要素。
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PCT/EP2004/003805 WO2004090988A1 (de) | 2003-04-10 | 2004-04-08 | Verfahren zur herstellung eines bipolaren halbleiterbauelements, insbesondere eines bipolartransistors, und entsprechendes bipolares halbleiterbauelement |
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US7687887B1 (en) * | 2006-12-01 | 2010-03-30 | National Semiconductor Corporation | Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter |
US7679164B2 (en) | 2007-01-05 | 2010-03-16 | International Business Machines Corporation | Bipolar transistor with silicided sub-collector |
DE102009001552A1 (de) * | 2008-12-12 | 2010-06-17 | Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik | Bipolartransistor mit selbstjustiertem Emitterkontakt |
US8736355B2 (en) * | 2012-06-12 | 2014-05-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device layout for reference and sensor circuits |
US9166067B2 (en) | 2012-06-12 | 2015-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device layout for reference and sensor circuits |
US9231074B2 (en) | 2013-07-19 | 2016-01-05 | Globalfoundries Inc. | Bipolar junction transistors with an air gap in the shallow trench isolation |
US10211090B2 (en) | 2016-10-12 | 2019-02-19 | Globalfoundries Inc. | Transistor with an airgap for reduced base-emitter capacitance and method of forming the transistor |
US10453919B2 (en) * | 2017-11-06 | 2019-10-22 | Stmicroelectronics (Crolles 2) Sas | Heterojunction bipolar transistor with counter-doped collector region and increase collector dependent breakdown voltage |
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DE19748523C2 (de) * | 1997-11-03 | 1999-10-07 | Siemens Ag | Halbleiterbauelement, Verfahren zum Herstellen eines derartigen Halbleiterbauelementes und Verwendung des Verfahrens |
US6693335B2 (en) * | 1998-09-01 | 2004-02-17 | Micron Technology, Inc. | Semiconductor raised source-drain structure |
DE19958062C2 (de) | 1999-12-02 | 2002-06-06 | Infineon Technologies Ag | Verfahren zur Herstellung eines Bipolartransistors und Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit einem solchen Bipolartransistor |
US6346453B1 (en) * | 2000-01-27 | 2002-02-12 | Sige Microsystems Inc. | Method of producing a SI-GE base heterojunction bipolar device |
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FR2806831B1 (fr) * | 2000-03-27 | 2003-09-19 | St Microelectronics Sa | Procede de fabrication d'un transistor bipolaire de type double-polysilicium auto-aligne a base a heterojonction et transistor correspondant |
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JP2006523010A (ja) | 2006-10-05 |
EP1611615B1 (de) | 2011-08-31 |
US7285470B2 (en) | 2007-10-23 |
US20060040456A1 (en) | 2006-02-23 |
WO2004090988A1 (de) | 2004-10-21 |
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