JP4051326B2 - 電子装置の製造方法 - Google Patents
電子装置の製造方法 Download PDFInfo
- Publication number
- JP4051326B2 JP4051326B2 JP2003302190A JP2003302190A JP4051326B2 JP 4051326 B2 JP4051326 B2 JP 4051326B2 JP 2003302190 A JP2003302190 A JP 2003302190A JP 2003302190 A JP2003302190 A JP 2003302190A JP 4051326 B2 JP4051326 B2 JP 4051326B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- wiring board
- electronic device
- wiring
- fine metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
2・・・・電子部品素子
3・・・・絶縁性樹脂材
4・・・・導電性樹脂材
5・・・・グランド配線パターン
6・・・・信号配線パターン
7・・・・グランド電極端子
8・・・・信号電極端子
9・・・・グランド用金属細線
10・・・信号用金属細線
20・・・大型基板
Claims (1)
- 複数の配線基板領域を有する大型基板を形成し、該大型基板の各配線基板領域に、グランド配線パターンを形成するとともに、上面に複数の接続電極を有する電子部品素子を載置する工程1と、
前記グランド配線パターンと前記接続電極とを、ループ形状をなす金属細線を介して接続する工程2と、
絶縁性を有する第1の液状樹脂を、前記電子部品素子全体を覆い、且つ前記金属細線の一部が露出するようにして、全ての配線基板領域にわたって塗布することにより絶縁性樹脂を形成する工程3と、
導電性粒子を含有する第2の液状樹脂を、前記絶縁性樹脂の上面及び金属細線の露出部を覆うようにして全ての配線基板領域にわたって塗布することにより金属細線と電気的に接続させた導電性樹脂を形成する工程4と、
前記大型基板を各配線基板領域の外周に沿って絶縁性樹脂及び導電性樹脂と共に切断することにより複数の電子装置を切り出す工程5と、を含む電子装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003302190A JP4051326B2 (ja) | 2003-08-26 | 2003-08-26 | 電子装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003302190A JP4051326B2 (ja) | 2003-08-26 | 2003-08-26 | 電子装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005072392A JP2005072392A (ja) | 2005-03-17 |
JP4051326B2 true JP4051326B2 (ja) | 2008-02-20 |
Family
ID=34406525
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003302190A Expired - Fee Related JP4051326B2 (ja) | 2003-08-26 | 2003-08-26 | 電子装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4051326B2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7030469B2 (en) * | 2003-09-25 | 2006-04-18 | Freescale Semiconductor, Inc. | Method of forming a semiconductor package and structure thereof |
CN1755929B (zh) * | 2004-09-28 | 2010-08-18 | 飞思卡尔半导体(中国)有限公司 | 形成半导体封装及其结构的方法 |
WO2007083352A1 (ja) | 2006-01-17 | 2007-07-26 | Spansion Llc | 半導体装置およびその製造方法 |
CN102105981B (zh) * | 2008-07-31 | 2013-11-13 | 斯盖沃克斯解决方案公司 | 集成的干扰屏蔽体的半导体封装体及其制造方法 |
US8373264B2 (en) | 2008-07-31 | 2013-02-12 | Skyworks Solutions, Inc. | Semiconductor package with integrated interference shielding and method of manufacture thereof |
JP4525866B2 (ja) * | 2008-08-19 | 2010-08-18 | 株式会社村田製作所 | 回路モジュール及びその製造方法 |
JP5779227B2 (ja) * | 2013-03-22 | 2015-09-16 | 株式会社東芝 | 半導体装置の製造方法 |
JP2015015498A (ja) * | 2013-03-22 | 2015-01-22 | 株式会社東芝 | 半導体装置 |
JP6835261B2 (ja) * | 2018-01-15 | 2021-02-24 | 株式会社村田製作所 | 電子部品パッケージおよびその製造方法 |
CN113594151B (zh) * | 2021-06-25 | 2024-05-14 | 苏州汉天下电子有限公司 | 半导体封装及其制造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06275741A (ja) * | 1993-03-19 | 1994-09-30 | Toppan Printing Co Ltd | 半導体装置 |
JP3797771B2 (ja) * | 1997-10-24 | 2006-07-19 | シチズン電子株式会社 | 赤外線リモートコントロール受光ユニット及びその製造方法 |
JP2001244688A (ja) * | 2000-02-28 | 2001-09-07 | Kyocera Corp | 高周波モジュール部品及びその製造方法 |
JP3718131B2 (ja) * | 2001-03-16 | 2005-11-16 | 松下電器産業株式会社 | 高周波モジュールおよびその製造方法 |
JP3632960B2 (ja) * | 2001-11-27 | 2005-03-30 | 京セラ株式会社 | 半導体装置 |
JP4662324B2 (ja) * | 2002-11-18 | 2011-03-30 | 太陽誘電株式会社 | 回路モジュール |
-
2003
- 2003-08-26 JP JP2003302190A patent/JP4051326B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005072392A (ja) | 2005-03-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20060113642A1 (en) | Semiconductor device | |
US7956453B1 (en) | Semiconductor package with patterning layer and method of making same | |
CN109155288B (zh) | 电子元件安装用基板和电子装置 | |
JPWO2007074846A1 (ja) | 微小電子機械装置およびその製造方法ならびに配線基板 | |
KR20160066311A (ko) | 반도체 패키지 및 반도체 패키지의 제조방법 | |
US10573591B2 (en) | Electronic component mounting board, electronic device, and electronic module | |
JP2012159935A (ja) | 電子部品モジュール、電子部品モジュールの製造方法、多機能カード | |
JP4051326B2 (ja) | 電子装置の製造方法 | |
JP2005252335A (ja) | 集積回路装置およびその製造方法 | |
JP2004055965A (ja) | 配線基板及び半導体装置並びにこれらの製造方法、回路基板並びに電子機器 | |
CN108028231B (zh) | 电子元件安装用基板以及电子装置 | |
JP6809876B2 (ja) | 配線基板、電子装置および配線基板の製造方法 | |
JP4057968B2 (ja) | 電子装置 | |
CN108735706B (zh) | 电子元件安装用基板、电子装置以及电子模块 | |
JP2005019900A (ja) | 電子装置 | |
JP3872378B2 (ja) | 電子装置 | |
JP4883882B2 (ja) | 電子装置 | |
JP2020053578A (ja) | 回路基板および電子部品 | |
JP4587587B2 (ja) | 電子部品搭載用基板 | |
JP7433766B2 (ja) | 回路基板、電子部品および電子モジュール | |
JP3935833B2 (ja) | 電子装置 | |
JP4558004B2 (ja) | 電子部品、シールドカバー、多数個取り用母基板、配線基板及び電子機器 | |
JP2005159184A (ja) | 電子装置の製造方法 | |
JP2011091451A (ja) | 電子装置 | |
JP2009111428A (ja) | 電子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060210 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060925 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20071109 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20071203 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101207 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101207 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111207 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111207 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121207 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131207 Year of fee payment: 6 |
|
LAPS | Cancellation because of no payment of annual fees |