JP4038519B2 - 統合ノード処理を用いる低密度パリティ検査符号の復号方法及び装置 - Google Patents
統合ノード処理を用いる低密度パリティ検査符号の復号方法及び装置 Download PDFInfo
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- H—ELECTRICITY
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1114—Merged schedule message passing algorithm with storage of sums of check-to-bit node messages or sums of bit-to-check node messages, e.g. in order to increase the memory efficiency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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Description
710 統合ノードプロセッサー
712 加算器/減算器
714 検査ノードプロセッサー
716 フリップフロップ
718 加算器
720 LLRメモリ
730 硬判定部
732 パリティー検査ブロック
734 ビットバッファ
740 検査ノードメッセージメモリ
Claims (20)
- パリティ検査ノード行列により複数の検査ノードと複数の変数ノードで構成される低密度パリティ検査符号を復号する装置であって、
前記検査ノードの中で、検査ノード処理を遂行する少なくとも一つの検査ノードを選択する検査ノード選択スケジューラーと、
前記変数ノードに対する入力LLR(Log Likelihood Ratio)値を初期LLR値として格納し、前記選択された検査ノードに接続された変数ノードに対してアップデートされたLLR値を格納するLLRメモリと、
前記選択された検査ノードに対して検査ノード処理が遂行された結果である検査ノードメッセージを格納する検査ノードメッセージメモリと、
前記LLRメモリから読み出された該当LLR値から、前記検査ノードメッセージメモリに格納されている前記選択された検査ノードの検査ノードメッセージを減算して変数ノードメッセージを生成し、前記変数ノードメッセージに対して検査ノード処理を遂行し、前記検査ノード処理結果値に前記変数ノードメッセージを加算してアップデートされたLLR値を計算し、前記計算されたLLR値を前記LLRメモリに伝達する少なくとも一つの統合ノードプロセッサーと、
を含むことを特徴とする装置。 - 前記検査ノード選択スケジューラーは、前記複数の検査ノードを一つずつインデキシングしてインデキシング順に選択し、或いは一定規則に従って前記複数の検査ノードのうちの少なくとも一つを選択することを特徴とする請求項1記載の装置。
- 前記検査ノード選択スケジューラーは、前記LLRメモリから同じLLR値が同時に読み出されないように前記少なくとも一つの検査ノードを選択することを特徴とする請求項2記載の装置。
- 前記アップデートされたLLR値を用いて硬判定を遂行する硬判定部と、
前記硬判定された結果を格納するビットバッファ部と、
前記硬判定された結果に対してパリティ検査を遂行し、パリティ検査結果が良いと、前記統合ノードプロセッサーの動作を中断させ、前記パリティ検査結果が悪いと、前記統合ノードプロセッサーの動作を反復させるパリティ検査部と、
をさらに含むことを特徴とする請求項1記載の装置。 - 前記パリティ検査部は、前記複数の検査ノードがすべて一度ずつ選択されたときに前記パリティ検査を遂行することを特徴とする請求項1記載の装置。
- 前記LLRメモリ及び検査ノードメッセージメモリは、前記複数の検査ノードに各々対応するサブメトリックブロックに分割されることを特徴とする請求項1記載の装置。
- 前記サブメトリックブロックは、それぞれ該当検査ノードに対応する検査ノードメッセージ値或いは該当検査ノードに接続された変数ノードのLLR値を格納することを特徴とする請求項9記載の装置。
- 前記少なくとも一つの統合ノードプロセッサーは、前記選択された少なくとも一つの選択された検査ノードに対応することを特徴とする請求項1記載の装置。
- パリティ検査ノード行列により複数の検査ノードと複数の変数ノードで構成される低密度パリティ検査符号を復号する方法であって、
前記複数の検査ノードのうち検査ノード処理を遂行する少なくとも一つの検査ノードを選択する段階と、
前記選択された検査ノードに対応する検査ノードメッセージを読み出し、前記検査ノードと接続された変数ノードのLLR値から前記検査ノードメッセージ値を減算して変数ノードメッセージを計算する段階と、
前記計算された変数ノードメッセージに検査ノード処理を遂行して検査ノードメッセージを生成し、前記生成された検査ノードメッセージを格納する段階と、
前記LLR値に前記生成された検査ノードメッセージを加算してアップデートされたLLR値を計算し格納する段階と、
前記アップデートされたLLR値に対して硬判定及びパリティ検査を遂行する段階と、
を有することを特徴とする方法。 - 前記選択する段階は、
前記複数の検査ノードを一つずつインデキシングしてインデキシング順に選択し、或いは一定規則に従って前記複数の検査ノードのうちの少なくとも一つを選択することを特徴とする請求項12記載の方法。 - 同じLLR値が同時に読み出されないように少なくとも一つの検査ノードを選択することを特徴とする請求項13記載の方法。
- 前記硬判定及びパリティ検査を遂行する段階は、
硬判定を遂行し、前期硬判定された結果に対してパリティ検査を遂行し、パリティ検査の結果が良いと、復号を中断し、パリティ検査の結果が悪いと、反復復号を遂行するパリティ検査部をさらに含んでなることを特徴とする請求項13記載の方法。 - 前記パリティ検査は、前記複数の検査ノードがすべて一度ずつ選択されたときに前記パリティ検査を遂行することを特徴とする請求項12記載の方法。
- 前記LLR値及び検査ノードメッセージは、前記複数の検査ノードに各々対応するサブメトリックブロックに分割されたメモリに格納されることを特徴とする請求項12記載の方法。
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Publication number | Publication date |
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KR20060057253A (ko) | 2006-05-26 |
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US7454685B2 (en) | 2008-11-18 |
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JP2006148937A (ja) | 2006-06-08 |
EP1659726A3 (en) | 2006-06-14 |
EP1659726A2 (en) | 2006-05-24 |
DE602005016355D1 (de) | 2009-10-15 |
US20060123318A1 (en) | 2006-06-08 |
AU2005225107B2 (en) | 2008-02-14 |
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