JP4023032B2 - Mounting structure and mounting method of semiconductor device - Google Patents

Mounting structure and mounting method of semiconductor device Download PDF

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JP4023032B2
JP4023032B2 JP15574599A JP15574599A JP4023032B2 JP 4023032 B2 JP4023032 B2 JP 4023032B2 JP 15574599 A JP15574599 A JP 15574599A JP 15574599 A JP15574599 A JP 15574599A JP 4023032 B2 JP4023032 B2 JP 4023032B2
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electrode
semiconductor chip
chip
semiconductor device
mounting structure
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JP2000349207A (en
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健史 渡辺
和仁 野村
平井　　康義
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

【０００１】
【発明の属する技術分野】
本発明は、大電力用半導体デバイスの電極との接合に用いられる半導体装置の実装構造及び実装方法に関する。
【０００２】
【従来の技術】
従来、半導体デバイスの電極と電気配線等との電気的接続は、図４に示すように、Ｓｉチップ５１に設けられた複数の電極５２のそれぞれにＡｌワイヤ５３を図中矢印で示すように、１つ１つＡｌワイヤ５３をワイヤボンディングすることによって行なっている。例えば、Ｓｉチップ５１に備えられた電極５２にφ２００μｍ以上のＡｌワイヤ５３を用いたワイヤボンディングが広く使用されている。
【０００３】
【発明が解決しようとする課題】
しかしながら、上記したように、大電力用半導体デバイスにＡｌワイヤ５３による接続方法を用いると、Ａｌワイヤ５３に大電流を流してＳｉ素子が発熱したときに、Ａｌワイヤ５３とＳｉチップ５１との熱膨張係数差によりボンディング部分に熱応力が生じ、ボンディング部周囲から中心部に向かって亀裂が進展し、接続不良となるという問題が発生しうる。
【０００４】
近年では、パワーデバイスとして、さらに大電流化が要求されるようになっているため、Ｓｉチップ５１に接続するＡｌワイヤ５３の多本数化、大径化が必要とされるのであるが、このような場合に特に上記問題が発生しやすくなる。
【０００５】
また、Ｓｉチップ５１の小型化に応じて、単位面積当たりの電流密度が大きくなるため、より発熱し、ワイヤボンディングの冷熱耐久寿命はさらに短くなる傾向にある。
【０００６】
本発明は上記問題に鑑みて成され、大電力用半導体デバイスの電極との電気的な接合部位における冷熱耐久性を向上させることを目的とする。
【０００７】
【課題を解決するための手段】
上記問題を解決すべく、請求項１に記載の発明においては、一面側に電極（２）が形成されてなるＳｉにて構成された半導体チップ（１）と、電極上に配置されたバンプ部（６）と、半導体チップのうち電極が形成されている面と対向する面を有してなり、バンプ部と接合されて、該バンプ部を介して電極と電気的に接合された接合部材（４）と、接合部材に接続されたリード（３）と、半導体チップのうち、電極が設けられた面の反対側に配置された第１の放熱板（８）とを有して構成され、接合部材と第１の放熱板とは、半導体チップの材料と熱膨張係数が近似するように、接合部材の材料はＭｏ、第１の放熱板はＡｌＮで構成され、接合部材と第１の放熱板とは同等の厚みで構成されていると共に、接合部材のうち、バンプ部と接する部位は、突起部（４ａ）となっていることを特徴とする。
このように、接合部材のうち、バンプ部と接する部位は、突起部（４ａ）にすると好ましい。
【０００８】
さらに、半導体チップを接合部材と第１の放熱板とで挟み込んだ構成にすると共に、これら接合部材と放熱板とを半導体チップと熱膨張係数が近似した材質となるように接合部材の材料をＭｏとすると共に第１の放熱板をＡｌＮで構成することにより、熱膨張係数差に基づく熱応力の発生を抑制することができる。このため、半導体チップとの電気的な接合部における冷熱耐久性を向上させることができる。
この場合、接合部材と第１の放熱板とを同等の厚みにすると、熱膨張係数差に基づく熱応力の発生を抑制することができる。
【０００９】
請求項２に記載の発明においては、接合部材を挟んで、半導体チップの反対側には、第２の放熱板（７）が配置されていることを特徴としている。
【００１０】
このように、第１、第２の放熱板で半導体チップを挟むようにすれば、第１、第２の放熱板のそれぞれで熱を放射させることができるため、半導体チップの高温化を抑制することができる。
【００１１】
例えば、請求項３に示すように、第１、第２の放熱板の外周を、枠部材（１８）で囲い、第１、第２の放熱板及び枠部材を、これらの間の液密性が保持されるように組付ければ、半導体装置を水等の冷却液中に入れ、冷却することも可能である。
【００１２】
なお、請求項１ないし５に記載の半導体装置の実装構造は、請求項６に示すように、半導体チップに１００Ａ／ｃｍ2以上の電流を流すような大電流用デバイスに用いると好適である。
【００１３】
また、請求項１ないし６に示す構造は、請求項７に示すように、半導体チップ（１）と接合部材（４）を備えたリード（３）とを用意し、電極と接合部材の間にバンプ部を配置したのち、該バンプ部を介して電極と接合部材とを接合し、接合部材のうちバンプ部と接する部位を突起部（４ａ）とすることにより製造される。
この場合、半導体チップのうち電極が形成された面の反対側に、接合部材と同等の厚みを有して構成されてなる放熱板（８）を配置すると好ましい。このような放熱板（８）をＡｌＮにて構成することができる。
【００１４】
この場合、請求項８に示すように、半導体チップ上に接合部材を備えたリードを搭載し、接合部材を超音波振動させることによって行なうことによって、接合部材と電極とを接合してもよい。
【００１５】
（参考実施形態）
上記実施形態では、Ｚｎ−Ｓｎはんだ６を介してリード３の先端位置に備えられた接合部材４とＳｉチップ１上の各エミッタ電極２との電気的接合を行なったが、この他の方法を用いて行なってもよい。
【００１６】
なお、上記括弧内の符号は、後述する実施形態における図中に表わされる符号との対応関係を示している。
【００１７】
【発明の実施の形態】
図１に、本発明の一実施形態を適用した大電力用デバイスの実装構造の断面構成を示す。以下、図１に基づき上記実装構造について説明する。
【００１８】
図１に示すＳｉチップ１には、電流がＳｉチップ１の表裏面方向に向かって流れるいわゆる縦型構造のＩＧＢＴが大電力用デバイスとして形成されている。このＩＧＢＴは複数のユニットセルで構成されている。そして、Ｓｉチップ１の表面には、複数のユニットセルからなるＩＧＢＴのそれぞれに電気的に接続された複数の電極２が形成されている。これら複数の電極２はＡｌで構成されており、ＩＧＢＴのエミッタ電極を構成している。以下、電極２をエミッタ電極という。
【００１９】
そして、エミッタ電極２に接続される引き出し用のリード３の先端、つまりエミッタ電極２との接続部位には、Ｓｉチップ１の表面と対向する面を有する接合部材４が配置されている。この接合部材４は、ＡｌよりもＳｉと熱膨張係数が近似しているＭｏで構成されている。
【００２０】
接合部材４のうちＳｉチップ１と対向する面には、複数のエミッタ電極２のそれぞれと対応する位置にそれぞれ突起部４ａが備えられている。これら突起部４ａの先端位置にはＮｉ／Ａｕメッキ５が施されており、このＮｉ／Ａｕメッキ５の表面にはＺｎ−Ｓｎはんだ６が配置されている。
【００２１】
そして、このＺｎ−Ｓｎはんだ６を介して、複数のエミッタ電極２と接合部材４が電気的に接合された状態となっている。このＺｎ−Ｓｎはんだ６に含まれているＺｎはＡｌに対して拡散定数が大きく、電気伝導性が良好な金属である。ただし、Ｚｎの融点が４２０℃と高温であるため、Ｓｎとの合金とすることによってＺｎ−Ｓｎの共晶温度１９８℃まで融点温度が低下するようにしている。
【００２２】
このように、エミッタ電極２からの引き出し用のリード３は、接合部材４を介してＳｉチップ１上のエミッタ電極２と電気的に接合されるように構成されている。
【００２３】
さらに、リード３のうち接合部材４が配置された側の反対側には、ＡｌＮで構成された放熱板７が備えられている。このように、Ｓｉチップ１の表面側においては、放熱板７を介して、Ｓｉチップ１が発した熱が放射できるようになっている。
【００２４】
一方、Ｓｉチップ１の裏面側には、ＡｌＮで構成された放熱板８が配置されている。この放熱板８は、接合部材４と略同等の厚みで構成されている。この放熱板８の表面には、金属箔配線９がパターニングされており、Ｓｉチップ１の裏面ははんだ１０を介して金属箔配線９に電気的に接続された状態となっている。そして、金属箔配線９には取り出し用のリード１１が接続されている。このように、Ｓｉチップ１の裏面側においては、放熱板８を介して、Ｓｉチップ１が発した熱が放射できるようになっている。
【００２５】
さらに、Ｓｉチップ１の表面側にはまた、ＩＧＢＴのゲート電極１２が形成されている。このゲート電極１２は、Ｚｎ−Ｓｎはんだ１３を介して配線部１４に接続されている。この配線部１４はＳｉチップ１の裏面側に接続された放熱板８方向に取り回され、はんだ１５を介して放熱板８上にパターニングされた金属箔配線１６に電気的に接続されている。そして、金属箔配線１６には取り出し用のリード１７が接続されている。
【００２６】
そして、Ｓｉチップ１の表面側に配置された放熱板７と、Ｓｉチップ１の裏面側に配置された放熱板８は同様の形状（例えば、４角形）で構成されており、これら放熱板７、８の外周を樹脂ケース１８で囲んで、Ｓｉチップ１の防水がなされるようになっている。
【００２７】
なお、樹脂ケース１８には、部分的に開口部が形成されており、この開口部を通じて各リード３、１１、１７が樹脂ケース１８の外部に引き出せるようになっている。
【００２８】
このように構成された大電力用デバイスの実装構造は、例えば、放熱板７、８を冷却液に浸すことで、放熱板７、８から冷却液へ放熱が行われるように構成される。このとき、Ｓｉチップ１の表裏面の両面において、放熱板７、８を配置し、両面から放熱が行われるようにしているため、片面のみから行われる場合に比して放熱効率を良好にすることができる。これにより、Ｓｉチップ１に例えば１００Ａ／ｃｍ2以上の大電流を流した時に、Ｓｉチップ１が発熱しても、Ｓｉチップ１が高温にならないようにすることができる。
【００２９】
このように、Ｓｉチップ１の高温化を抑制することによって、Ｓｉチップ１が高温となることによって発生するＳｉチップ１との電気的接合が行われる部分の熱膨張係数の相違による熱応力の発生をより低減することができる。
【００３０】
さらに、本実施形態の実装構造においては、Ｓｉチップ１と接合される基板として、接合部材４と放熱板８を用いている。これら、接合部材４と放熱板８は、それぞれＭｏとＡｌＮという、Ｓｉと熱膨張係数が近似する物質で構成しているため、Ｓｉチップ１との熱膨張係数の相違による熱応力が発生しにくくできる。このため、熱応力による接続部位の剥離が発生し難くすることができる。
【００３１】
ただし、ＭｏやＡｌＮの熱膨張係数がＳｉの熱膨張係数と近似しているとしても熱応力を完全に抑制することはできない。このため、本実施形態では、接合部材４と放熱板８によってＳｉチップ１を挟み込んだサンドイッチ構造とすることによって、Ｓｉチップ１の表裏に同等の熱応力が発生するようにでき、互いに打ち消し合うようにできるため、Ｓｉチップ１と接合部材４若しくは放熱板８との熱膨張係数の相違から生じるバイメタル効果による反りをさらに抑制することができる。
【００３２】
次に、本実施形態における大電流用デバイスの実装工程について説明する。この実装工程を図２に示し、この図に基づいて説明する。
【００３３】
まず、複数のユニットセルからなるＩＧＢＴ、及びこのＩＧＢＴのエミッタ電極２が形成されたＳｉチップ１を用意すると共に、先端位置に接合部材４が配置されたリード３を用意する。
【００３４】
この接合部材４は、Ｓｉチップ１と対向する面を有している。この面のうち、Ｓｉチップ１のエミッタ電極２のそれぞれと対応する位置には、突起部４ａが形成されており、この突起部４ａの先端をＮｉ／Ａｕメッキ５を施す。このように、Ｎｉメッキを施すことにより、Ｚｎ−Ｓｎはんだ６が濡れ易いようにできる。また、このようにＮｉメッキのみでなく、Ａｕメッキも施すことにより、Ｎｉメッキの酸化を防止することができる。
【００３５】
そして、各突起部４ａの先端にＺｎ−Ｓｎはんだ６を塗布したのち、対応し合う突起部４ａとエミッタ電極２のそれぞれが一致するように位置合わせして、リード３をＳｉチップ１上に搭載する。
【００３６】
そして、Ｚｎ−Ｓｎの共晶温度以上の温度、例えば２１０〜２５０℃の熱処理を施し、Ｚｎ−Ｓｎはんだ６を溶融する。これにより、エミッタ電極２及びＮｉ／Ａｕメッキ５にＺｎ−Ｓｎはんだ６が濡れ広がり、リード３とＳｉチップ１が接合される。
【００３７】
この後、表面に金属箔配線９、１６をパターニングした放熱板８を用意し、はんだ１０を介して放熱板８上の金属箔配線９とＳｉチップ１の裏面とを接続すると共に、配線部１４やはんだ１５を介してＳｉチップ１表面側に形成されたゲート電極１２と金属箔配線１６とを接合する。
【００３８】
接合手順は、はんだ材質によりＳｉチップ１と接合部材４を接合後、Ｓｉチップ１と放熱板８、Ｓｉチップ１と配線部１４を接合しても、Ｓｉチップ１と放熱板８を接合後、Ｓｉチップ１と接合部材４、Ｓｉチップ１と配線部１４を接合しても、Ｓｉチップ１と放熱板８、Ｓｉチップ１と接合部材４、Ｓｉチップ１と配線部１４を同時に接合してもよい。
【００３９】
そして、金属箔配線９、１６にリード１１、１７を接続すると共に、Ｓｉチップ１の表面側に配置されたリード３上に放熱板７を固定し、さらに放熱板７、８の外周を樹脂ケース１８で囲むことによって本実施形態に示す実装構造が完成する。
【００４０】
（他の実施形態）
上記実施形態では、Ｚｎ−Ｓｎはんだ６を介してリード３の先端位置に備えられた接合部材４とＳｉチップ１上の各エミッタ電極２との電気的接合を行なったが、この他の方法を用いて行なってもよい。
【００４１】
例えば、図３に示すように、接合部材４のうちＳｉチップ２と対向する面に、各エミッタ電極２のそれぞれと対応する位置に軟金属２０を配置する。この軟金属２０としては、例えば、Ａｌを採用することができる。そして、各エミッタ電極２と各軟金属２０とを位置合わせして、リード３をＳｉチップ１上に搭載する。その後、図中の矢印に示すように、超音波振動を加えることによって軟金属２０とエミッタ電極２とを擦り合わせることで、これらを電気的に接合する事も可能である。
【００４２】
なお、このとき、接合部分全体を３６０℃程度に加熱すれば、振動幅、振動速度を下げることができるため、振動によるＳｉチップ１のダメージを低減することができる。また、軟金属２０をＡｌ等で形成する場合、軟金属２０の両接合面をＡｕ膜で覆ったり、Ａｕ微粉末で覆ったりすることによって、よりエミッタ電極２や接合部材４と接合され易くすることもできる。
【００４３】
また、接合部材４に突起部４ａを形成しなくても接合部材４とＳｉチップ１とを接合する事も可能である。
【００４４】
例えば、Ｓｉチップの表面に備えられるエミッタ電極をＳｉチップの表面から突出するように構成し、接合部材にＺｎ−Ｓｎはんだを用いてはんだ付けすることができる。また、ＳｉチップのＡｌ電極上にＡｕバンプあるいはＣｕバンプを配置し、超音波接合によってＡｌ電極上の各バンプと接合部材とを接合するようにしてもよい。また、ＳｉチップのＡｌ電極上にＡｕバンプ等を配置したのち、Ａｕバンプなどに接合部材を押し付け、加熱処理を施す事で、各バンプと接合部材とを接合してもよい。
【図面の簡単な説明】
【図１】 本発明の一実施形態における大電流用デバイスの実装構造を表わす断面図である。
【図２】 図１の大電流用デバイスの実装方法を示す図である。
【図３】 他の実施形態における大電流用デバイスの実装構造を表わす断面図である。
【図４】 従来における大電流用デバイスの実装構造を表わす断面図である。
【符号の説明】
１…Ｓｉチップ、２…エミッタ電極、３、１１、１７…リード、３…接合部材、４ａ…突起部、５…Ｎｉ／Ａｕメッキ、６、１３…Ｚｎ−Ｓｎはんだ、７、８…放熱板、９、１６…金属箔配線、１０、１５…はんだ、１２…ゲート電極、１４…配線部、１８…樹脂ケース。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a mounting structure and a mounting method for a semiconductor device used for bonding to an electrode of a high power semiconductor device.
[0002]
[Prior art]
Conventionally, as shown in FIG. 4, the electrical connection between the electrode of the semiconductor device and the electric wiring or the like is such that an Al wire 53 is indicated by an arrow in each of the plurality of electrodes 52 provided on the Si chip 51. This is performed by wire bonding of Al wires 53 one by one. For example, wire bonding using an Al wire 53 with a diameter of 200 μm or more is widely used for the electrode 52 provided on the Si chip 51.
[0003]
[Problems to be solved by the invention]
However, as described above, when the connection method using the Al wire 53 is used for the high power semiconductor device, when the Si element generates heat when a large current is passed through the Al wire 53, the heat between the Al wire 53 and the Si chip 51 is generated. A thermal stress is generated in the bonding portion due to the difference in expansion coefficient, and a crack may develop from the periphery of the bonding portion toward the center portion, resulting in a problem of poor connection.
[0004]
In recent years, as a power device is required to have a larger current, it is necessary to increase the number of Al wires 53 connected to the Si chip 51 and increase the diameter. In particular, the above problem is likely to occur.
[0005]
Further, as the Si chip 51 is downsized, the current density per unit area increases, so that heat is generated more and the thermal durability life of wire bonding tends to be further shortened.
[0006]
The present invention has been made in view of the above problems, and an object of the present invention is to improve the thermal durability at an electrical junction site with an electrode of a high power semiconductor device.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, in the invention according to claim 1, a semiconductor chip (1) made of Si in which an electrode (2) is formed on one surface side, and a bump portion arranged on the electrode (6) and a bonding member having a surface facing the surface on which the electrode is formed in the semiconductor chip, bonded to the bump portion, and electrically bonded to the electrode via the bump portion ( 4), a lead (3) connected to the joining member, and a first heat radiating plate (8) disposed on the opposite side of the surface of the semiconductor chip where the electrodes are provided, The bonding member and the first heat radiating plate are made of Mo and the first heat radiating plate is made of AlN so that the thermal expansion coefficient is similar to that of the semiconductor chip material. with the plate is composed of equal thickness, of the bonding member in contact with the bump portion Position is characterized by that a protrusion (4a).
As described above, it is preferable that a portion of the bonding member that contacts the bump portion is a protrusion (4a).
[0008]
Further, the semiconductor chip is sandwiched between the joining member and the first heat radiation plate, and the material of the joining member is set to Mo so that the joining member and the heat radiation plate are made of a material whose thermal expansion coefficient approximates that of the semiconductor chip. In addition, by forming the first heat radiating plate with AlN, it is possible to suppress the generation of thermal stress based on the difference in thermal expansion coefficient. For this reason, it is possible to improve the thermal durability at the electrical junction with the semiconductor chip.
In this case, a junction member and a first heat radiating plate when the equivalent thickness, it is possible to suppress the generation of thermal stress due to thermal expansion coefficient difference.
[0009]
The invention according to claim 2 is characterized in that a second heat radiating plate (7) is disposed on the opposite side of the semiconductor chip with the joining member interposed therebetween.
[0010]
Thus, first, if to sandwich the semiconductor chip in the second discharge hot plate, first, since it is possible to radiate heat in each of the second heat radiating plate, suppressing the high temperature of the semiconductor chip can do.
[0011]
For example, as shown in claim 3 , the outer periphery of the first and second heat radiating plates is surrounded by a frame member (18), and the first and second heat radiating plates and the frame member are liquid-tight between them. If the semiconductor device is assembled so as to be held, it is possible to cool the semiconductor device by putting it in a coolant such as water.
[0012]
Incidentally, the mounting structure of a semiconductor device according to claims 1 to 5, as shown in claim 6, it is preferable to use a large current for devices such as flow 100A / cm 2 or more current into the semiconductor chip.
[0013]
In the structure shown in claims 1 to 6 , as shown in claim 7 , a semiconductor chip (1) and a lead (3) provided with a joining member (4) are prepared, and between the electrode and the joining member, After the bump portion is disposed, the electrode and the bonding member are bonded via the bump portion, and the portion of the bonding member that is in contact with the bump portion is formed as a protrusion (4a).
In this case, preferably on the opposite side of the surface on which the electrodes are formed of a semi-conductor chip, arranged a heat dissipating plate made is configured with a joint member equivalent thickness (8). Such radiating plate (8) can be configured by the A l N.
[0014]
In this case, as shown in claim 8 , a lead provided with a joining member may be mounted on a semiconductor chip, and the joining member and the electrode may be joined by performing ultrasonic vibration of the joining member.
[0015]
( Reference embodiment)
In the above embodiment, the bonding member 4 provided at the tip position of the lead 3 and the respective emitter electrodes 2 on the Si chip 1 are electrically connected via the Zn—Sn solder 6. May be used.
[0016]
In addition, the code | symbol in the said parenthesis has shown the correspondence with the code | symbol represented in the figure in embodiment mentioned later.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a cross-sectional configuration of a high-power device mounting structure to which an embodiment of the present invention is applied. Hereinafter, the mounting structure will be described with reference to FIG.
[0018]
In the Si chip 1 shown in FIG. 1, a so-called vertical structure IGBT in which a current flows toward the front and back surfaces of the Si chip 1 is formed as a high power device. This IGBT is composed of a plurality of unit cells. On the surface of the Si chip 1, a plurality of electrodes 2 electrically connected to each of the IGBTs composed of a plurality of unit cells are formed. The plurality of electrodes 2 are made of Al and constitute an IGBT emitter electrode. Hereinafter, the electrode 2 is referred to as an emitter electrode.
[0019]
A joining member 4 having a surface facing the surface of the Si chip 1 is disposed at the tip of the lead 3 for extraction connected to the emitter electrode 2, that is, at the connection portion with the emitter electrode 2. The joining member 4 is made of Mo which has a thermal expansion coefficient closer to that of Si than Al.
[0020]
On the surface of the bonding member 4 facing the Si chip 1, projections 4 a are provided at positions corresponding to the plurality of emitter electrodes 2, respectively. Ni / Au plating 5 is applied to the tip positions of the protrusions 4 a, and Zn—Sn solder 6 is disposed on the surface of the Ni / Au plating 5.
[0021]
The plurality of emitter electrodes 2 and the joining member 4 are electrically joined through the Zn—Sn solder 6. Zn contained in the Zn—Sn solder 6 is a metal having a large diffusion constant with respect to Al and good electrical conductivity. However, since the melting point of Zn is as high as 420 ° C., the melting point temperature is lowered to the eutectic temperature of Zn—Sn of 198 ° C. by using an alloy with Sn.
[0022]
Thus, the lead 3 for extraction from the emitter electrode 2 is configured to be electrically joined to the emitter electrode 2 on the Si chip 1 via the joining member 4.
[0023]
Further, a heat radiating plate 7 made of AlN is provided on the opposite side of the lead 3 to the side where the joining member 4 is disposed. Thus, on the surface side of the Si chip 1, heat generated by the Si chip 1 can be radiated through the heat dissipation plate 7.
[0024]
On the other hand, a heat radiating plate 8 made of AlN is disposed on the back side of the Si chip 1. The heat radiating plate 8 has a thickness substantially equal to that of the bonding member 4. A metal foil wiring 9 is patterned on the surface of the heat radiating plate 8, and the back surface of the Si chip 1 is electrically connected to the metal foil wiring 9 via a solder 10. A lead 11 for taking out is connected to the metal foil wiring 9. Thus, on the back side of the Si chip 1, the heat generated by the Si chip 1 can be radiated through the heat radiating plate 8.
[0025]
Further, an IGBT gate electrode 12 is also formed on the surface side of the Si chip 1. The gate electrode 12 is connected to the wiring part 14 via a Zn—Sn solder 13. This wiring portion 14 is routed in the direction of the heat sink 8 connected to the back side of the Si chip 1 and is electrically connected to the metal foil wiring 16 patterned on the heat sink 8 via the solder 15. A lead 17 for taking out is connected to the metal foil wiring 16.
[0026]
And the heat sink 7 arrange | positioned at the surface side of Si chip 1 and the heat sink 8 arrange | positioned at the back surface side of Si chip 1 are comprised by the same shape (for example, square shape), These heat sink 7 , 8 is surrounded by a resin case 18 so that the Si chip 1 is waterproofed.
[0027]
The resin case 18 is partially formed with an opening, and the leads 3, 11, and 17 can be drawn out of the resin case 18 through the opening.
[0028]
The high power device mounting structure configured as described above is configured such that heat is radiated from the heat sinks 7 and 8 to the coolant by immersing the heat sinks 7 and 8 in the coolant. At this time, since the heat radiation plates 7 and 8 are arranged on both the front and back surfaces of the Si chip 1 so that heat is radiated from both surfaces, the heat radiation efficiency is improved as compared with the case where the heat radiation is performed from only one surface. be able to. As a result, even when a large current of, for example, 100 A / cm 2 or more is passed through the Si chip 1, even if the Si chip 1 generates heat, the Si chip 1 can be prevented from reaching a high temperature.
[0029]
In this way, by suppressing the high temperature of the Si chip 1, the generation of thermal stress due to the difference in the coefficient of thermal expansion of the portion where electrical bonding with the Si chip 1 is generated due to the high temperature of the Si chip 1. Can be further reduced.
[0030]
Further, in the mounting structure of the present embodiment, the bonding member 4 and the heat radiating plate 8 are used as a substrate bonded to the Si chip 1. Since the joining member 4 and the heat radiating plate 8 are made of a material having a thermal expansion coefficient similar to that of Si and Mo and AlN, respectively, thermal stress due to the difference in thermal expansion coefficient from the Si chip 1 is hardly generated. it can. For this reason, it is possible to make it difficult for the connection site to peel off due to thermal stress.
[0031]
However, even if the thermal expansion coefficient of Mo or AlN approximates the thermal expansion coefficient of Si, the thermal stress cannot be completely suppressed. For this reason, in this embodiment, by adopting a sandwich structure in which the Si chip 1 is sandwiched between the joining member 4 and the heat radiating plate 8, it is possible to generate the same thermal stress on the front and back of the Si chip 1 so as to cancel each other. Therefore, it is possible to further suppress the warp due to the bimetal effect caused by the difference in thermal expansion coefficient between the Si chip 1 and the bonding member 4 or the heat radiating plate 8.
[0032]
Next, the mounting process of the large current device in the present embodiment will be described. This mounting process is shown in FIG. 2 and will be described based on this figure.
[0033]
First, an IGBT composed of a plurality of unit cells and an Si chip 1 on which the emitter electrode 2 of the IGBT is formed are prepared, and a lead 3 having a bonding member 4 disposed at the tip position is prepared.
[0034]
The bonding member 4 has a surface facing the Si chip 1. On this surface, projections 4a are formed at positions corresponding to the respective emitter electrodes 2 of the Si chip 1, and Ni / Au plating 5 is applied to the tips of the projections 4a. Thus, by applying Ni plating, the Zn—Sn solder 6 can be easily wetted. Further, not only Ni plating but also Au plating can be used to prevent oxidation of Ni plating.
[0035]
Then, after applying Zn-Sn solder 6 to the tip of each protrusion 4a, the corresponding protrusion 4a and the emitter electrode 2 are aligned so that they correspond to each other, and the lead 3 is mounted on the Si chip 1. To do.
[0036]
Then, heat treatment at a temperature equal to or higher than the eutectic temperature of Zn—Sn, for example, 210 to 250 ° C. is performed to melt the Zn—Sn solder 6. As a result, the Zn—Sn solder 6 wets and spreads on the emitter electrode 2 and the Ni / Au plating 5, and the lead 3 and the Si chip 1 are joined.
[0037]
Thereafter, a heat radiating plate 8 patterned with metal foil wirings 9 and 16 is prepared on the front surface, and the metal foil wiring 9 on the heat radiating plate 8 and the back surface of the Si chip 1 are connected via the solder 10, and the wiring portion 14. Further, the gate electrode 12 formed on the surface side of the Si chip 1 and the metal foil wiring 16 are joined via the solder 15.
[0038]
The joining procedure is that after joining the Si chip 1 and the joining member 4 with the solder material, the Si chip 1 and the heat radiating plate 8 and the Si chip 1 and the wiring portion 14 are joined, but after the Si chip 1 and the heat radiating plate 8 are joined, Even if the Si chip 1 and the bonding member 4 and the Si chip 1 and the wiring portion 14 are bonded, the Si chip 1 and the heat sink 8, the Si chip 1 and the bonding member 4, and the Si chip 1 and the wiring portion 14 are bonded simultaneously. Good.
[0039]
Then, the leads 11 and 17 are connected to the metal foil wirings 9 and 16, the heat sink 7 is fixed on the leads 3 arranged on the surface side of the Si chip 1, and the outer periphery of the heat sinks 7 and 8 is attached to the resin case. The mounting structure shown in this embodiment is completed by enclosing it with 18.
[0040]
(Other embodiments)
In the above embodiment, the bonding member 4 provided at the tip position of the lead 3 and the respective emitter electrodes 2 on the Si chip 1 are electrically connected via the Zn—Sn solder 6. May be used.
[0041]
For example, as shown in FIG. 3, a soft metal 20 is disposed on the surface of the bonding member 4 facing the Si chip 2 at a position corresponding to each emitter electrode 2. As this soft metal 20, for example, Al can be adopted. Then, each emitter electrode 2 and each soft metal 20 are aligned, and the lead 3 is mounted on the Si chip 1. Thereafter, as indicated by the arrows in the figure, the soft metal 20 and the emitter electrode 2 are rubbed together by applying ultrasonic vibrations, so that they can be electrically joined.
[0042]
At this time, if the entire bonded portion is heated to about 360 ° C., the vibration width and vibration speed can be lowered, so that damage to the Si chip 1 due to vibration can be reduced. Further, when the soft metal 20 is formed of Al or the like, both the joining surfaces of the soft metal 20 are covered with an Au film or covered with Au fine powder, thereby making it easier to join the emitter electrode 2 and the joining member 4. You can also.
[0043]
It is also possible to bond the bonding member 4 and the Si chip 1 without forming the protrusion 4 a on the bonding member 4.
[0044]
For example, the emitter electrode provided on the surface of the Si chip can be configured to protrude from the surface of the Si chip, and the bonding member can be soldered using Zn—Sn solder. Further, Au bumps or Cu bumps may be disposed on the Al electrode of the Si chip, and each bump on the Al electrode and the bonding member may be bonded by ultrasonic bonding. Alternatively, after arranging Au bumps or the like on the Al electrode of the Si chip, each bump and the joining member may be joined by pressing the joining member against the Au bump or the like and performing a heat treatment.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a mounting structure of a device for large current in an embodiment of the present invention.
FIG. 2 is a diagram showing a mounting method of the large current device of FIG. 1;
FIG. 3 is a cross-sectional view illustrating a mounting structure of a high-current device in another embodiment.
FIG. 4 is a cross-sectional view showing a conventional mounting structure of a device for large current.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Si chip, 2 ... Emitter electrode 3, 11, 17 ... Lead, 3 ... Joining member, 4a ... Projection part , 5 ... Ni / Au plating, 6, 13 ... Zn-Sn solder, 7, 8 ... Heat sink 9, 16 ... metal foil wiring, 10, 15 ... solder, 12 ... gate electrode, 14 ... wiring part, 18 ... resin case.

Claims (8)

一面側に電極（２）が形成されてなるＳｉにて構成された半導体チップ（１）と、
前記電極上に配置されたバンプ部（６）と、
前記半導体チップのうち前記電極が形成されている面と対向する面を有してなり、前記バンプ部と接合されて、該バンプ部を介して前記電極と電気的に接合された接合部材（４）と、
前記接合部材に接続されたリード（３）と、
前記半導体チップのうち、前記電極が設けられた面の反対側に配置された第１の放熱板（８）とを有して構成され、
前記接合部材と前記第１の放熱板とは、前記半導体チップの材料と熱膨張係数が近似するように、前記接合部材の材料はＭｏ、前記第１の放熱板はＡｌＮで構成され、
前記接合部材と前記第１の放熱板とは同等の厚みで構成されていると共に、前記接合部材のうち、前記バンプ部と接する部位は、突起部（４ａ）となっていることを特徴とする半導体装置の実装構造。 A semiconductor chip (1) made of Si having an electrode (2) formed on one side thereof;
A bump portion (6) disposed on the electrode;
A bonding member (4) having a surface opposite to the surface on which the electrode is formed in the semiconductor chip, bonded to the bump portion, and electrically bonded to the electrode through the bump portion. )When,
A lead (3) connected to the joining member;
Of the semiconductor chip, the first heat dissipation plate (8) disposed on the opposite side of the surface provided with the electrode,
The joining member and the first heat radiating plate are made of Mo, and the first heat radiating plate is made of AlN, so that the thermal expansion coefficient of the material of the semiconductor chip is similar.
The joining member and the first heat radiating plate are configured to have the same thickness, and a portion of the joining member that is in contact with the bump portion is a protrusion (4a). Semiconductor device mounting structure. 前記接合部材を挟んで、前記半導体チップの反対側には、第２の放熱板（７）が配置されていることを特徴とする請求項１に記載の半導体装置の実装構造。Across the junction member, the opposite side of the semiconductor chip, the mounting structure of a semiconductor device according to claim 1, wherein the second heat radiating plate (7) is arranged. 前記第１、第２の放熱板の外周は、枠部材（１８）で囲まれており、前記第１、第２の放熱板及び前記枠部材は、これらの間の液密性が保持されるように組付けられていることを特徴とする請求項２に記載の半導体装置の実装構造。The outer peripheries of the first and second heat radiating plates are surrounded by a frame member (18), and the first and second heat radiating plates and the frame member maintain liquid tightness therebetween. 3. The semiconductor device mounting structure according to claim 2 , wherein the semiconductor device mounting structure is assembled as described above. 前記接合部材のうち前記バンプ部と接する部位には、Ｎｉを含む金属材料が塗布されていることを特徴とする請求項１ないし３のいずれか１つに記載の半導体装置の実装構造。Mounting structure of a semiconductor device according to the portion contacting with the bump portion of the joining member is any one of claims 1 to 3 metal material is characterized in that it is applied including Ni. 前記バンプ部は、Ｚｎを含有するはんだで構成されていることを特徴とする請求項１ないし４のいずれか１つに記載の半導体装置の実装構造。The bump portion, the mounting structure of a semiconductor device according to any one of claims 1 to 4, characterized in that consists of solder containing Zn. 前記半導体チップには、１００Ａ／ｃｍ2以上の電流が流されることを特徴とする請求項１ないし５のいずれか１つに記載の半導体装置の実装構造。Mounting structure of a semiconductor device according to the semiconductor chip is any one of claims 1 to 5, characterized in that 100A / cm 2 or more current flows. 一面側に電極（２）が備えられている半導体チップ（１）の該電極を、バンプ部（６）を介してリード（３）に電気的に接合する半導体装置の実装方法において、
一面側に電極が備えられたＳｉにて構成される半導体チップを用意する工程と、
前記半導体チップのうち前記電極が形成されている面と対向する面を有すると共に前記半導体チップと熱膨張係数が近似する材質で構成された接合部材（４）を備えたリード（３）を用意する工程と、
前記電極と前記接合部材の間に前記バンプ部を配置したのち、該バンプ部を介して前記電極と前記接合部材とを接合する工程と、
前記半導体チップのうち前記電極が形成された面の反対側に、前記半導体チップと熱膨張係数が近似するＡｌＮにて構成され、かつ、前記接合部材と同等の厚みを有して構成されてなる放熱板（８）を配置する工程と、を含み、
前記接合部材のうち前記バンプ部と接する部位を突起部（４ａ）とすることを特徴とする半導体装置の実装方法。In the mounting method of the semiconductor device, in which the electrode of the semiconductor chip (1) provided with the electrode (2) on one side is electrically joined to the lead (3) through the bump part (6),
Preparing a semiconductor chip composed of Si with electrodes provided on one side;
A lead (3) having a surface facing the surface on which the electrode is formed in the semiconductor chip and including a joining member (4) made of a material whose thermal expansion coefficient approximates that of the semiconductor chip is prepared. Process,
After disposing the bump portion between the electrode and the bonding member, bonding the electrode and the bonding member through the bump portion;
The semiconductor chip is made of AlN whose thermal expansion coefficient is similar to that of the semiconductor chip, on the opposite side of the surface on which the electrodes are formed, and has the same thickness as the bonding member. Arranging the heat sink (8) ,
A method of mounting a semiconductor device, wherein a portion of the bonding member that contacts the bump is a protrusion (4a). 前記電極と前記接合部材との接合工程は、前記半導体チップ上に前記接合部材を備えたリードを搭載し、前記接合部材を超音波振動させることによって行なうことを特徴とする請求項７に記載の半導体装置の実装方法。Bonding process of the bonding member and the electrode is equipped with a lead provided with the joint member on said semiconductor chip, according to the joining member to claim 7, characterized in that done by ultrasonic vibration Semiconductor device mounting method.
JP15574599A 1999-06-02 1999-06-02 Mounting structure and mounting method of semiconductor device Expired - Fee Related JP4023032B2 (en)

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