JP2009147123A - Semiconductor device, and manufacturing method therefor - Google Patents

Semiconductor device, and manufacturing method therefor Download PDF

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JP2009147123A
JP2009147123A JP2007323128A JP2007323128A JP2009147123A JP 2009147123 A JP2009147123 A JP 2009147123A JP 2007323128 A JP2007323128 A JP 2007323128A JP 2007323128 A JP2007323128 A JP 2007323128A JP 2009147123 A JP2009147123 A JP 2009147123A
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solder
semiconductor device
surface electrode
lead
electrode
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Yoshinari Ikeda
良成 池田
Harutaka Taniguchi
春隆 谷口
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/37147—Copper [Cu] as principal constituent
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    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents damages and destruction to an aluminum electrode, when jointing a metal component, such as, a lead frame or a heat spreader thereto. <P>SOLUTION: The aluminum film 11 is formed as a surface electrode 13 of a semiconductor element 10, and a nickel film 12 is formed on its upper surface as a metal protective film. A lead frame 21 is jointed on the nickel film 12 of the surface electrode 13 via a lead-free solder 22. The total surface of the aluminum film 11 of the surface electrode 13 is covered by the nickel film 12 formed thinner than the lead-free solder 22. The cross-sectional shape of the outer peripheral part of the lead-free solder 22 is formed into a semicircular shape (bent fillet shape 23), bundled inwardly in an intermediate part in its thickness direction. An end of the surface electrode 13 of the semiconductor element 10 is formed up to an outside position by a distance (d) from an outer peripheral end of the lead-free solder 22 used as a junction part to the lead frame 21. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体素子の表面電極に電気的配線あるいは放熱部材としての金属部品を接合した半導体装置及びその製造方法に関し、とくにＩＧＢＴモジュールなど、縦型半導体素子を使用するパワー半導体素子を組み込んで構成された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device in which electrical wiring or a metal part as a heat radiating member is joined to a surface electrode of a semiconductor element and a method for manufacturing the same, and more particularly to a power semiconductor element using a vertical semiconductor element such as an IGBT module. The present invention relates to a semiconductor device and a manufacturing method thereof.

縦型半導体素子は、半導体基板の表裏主面にそれぞれ電極が配置され、電流が半導体基板内部を上下方向に流れるものであって、大電流用途に適した構造の半導体チップとして知られている。この種の縦型半導体素子は、現状では、高い熱伝導性が要求されるＩＧＢＴモジュールなどに組み込まれた大容量半導体装置（パワーデバイス）として多用されている。   A vertical semiconductor element is known as a semiconductor chip having a structure suitable for a large current application, in which electrodes are arranged on the front and back main surfaces of a semiconductor substrate and current flows in the vertical direction inside the semiconductor substrate. At present, this type of vertical semiconductor element is widely used as a large-capacity semiconductor device (power device) incorporated in an IGBT module or the like that requires high thermal conductivity.

図６は、従来のパワーデバイスの一例をその断面構成によって示す断面図である。
パワー半導体モジュール１００には、セラミクス基板１３１の表面で所定の電気回路パターンを構成する導体層１３２と、その裏面で裏銅箔を構成する導体層１３３が形成されたセラミクス絶縁板（ＤＢＣ基板）１３０の上に、それぞれはんだ層１２０を介して２枚の半導体チップ１１０が接合されている。また、セラミクス絶縁板１３０の半導体チップ１１０との接合面とは反対の面に、はんだ層１２１を介して銅ベース１４０が接合されている。さらに、銅ベース１４０には、セラミクス絶縁板１３０との接合面とは反対の面にサーマルコンパウンド１５０を介して冷却フィン１６０が接合されている。冷却フィン１６０は、サーマルコンパウンド１５０により銅ベース１４０との間で密着して、両者の熱伝導を良好にして、パワー半導体モジュール１００で発生する熱を放散する機能を果たしている。 FIG. 6 is a cross-sectional view showing an example of a conventional power device by its cross-sectional configuration.
In the power semiconductor module 100, a ceramic insulating plate (DBC substrate) 130 in which a conductor layer 132 constituting a predetermined electric circuit pattern on the front surface of the ceramic substrate 131 and a conductor layer 133 constituting a back copper foil on the back surface is formed. Two semiconductor chips 110 are joined to each other via a solder layer 120. Further, the copper base 140 is bonded to the surface of the ceramic insulating plate 130 opposite to the bonding surface with the semiconductor chip 110 via the solder layer 121. Further, the cooling fin 160 is joined to the copper base 140 via a thermal compound 150 on the surface opposite to the joint surface with the ceramic insulating plate 130. The cooling fin 160 is in close contact with the copper base 140 by the thermal compound 150 to improve the heat conduction between the two and to dissipate heat generated in the power semiconductor module 100.

セラミクス基板１３１には、たとえばアルミナ（Ａｌ2Ｏ3）が用いられる。また、セラミクス基板１３１に接合されている導体層１３２，１３３には、銅（Ｃｕ）やアルミニウム（Ａｌ：以下、アルミと略称する。）などが用いられる。導体層１３２の電気回路パターンは、エッチングなどにより形成される。 For example, alumina (Al 2 O 3 ) is used for the ceramic substrate 131. For the conductor layers 132 and 133 bonded to the ceramic substrate 131, copper (Cu), aluminum (Al: hereinafter abbreviated as aluminum), or the like is used. The electric circuit pattern of the conductor layer 132 is formed by etching or the like.

ここで、半導体チップ１１０をセラミクス絶縁板１３０の電気回路パターン（導体層１３２）に接合するはんだ層１２０や、裏銅箔を構成する導体層１３３と銅ベース１４０とを接合するはんだ層１２０，１２１には、板はんだやクリームはんだが利用され、それらが一定の接合層厚さを確保するように組立てられている。なお、図６のパワー半導体モジュール１００には、樹脂ケース、外部端子、ワイヤボンディングなどは示されていない。   Here, the solder layer 120 for joining the semiconductor chip 110 to the electrical circuit pattern (conductor layer 132) of the ceramic insulating plate 130, or the solder layers 120, 121 for joining the conductor layer 133 constituting the back copper foil and the copper base 140 are joined. In this case, plate solder or cream solder is used, and they are assembled so as to ensure a constant thickness of the bonding layer. Note that the power semiconductor module 100 in FIG. 6 does not show a resin case, an external terminal, wire bonding, or the like.

こうしたパワーデバイスのシリコン基板（半導体チップ１１０）は、従来から、その裏面側にはんだ接合ができるような金属電極膜が被着されている。また、表面（上面）側の金属電極はアルミ電極膜が成膜され、ワイヤボンディングにより外部接続端子と接続されるものが一般的であった。最近では、半導体素子の表面側の電気配線として、ワイヤボンディングに代えて、たとえばリードフレームを使用するパワーデバイスも提案されている。   Conventionally, the silicon substrate (semiconductor chip 110) of such a power device has been coated with a metal electrode film that can be soldered on the back side thereof. Further, the metal electrode on the surface (upper surface) side is generally formed of an aluminum electrode film and connected to an external connection terminal by wire bonding. Recently, a power device using, for example, a lead frame instead of wire bonding has been proposed as the electrical wiring on the surface side of the semiconductor element.

図７は、パワー半導体モジュールの構造を示す断面図である。
このパワー半導体モジュール２００には、複数の発熱性の半導体素子２１０（ＩＧＢＴモジュール）が、はんだ層２２０を介して、長方形板状の絶縁基板２３１の表面に形成された回路パターン２３２の所定位置に接合されている。この図７では、複数の半導体素子２１０の一つだけが表示されている。 FIG. 7 is a cross-sectional view showing the structure of the power semiconductor module.
In this power semiconductor module 200, a plurality of exothermic semiconductor elements 210 (IGBT modules) are bonded to predetermined positions of a circuit pattern 232 formed on the surface of a rectangular plate-like insulating substrate 231 via a solder layer 220. Has been. In FIG. 7, only one of the plurality of semiconductor elements 210 is displayed.

絶縁基板２３１の裏面では、導体層２３３がこの絶縁基板２３１よりも大きな長方形板状の銅板からなるヒートシンク２６０にはんだ層２２１を介して接合され、このヒートシンク２６０の上端縁に沿って半導体素子２１０を取り囲むように、樹脂成形されたケース２６１が接着されている。ケース２６１の内壁には外部接続端子として、エミッタ用端子２５１やコレクタ用端子２５２等が設けられており、それぞれ複数本のアルミワイヤ２４１，２４２等を介して絶縁基板２３１上の各回路パターン２３２に電気的に接続されている。そして、絶縁基板２３１と反対側に形成された半導体素子２１０の表面電極には、はんだ層２２２を介して、低電気抵抗率で高熱伝導率を有する銅からなる長方形板状の高熱伝導体２４０が接合されている。この高熱伝導体２４０は、二股のリードフレーム（電気伝導体）として構成している。   On the back surface of the insulating substrate 231, the conductor layer 233 is bonded to a heat sink 260 made of a rectangular copper plate larger than the insulating substrate 231 via the solder layer 221, and the semiconductor element 210 is connected along the upper edge of the heat sink 260. A resin-molded case 261 is adhered so as to surround it. On the inner wall of the case 261, an emitter terminal 251 and a collector terminal 252 are provided as external connection terminals, and each circuit pattern 232 on the insulating substrate 231 is provided via a plurality of aluminum wires 241 and 242, respectively. Electrically connected. The surface electrode of the semiconductor element 210 formed on the side opposite to the insulating substrate 231 has a rectangular plate-shaped high thermal conductor 240 made of copper having low electrical resistivity and high thermal conductivity via the solder layer 222. It is joined. The high thermal conductor 240 is configured as a bifurcated lead frame (electrical conductor).

すなわち、高熱伝導体２４０は半導体素子２１０の表面電極と接続される本体と、その側方に、はんだ層２２３を介して絶縁基板２３１の回路パターン２３２に電気的に接続されるリードフレーム部とを有している。この本体とリードフレーム部とは、その上端縁が架橋部によって接続されている。   That is, the high thermal conductor 240 has a main body connected to the surface electrode of the semiconductor element 210 and a lead frame portion electrically connected to the circuit pattern 232 of the insulating substrate 231 through the solder layer 223 on the side thereof. Have. The upper end edge of the main body and the lead frame portion is connected by a bridging portion.

この高熱伝導体２４０では、その本体側が半導体素子２１０の表面に形成されたエミッタ電極（図示せず）に接続され、そのリードフレーム部が絶縁基板２３１の回路パターン２３２に接続される。さらにエミッタ電流を絶縁基板２３１からエミッタ用端子２５１側に流すべく、アルミワイヤ２４１の一端がエミッタ用端子２５１にボンディングされ、他端が回路パターン２３２に接続されている。半導体素子２１０の裏面にはコレクタ電極が形成されており、はんだ層２２０を介して絶縁基板２３１の回路パターン２３２に接続されている。   In the high thermal conductor 240, the main body side is connected to an emitter electrode (not shown) formed on the surface of the semiconductor element 210, and the lead frame portion is connected to the circuit pattern 232 of the insulating substrate 231. Further, one end of the aluminum wire 241 is bonded to the emitter terminal 251 and the other end is connected to the circuit pattern 232 so that an emitter current flows from the insulating substrate 231 to the emitter terminal 251 side. A collector electrode is formed on the back surface of the semiconductor element 210 and is connected to the circuit pattern 232 of the insulating substrate 231 through the solder layer 220.

また、半導体素子２１０の表面にはゲート電極も形成されており、このゲート電極と回路パターン２３２とをつなぐアルミワイヤ２４３がボンディングされている。このゲート電極と電気的に接続される回路パターン２３２からは、さらにアルミワイヤ２４４が延出されており、その先端がケース２６１の内壁に設けられた図示しないゲート用端子に接続されている。   A gate electrode is also formed on the surface of the semiconductor element 210, and an aluminum wire 243 that connects the gate electrode and the circuit pattern 232 is bonded. An aluminum wire 244 is further extended from the circuit pattern 232 electrically connected to the gate electrode, and the tip thereof is connected to a gate terminal (not shown) provided on the inner wall of the case 261.

このように、パワー半導体モジュール２００は各アルミワイヤ２４１〜２４４によって電気配線が形成されている。さらに、これら絶縁基板２３１、半導体素子２１０、高熱伝導体２４０および各アルミワイヤ２４１〜２４４を水分、湿気、塵などから保護するために、ケース２６１内はゲル２７０で封止されている。   In this way, the power semiconductor module 200 has electrical wiring formed by the aluminum wires 241 to 244. Further, in order to protect the insulating substrate 231, the semiconductor element 210, the high thermal conductor 240 and the aluminum wires 241 to 244 from moisture, moisture, dust, etc., the inside of the case 261 is sealed with a gel 270.

こうしたリードフレーム（高熱伝導体２４０）を使用するパワーデバイスでは、環境に配慮する観点から、半導体素子２１０を接着する際のはんだ層２２０〜２２３として、鉛（Ｐｂ）フリー組成の錫−銀（Ｓｎ−Ａｇ）系はんだ（鉛フリーはんだ）等が使用されるようになってきた。鉛フリーはんだを使用したパワー半導体モジュール２００は、所謂パワーサイクル試験と呼ばれている断続通電試験を行うことによって、半導体素子２１０の面内で、より高温になる半導体素子２１０中央部の下のはんだ層２２０が劣化し、縦方向に割れを生じることが明らかになっている（非特許文献１参照）。   In a power device using such a lead frame (high thermal conductor 240), from the viewpoint of consideration for the environment, as a solder layer 220 to 223 when bonding the semiconductor element 210, tin-silver (Sn) having a lead (Pb) -free composition is used. -Ag) type solder (lead-free solder) has come to be used. The power semiconductor module 200 using lead-free solder is subjected to an intermittent energization test called a so-called power cycle test, so that the solder under the central portion of the semiconductor element 210 becomes higher in the plane of the semiconductor element 210. It has been revealed that the layer 220 deteriorates and cracks in the vertical direction (see Non-Patent Document 1).

非特許文献１では、パワー半導体モジュールの信頼性において最も重要視されるパワーサイクル信頼性について、寿命向上のための設計技術が紹介されている。シリコンチップ接合部に鉛基はんだを用いると、ＩＧＢＴモジュールの実使用温度域でのパワーサイクル寿命は、はんだ接合部の寿命が支配的である。そこで、はんだ接合部寿命の改善に向けて、高強度で濡れ性に優れたＳｎ−Ａｇ系の鉛フリーはんだ材料が新たに開発されている。また、シリコンチップ接合部に新開発のＳｎ−Ａｇ系の鉛フリーはんだを適用することで、パワーサイクル寿命の向上が達成できる。さらに、その破壊メカニズムが明らかにされている。   Non-Patent Document 1 introduces a design technique for improving the life of power cycle reliability, which is regarded as most important in the reliability of power semiconductor modules. When lead-based solder is used for the silicon chip joint, the life of the solder joint is dominant in the power cycle life in the actual use temperature range of the IGBT module. Therefore, a Sn-Ag-based lead-free solder material having high strength and excellent wettability has been newly developed to improve the solder joint life. Further, by applying a newly developed Sn-Ag-based lead-free solder to the silicon chip joint, an improvement in power cycle life can be achieved. Furthermore, the destruction mechanism has been clarified.

図８は、鉛フリーはんだによる表面電極とリードフレームの接続部分を示す拡大断面図である。
半導体素子２１０の表面には、アルミ電極２１１が成膜されており、さらにその上面にニッケル／金（Ｎｉ／Ａｕ）層２１２が無電解めっき処理によって施されている。そして、リードフレーム２４０の一端と半導体素子２１０の表面のアルミ電極２１１との接合には、はんだ層２２２が用いられる。 FIG. 8 is an enlarged cross-sectional view showing a connection portion between the surface electrode and the lead frame using lead-free solder.
An aluminum electrode 211 is formed on the surface of the semiconductor element 210, and a nickel / gold (Ni / Au) layer 212 is applied to the upper surface thereof by electroless plating. A solder layer 222 is used to join one end of the lead frame 240 and the aluminum electrode 211 on the surface of the semiconductor element 210.

こうしたリードフレームなどの導体をはんだ接合層によって半導体素子の表面電極に面接合する半導体装置では、半導体素子とリードフレームとの線膨張係数差に起因してはんだ接合層に発生する熱応力と歪みを低減することによって、半導体素子とリードフレームとの接合の信頼性を高める必要がある（例えば、特許文献１参照）。この特許文献１の発明では、リードフレームの表面に無電界めっきによるニッケル膜を形成している。   In a semiconductor device in which a conductor such as a lead frame is surface bonded to a surface electrode of a semiconductor element by a solder bonding layer, thermal stress and strain generated in the solder bonding layer due to a difference in linear expansion coefficient between the semiconductor element and the lead frame are reduced. It is necessary to increase the reliability of bonding between the semiconductor element and the lead frame by reducing the number (for example, see Patent Document 1). In the invention of Patent Document 1, a nickel film is formed by electroless plating on the surface of a lead frame.

また、別の半導体装置では、エミッタ電極およびゲート電極を、アルミ電極と無電解ニッケル／金メッキ膜である金属電極との積層膜として構成するようにしている（例えば、特許文献２参照）。こうした金属電極は、アルミ電極の表面側からニッケルメッキ層、金メッキ層が順次無電解メッキにより形成され積層されてなる膜、すなわち無電解ニッケル／金メッキ膜として、ニッケルメッキ層の厚さは５μｍ程度、金メッキ層の厚さは０．１μｍ程度にすることができる。
特開２００５−１２９８８６号公報（段落番号〔００３６〕〜〔００４４〕、図１など） 特開２００５−１９８３０号公報（段落番号〔００４１〕〜〔００５６〕、図２など） 富士時報Ｖｏｌ．７４ Ｎｏ．２ ２００１年 両角 朗・山田 克己・宮坂 忠志「パワー半導体モジュールにおける信頼性設計技術」（ｐｐ．１４５〜１４８） In another semiconductor device, the emitter electrode and the gate electrode are configured as a laminated film of an aluminum electrode and a metal electrode that is an electroless nickel / gold plating film (see, for example, Patent Document 2). Such a metal electrode is a film in which a nickel plating layer and a gold plating layer are sequentially formed by electroless plating from the surface side of the aluminum electrode, that is, as an electroless nickel / gold plating film, the thickness of the nickel plating layer is about 5 μm, The thickness of the gold plating layer can be about 0.1 μm.
Japanese Patent Laying-Open No. 2005-129886 (paragraph numbers [0036] to [0044], FIG. 1, etc.) Japanese Patent Laying-Open No. 2005-19830 (paragraph numbers [0041] to [0056], FIG. 2 etc.) Fuji Jiho Vol. 74 No. 2 2001 Akira Ryokaku, Katsumi Yamada, Tadashi Miyasaka “Reliability Design Technology in Power Semiconductor Modules” (pp.145-148)

図７に示すパワー半導体モジュール２００のように、リードフレームを使用するＩＧＢＴモジュールでは、半導体素子２１０の両面にはんだ層２２０，２２２による接合がなされ、上述したパワーサイクル試験では、それらのはんだ層２２０，２２２が劣化することで半導体装置の寿命を極端に短くするだけでなく、表面電極としてのアルミ膜にも損傷が生じるおそれがあった。   As in the power semiconductor module 200 shown in FIG. 7, in an IGBT module using a lead frame, the solder layers 220 and 222 are bonded to both surfaces of the semiconductor element 210. Deterioration of 222 may not only extremely shorten the life of the semiconductor device, but also damage the aluminum film as the surface electrode.

実際に、図８に示すように、半導体素子２１０のアルミ電極２１１とリードフレーム２４０との間では、そのはんだ層２２２の厚さ方向でのフィレット形状が半導体素子２１０のアルミ電極２１１に向かって斜め方向に直線的に広がった形状となっている。そして、ニッケル／金層２１２とはんだ層２２２の端部位置がほぼ一致するアルミ電極２１１部分にはクラック（亀裂）が発生していることが確認されている。これは、ニッケル（２１０００ｋｇｆ／ｍｍ2）に比べてヤング率が小さいアルミ（６０００ｋｇｆ／ｍｍ2）が強度的に弱く、しかもアルミ電極２１１上の厚いはんだ層２２２によって発生する応力がニッケル／金層２１２の端部に集中するために、アルミ電極２１１に亀裂（クラック２１１ａなど）が生じたものと推定される。 Actually, as shown in FIG. 8, between the aluminum electrode 211 of the semiconductor element 210 and the lead frame 240, the fillet shape in the thickness direction of the solder layer 222 is oblique toward the aluminum electrode 211 of the semiconductor element 210. It has a shape that spreads linearly in the direction. It has been confirmed that cracks have occurred in the aluminum electrode 211 portion where the end positions of the nickel / gold layer 212 and the solder layer 222 substantially coincide. This is because aluminum (6000 kgf / mm 2 ), whose Young's modulus is smaller than that of nickel (21000 kgf / mm 2 ), is weak in strength, and the stress generated by the thick solder layer 222 on the aluminum electrode 211 is stressed by the nickel / gold layer 212. It is presumed that a crack (crack 211a, etc.) has occurred in the aluminum electrode 211 due to the concentration at the end of the aluminum electrode 211.

こうしたクラック２１１ａなどがアルミ電極２１１に生じると、パワー半導体装置の表面電極には大きなエミッタ電流などが流れるため、半導体素子２１０が高温となりやすく、アルミ電極２１１とリードフレーム２４０の間で、電気的、機械的、熱的な接続を確保して安定動作を保証することが困難であった。   When such a crack 211a or the like occurs in the aluminum electrode 211, a large emitter current or the like flows through the surface electrode of the power semiconductor device, so that the semiconductor element 210 is likely to be at a high temperature. It was difficult to ensure a stable operation by securing a mechanical and thermal connection.

本発明はこのような点に鑑みてなされたものであり、リードフレームやヒートスプレッダ等の金属部品を接合する場合のアルミ電極の損傷、破壊を防止した半導体装置を提供することを目的とする。   The present invention has been made in view of these points, and an object thereof is to provide a semiconductor device that prevents damage and destruction of an aluminum electrode when metal parts such as a lead frame and a heat spreader are joined.

本発明では、上記問題を解決するために、半導体素子の表面電極に電気的配線あるいは放熱部材としての金属部品を接合した半導体装置において、前記表面電極に前記金属部品を接合するはんだ接合層と、前記表面電極の前記金属部品との接合部分に、前記はんだ接合層の厚みより薄く成膜された金属保護膜と、を備え、前記はんだ接合層が、その厚さ方向の中間部分で内側に括れたフィレット形状をなしていることを特徴とする半導体装置が提供される。   In the present invention, in order to solve the above problem, in a semiconductor device in which a metal component as an electrical wiring or a heat dissipation member is bonded to a surface electrode of a semiconductor element, a solder bonding layer that bonds the metal component to the surface electrode; A metal protective film formed to be thinner than a thickness of the solder joint layer at a joint portion of the surface electrode with the metal component, and the solder joint layer is bound inward at an intermediate portion in the thickness direction. A semiconductor device characterized by having a fillet shape is provided.

この半導体装置は、はんだ接合層をその厚さ方向の中間部分で内側に括れたフィレット形状としたので、表面電極に対するはんだ接合層からの応力集中を抑制して、表面電極の損傷、破壊を防止できる。   This semiconductor device has a fillet shape in which the solder joint layer is confined in the middle in the thickness direction, so that stress concentration from the solder joint layer on the surface electrode is suppressed, preventing damage and destruction of the surface electrode. it can.

ここで、金属保護膜が表面電極上ではんだ接合層の外周端部の外側位置まで成膜されていることが好ましい。両者の端面をずらすことにより、はんだ接合層への応力集中を防ぐことができるからである。   Here, it is preferable that the metal protective film is formed on the surface electrode up to the outer position of the outer peripheral end portion of the solder joint layer. This is because the stress concentration on the solder joint layer can be prevented by shifting the both end faces.

この発明は、さらに半導体素子の表面電極に電気的配線あるいは放熱部材としての金属部品を接合することで構成された半導体装置の製造方法において、前記表面電極上の前記金属部品との接合領域にはんだを配置する工程と、前記表面電極上で前記はんだを囲むように、前記はんだより高い融点の金属ワイヤを配置する工程と、前記金属部品を前記はんだ上に配置した状態でリフロー炉によって加熱して前記はんだを溶融する工程と、前記加熱した溶融はんだを冷却固化することで前記はんだのフィレット部から前記ワイヤを除去する工程と、を有することを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising joining a metal component as a heat dissipating member or an electrical wiring to a surface electrode of a semiconductor element. A step of disposing a metal wire having a melting point higher than that of the solder so as to surround the solder on the surface electrode, and heating by a reflow furnace in a state where the metal component is disposed on the solder. And a step of melting the solder and a step of removing the wire from the fillet portion of the solder by cooling and solidifying the heated molten solder.

こうした製造方法では、はんだ接合層の厚さ方向の中間部分で内側に括れたフィレット形状を容易に形成することができる。   In such a manufacturing method, a fillet shape that is confined inward at an intermediate portion in the thickness direction of the solder joint layer can be easily formed.

本発明の半導体装置及びその製造方法によれば、半導体素子の表面電極にリードフレームやヒートスプレッダ等の金属部品を接合する場合でもアルミ電極の損傷、破壊を容易かつ確実に防止できる。   According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to easily and reliably prevent the aluminum electrode from being damaged or broken even when a metal part such as a lead frame or a heat spreader is joined to the surface electrode of the semiconductor element.

以下、図面を参照してこの発明の実施の形態について説明する。図１は、実施の形態の半導体装置の電極接合構造を示す断面図、図２は、表面電極上でのリードフレームの接合位置を示す平面図である。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing an electrode bonding structure of a semiconductor device according to the embodiment, and FIG.

図１では、半導体素子１０の表面電極１３としてアルミ膜１１が形成され、その上面には鉛フリーはんだ２２との接合を可能とするニッケル膜１２が金属保護膜として成膜されている。そして、表面電極１３のニッケル膜１２上に鉛フリーはんだ２２を介して、図２に示す位置にリードフレーム２１が接合されている。金属保護膜としては、ニッケル膜１２以外に銅、金、クロム（Ｃｒ）などを含むニッケル組成物からなるニッケルめっき膜、あるいはチタン（Ｔｉ）、チタンナイトライド（ＴｉＮ）などの金属膜であってもよい。なお、図１に示す電極接合構造は、図２のＩ−Ｉ断面に相当する。   In FIG. 1, an aluminum film 11 is formed as a surface electrode 13 of a semiconductor element 10, and a nickel film 12 that can be bonded to a lead-free solder 22 is formed as a metal protective film on the upper surface thereof. A lead frame 21 is joined to the position shown in FIG. 2 via a lead-free solder 22 on the nickel film 12 of the surface electrode 13. The metal protective film is a nickel plating film made of a nickel composition containing copper, gold, chromium (Cr), etc. in addition to the nickel film 12, or a metal film such as titanium (Ti), titanium nitride (TiN), etc. Also good. The electrode bonding structure shown in FIG. 1 corresponds to the II cross section of FIG.

ここで、表面電極１３のアルミ膜１１は、鉛フリーはんだ２２より薄く成膜されたニッケル膜１２によってその全面が覆われている。また、鉛フリーはんだ２２の外周部の断面形状は、その厚さ方向の中間部分で内側に括れた半円形状（以下、「湾曲したフィレット形状２３」という。）となっている。さらに、半導体素子１０の表面電極１３は、その端部がリードフレーム２１との接合部分となる鉛フリーはんだ２２の外周端部から距離「ｄ」だけ外側位置まで形成されている。   Here, the entire surface of the aluminum film 11 of the surface electrode 13 is covered with a nickel film 12 formed thinner than the lead-free solder 22. The cross-sectional shape of the outer peripheral portion of the lead-free solder 22 is a semicircular shape (hereinafter, referred to as “curved fillet shape 23”) that is bound inward at an intermediate portion in the thickness direction. Further, the surface electrode 13 of the semiconductor element 10 is formed from the outer peripheral end portion of the lead-free solder 22 whose end portion is a joint portion with the lead frame 21 to the outer position by a distance “d”.

このように、半導体素子１０の表面電極１３に接合して電気的配線として用いられるリードフレーム２１には、銅などの導体で製作された金属部品が用いられ、それらは互いに鉛フリーはんだ２２によって接合され、その厚さ方向の中間部分で内側に括れた、湾曲したフィレット形状２３をなしている。そして、ニッケル膜１２の端部を鉛フリーはんだ２２の外周端部より距離「ｄ」だけ外側まで形成したことによって、鉛フリーはんだ２２の濡れ広がりの端部がニッケル膜１２の内側で止まっている。この距離「ｄ」は、鉛フリーはんだ２２の厚さと等しいか、あるいはそれ以上の大きさ（すなわち、ｄ≧鉛フリーはんだ２２の厚さ）であることが好ましい。一例として、「ｄ」は１００μｍに設定できる。   As described above, the lead frame 21 that is joined to the surface electrode 13 of the semiconductor element 10 and used as an electrical wiring uses metal parts made of a conductor such as copper, which are joined together by lead-free solder 22. Thus, a curved fillet shape 23 is formed which is bound inward at an intermediate portion in the thickness direction. Then, by forming the end of the nickel film 12 to the outside by the distance “d” from the outer peripheral end of the lead-free solder 22, the end of the lead-free solder 22 that has spread out is stopped inside the nickel film 12. . This distance “d” is preferably equal to or greater than the thickness of the lead-free solder 22 (that is, d ≧ thickness of the lead-free solder 22). As an example, “d” can be set to 100 μm.

これにより、はんだ接合層を構成する鉛フリーはんだ２２の厚さをアルミ膜１１に比べて圧倒的に厚く形成しても、鉛フリーはんだ２２によって発生するアルミ膜１１への応力を大幅に低減できる。また、アルミ膜１１に亀裂が生じた場合でも、ニッケル膜１２の端部への応力集中を抑制することで亀裂の進展が遅くなるから、リードフレーム２１を配線として採用した半導体装置の寿命を長くすることができる。   Thereby, even if the lead-free solder 22 constituting the solder joint layer is formed to be overwhelmingly thicker than the aluminum film 11, the stress on the aluminum film 11 generated by the lead-free solder 22 can be greatly reduced. . Further, even when a crack occurs in the aluminum film 11, the progress of the crack is slowed by suppressing the stress concentration on the end of the nickel film 12, so that the life of the semiconductor device employing the lead frame 21 as the wiring is extended. can do.

つぎに、鉛フリーはんだ２２を湾曲したフィレット形状２３に形成する半導体装置の製造方法について説明する。
図３は、図１に示す電極接合構造の半導体装置の製造方法を示す工程説明図である。 Next, a method for manufacturing a semiconductor device in which the lead-free solder 22 is formed into a curved fillet shape 23 will be described.
FIG. 3 is a process explanatory view showing a method of manufacturing the semiconductor device having the electrode junction structure shown in FIG.

同図（ａ）の半導体装置は、表面電極のニッケル膜１２上に板状のはんだペレット１５が配置され、さらに、断面円形の高融点金属ワイヤ１４がはんだペレット１５を囲むように配置された状態を示している。ここで、高融点金属ワイヤ１４の断面直径は、板状のはんだペレット１５の高さより小さいものが選択される。また、高融点金属ワイヤ１４には、はんだとの濡れ性が悪く、図１に示すような鉛フリーはんだ２２を溶融するためのリフロー温度でも溶融変形しないアルミワイヤなどが使用できる。   In the semiconductor device of FIG. 2A, a plate-like solder pellet 15 is arranged on the nickel film 12 of the surface electrode, and a refractory metal wire 14 having a circular cross section is arranged so as to surround the solder pellet 15. Is shown. Here, the cross-sectional diameter of the refractory metal wire 14 is selected to be smaller than the height of the plate-like solder pellet 15. Further, as the refractory metal wire 14, an aluminum wire that has poor wettability with solder and does not melt and deform even at a reflow temperature for melting the lead-free solder 22 as shown in FIG. 1 can be used.

同図（ｂ）の半導体装置は、リードフレーム２１を半導体素子１０の表面電極と平行に配置した状態を示している。この状態で、リフロー炉によってリフロー温度である３５０℃程度まで加熱すると、はんだペレット１５が溶融して、ニッケル膜１２とリードフレーム２１を一体に結合することができる。   The semiconductor device in FIG. 2B shows a state in which the lead frame 21 is arranged in parallel with the surface electrode of the semiconductor element 10. In this state, when the reflow furnace is heated to about 350 ° C. which is the reflow temperature, the solder pellets 15 are melted, and the nickel film 12 and the lead frame 21 can be bonded together.

同図（ｃ）の半導体装置は、はんだペレット１５が表面電極１３のニッケル膜１２上で溶融した状態を示している。この溶融状態のはんだ１５ａは、外周を囲むように配置された高融点金属ワイヤ１４の内側面によって、そのフィレット形状が規定されて、図１の鉛フリーはんだ２２に相当する断面が湾曲したフィレット形状２３となる。したがって、この半導体装置をリフロー炉から取り出して、溶融状態のはんだ１５ａが冷却固化すれば、そのフィレット部から高融点金属ワイヤ１４が容易に除去できる。   The semiconductor device of FIG. 3C shows a state where the solder pellet 15 is melted on the nickel film 12 of the surface electrode 13. The melted solder 15a has a fillet shape defined by the inner surface of the refractory metal wire 14 disposed so as to surround the outer periphery, and has a curved cross section corresponding to the lead-free solder 22 in FIG. 23. Therefore, if the semiconductor device is taken out from the reflow furnace and the molten solder 15a is cooled and solidified, the refractory metal wire 14 can be easily removed from the fillet portion.

ここでは、板状のはんだペレット１５を使用した例を説明したが、半導体素子１０の表面電極１３のうち、リードフレーム２１との接合領域にクリームはんだ（ペーストはんだ）を塗布しておいてもよい。   Here, an example in which the plate-like solder pellet 15 is used has been described. However, cream solder (paste solder) may be applied to a bonding region with the lead frame 21 in the surface electrode 13 of the semiconductor element 10. .

以上の半導体装置の製造方法では、表面電極１３が成膜されてリードフレーム２１のはんだ接合が可能になった半導体素子１０の上に板状のはんだペレット１５を配置し、その外周をはんだペレット１５の厚みより直径の小さい高融点金属ワイヤ１４で囲い、その上にリードフレーム２１を配置して、はんだリフローを行った。このとき、溶融状態のはんだ１５ａが高融点金属ワイヤ１４と接合しないため、冷却した後の接合層フィレットは厚さ方向の中間部分で内側に括れた形状になる。   In the semiconductor device manufacturing method described above, the plate-like solder pellet 15 is disposed on the semiconductor element 10 on which the surface electrode 13 is formed and the lead frame 21 can be soldered, and the outer periphery of the solder pellet 15 is disposed on the outer periphery. It was surrounded by a refractory metal wire 14 having a diameter smaller than the thickness of the wire, and a lead frame 21 was placed thereon, and solder reflow was performed. At this time, since the molten solder 15a is not bonded to the refractory metal wire 14, the bonding layer fillet after cooling has a shape confined inward at an intermediate portion in the thickness direction.

図４は、はんだ接合層のフィレット形状を示す断面図である。
同図（ａ）のはんだ接合層２２ａは、そのフィレットが断面楕円形で内側に括れた形状となっている。また、同図（ｂ）のはんだ接合層２２ｂは、そのフィレットが直線的に屈曲した断面構成となっている。 FIG. 4 is a cross-sectional view showing the fillet shape of the solder joint layer.
The solder joint layer 22a in FIG. 2A has a shape in which the fillet is elliptical in cross section and is bounded inside. Further, the solder joint layer 22b in FIG. 5B has a cross-sectional configuration in which the fillet is bent linearly.

図１に示す表面電極１３のアルミ膜１１を亀裂から保護するうえでは、図４（ａ）に示す曲線的なフィレットであることが望ましいけれども、厚さ方向の中央部で内側に括れた形状に構成されていればよい。   In order to protect the aluminum film 11 of the surface electrode 13 shown in FIG. 1 from cracks, the curved fillet shown in FIG. 4A is desirable. However, the shape is confined inward at the center in the thickness direction. It only has to be configured.

図５は、図１の半導体装置にパワーサイクル試験を実施した結果を示す図である。
パワーサイクル試験による破壊形態観察では、鉛フリーはんだ２２による接合層を内側に括れたフィレット形状２３にするとともに、ニッケル膜１２の端部を鉛フリーはんだ２２の外周端部より距離「ｄ」（１００μｍ）だけ外側まで形成したことで、アルミ膜１１にはクラック発生は見つからなかった。その一方で、鉛フリーはんだ２２の内部には、ニッケル膜１２に近接する部分でクラック２４が進展していることが確認されている。しかし、鉛フリーはんだ２２の厚さ（約１００μｍ）はアルミ膜１１（５μｍ）に比べて圧倒的に厚く形成されているので、そこに発生する応力は大幅に低減される。そのため、クラック２４の進展は遅く、リードフレーム２１による配線を採用した場合でも、半導体装置のパワーサイクル寿命を十分に確保できる。 FIG. 5 is a diagram illustrating a result of a power cycle test performed on the semiconductor device of FIG.
In the fracture mode observation by the power cycle test, the joint layer made of lead-free solder 22 is formed into a fillet shape 23 bounded inside, and the end of the nickel film 12 is separated from the outer peripheral end of the lead-free solder 22 by a distance “d” (100 μm). ) To the outside, no cracks were found in the aluminum film 11. On the other hand, in the lead-free solder 22, it has been confirmed that a crack 24 has progressed at a portion close to the nickel film 12. However, since the lead-free solder 22 has a thickness (about 100 μm) that is overwhelmingly thicker than that of the aluminum film 11 (5 μm), the stress generated there is greatly reduced. Therefore, the progress of the crack 24 is slow, and even when the wiring by the lead frame 21 is adopted, the power cycle life of the semiconductor device can be sufficiently secured.

なお、半導体素子の表面電極のアルミ膜上にヒートスプレッダなどの放熱部材を鉛フリーはんだで接合した場合も、そのはんだ接合層の外周部のフィレットを内側に括れた形状に形成することによって、半導体装置の寿命を確保できる。   Even when a heat dissipating member such as a heat spreader is joined with lead-free solder on the aluminum film of the surface electrode of the semiconductor element, the semiconductor device is formed by forming the fillet at the outer peripheral portion of the solder joint layer in an inner shape. Can ensure the service life.

以上、本発明の半導体装置では、半導体素子１０の表面電極１３上にはんだ接合層を設けるとき、その厚さ方向の中間部分で内側に括れたフィレット形状を形成するようにしたので、リードフレームやヒートスプレッダ等の金属部品を接合する場合でもアルミ膜１１などの損傷、破壊を容易かつ確実に防止して、電気的、機械的な接続が確保でき、信頼性の高いパワー半導体装置を提供できる。   As described above, in the semiconductor device according to the present invention, when the solder bonding layer is provided on the surface electrode 13 of the semiconductor element 10, the fillet shape is formed in the middle portion in the thickness direction. Even when metal parts such as a heat spreader are joined, damage and destruction of the aluminum film 11 and the like can be prevented easily and reliably, electrical and mechanical connections can be secured, and a highly reliable power semiconductor device can be provided.

実施の形態の半導体装置の電極接合構造を示す断面図である。It is sectional drawing which shows the electrode junction structure of the semiconductor device of embodiment. 表面電極上でのリードフレームの接合位置を示す平面図である。It is a top view which shows the joining position of the lead frame on a surface electrode. 図１に示す電極接合構造の半導体装置の製造方法を示す工程説明図である。It is process explanatory drawing which shows the manufacturing method of the semiconductor device of the electrode junction structure shown in FIG. はんだ接合層のフィレット形状を示す断面図である。It is sectional drawing which shows the fillet shape of a solder joint layer. 図１の半導体装置にパワーサイクル試験を実施した結果を示す図である。It is a figure which shows the result of having implemented the power cycle test to the semiconductor device of FIG. 従来のパワーデバイスの一例をその断面構成によって示す断面図である。It is sectional drawing which shows an example of the conventional power device with the cross-sectional structure. パワー半導体モジュールの構造を示す断面図である。It is sectional drawing which shows the structure of a power semiconductor module. 鉛フリーはんだによる表面電極とリードフレームの接続部分を示す拡大断面図である。It is an expanded sectional view which shows the connection part of the surface electrode and lead frame by lead-free solder.

符号の説明Explanation of symbols

１０ 半導体素子
１１ アルミ膜
１２ ニッケル膜
１３ 表面電極
２１ リードフレーム
２２ 鉛フリーはんだ
２３ 湾曲したフィレット形状
２４ クラック DESCRIPTION OF SYMBOLS 10 Semiconductor element 11 Aluminum film 12 Nickel film 13 Surface electrode 21 Lead frame 22 Lead free solder 23 Curved fillet shape 24 Crack

Claims (6)

半導体素子の表面電極に電気的配線あるいは放熱部材としての金属部品を接合した半導体装置において、
前記表面電極に前記金属部品を接合するはんだ接合層と、
前記表面電極の前記金属部品との接合部分に、前記はんだ接合層の厚みより薄く成膜された金属保護膜と、
を備え、
前記はんだ接合層が、その厚さ方向の中間部分で内側に括れたフィレット形状をなしていることを特徴とする半導体装置。 In a semiconductor device in which a metal part as an electrical wiring or a heat dissipation member is joined to a surface electrode of a semiconductor element,
A solder joint layer for joining the metal part to the surface electrode;
A metal protective film formed to be thinner than the thickness of the solder joint layer on the joint portion of the surface electrode with the metal component;
With
2. A semiconductor device according to claim 1, wherein the solder joint layer has a fillet shape that is confined inward at an intermediate portion in the thickness direction. 前記金属保護膜は、前記表面電極上で前記はんだ接合層の外周端部の外側位置まで成膜されていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the metal protective film is formed on the surface electrode up to an outer position of an outer peripheral end portion of the solder joint layer. 前記金属保護膜は、ニッケル（Ｎｉ）組成物からなるニッケルめっき膜であることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the metal protective film is a nickel plating film made of a nickel (Ni) composition. 前記表面電極は、アルミニウム（Ａｌ）層であることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the surface electrode is an aluminum (Al) layer. 前記はんだ接合層は、鉛フリーはんだによって形成されていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the solder joint layer is formed of lead-free solder. 半導体素子の表面電極に電気的配線あるいは放熱部材としての金属部品を接合することで構成された半導体装置の製造方法において、
前記表面電極上の前記金属部品との接合領域にはんだを配置する工程と、
前記表面電極上で前記はんだを囲むように、前記はんだより高い融点の金属ワイヤを配置する工程と、
前記金属部品を前記はんだ上に配置した状態でリフロー炉によって加熱して前記はんだを溶融する工程と、
前記加熱した溶融はんだを冷却固化した後、前記はんだのフィレット部から前記金属ワイヤを除去する工程と、
を有することを特徴とする半導体装置の製造方法。 In a method for manufacturing a semiconductor device configured by bonding a metal part as an electrical wiring or a heat dissipation member to a surface electrode of a semiconductor element,
Placing solder in a joint region with the metal part on the surface electrode;
Arranging a metal wire having a melting point higher than that of the solder so as to surround the solder on the surface electrode;
A step of melting the solder by heating with a reflow furnace in a state where the metal part is disposed on the solder;
After cooling and solidifying the heated molten solder, removing the metal wire from the fillet portion of the solder;
A method for manufacturing a semiconductor device, comprising:
JP2007323128A 2007-12-14 2007-12-14 Semiconductor device, and manufacturing method therefor Pending JP2009147123A (en)

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Cited By (5)

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Publication number Priority date Publication date Assignee Title
JP2012227356A (en) * 2011-04-20 2012-11-15 Showa Denko Kk Laminated material for insulating substrate
DE102013208350A1 (en) 2012-05-08 2013-11-14 Showa Denko K.K. MANUFACTURING PROCESS FOR A COOLER
EP2803480A2 (en) 2013-05-17 2014-11-19 Showa Denko K.K. Production method of multilayer clad material
US8987895B2 (en) 2010-11-08 2015-03-24 Showa Denko K.K. Clad material for insulating substrates
WO2024040448A1 (en) * 2022-08-23 2024-02-29 京东方科技集团股份有限公司 Circuit board, preparation method, functional backplane, backlight module, and display panel

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987895B2 (en) 2010-11-08 2015-03-24 Showa Denko K.K. Clad material for insulating substrates
JP2012227356A (en) * 2011-04-20 2012-11-15 Showa Denko Kk Laminated material for insulating substrate
DE102013208350A1 (en) 2012-05-08 2013-11-14 Showa Denko K.K. MANUFACTURING PROCESS FOR A COOLER
US8772926B2 (en) 2012-05-08 2014-07-08 Showa Denko K.K. Production method of cooler
EP2803480A2 (en) 2013-05-17 2014-11-19 Showa Denko K.K. Production method of multilayer clad material
WO2024040448A1 (en) * 2022-08-23 2024-02-29 京东方科技集团股份有限公司 Circuit board, preparation method, functional backplane, backlight module, and display panel

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