CN218351473U - Reverse conduction voltage drop SiC MOSFET device - Google Patents
Reverse conduction voltage drop SiC MOSFET device Download PDFInfo
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- CN218351473U CN218351473U CN202221230477.5U CN202221230477U CN218351473U CN 218351473 U CN218351473 U CN 218351473U CN 202221230477 U CN202221230477 U CN 202221230477U CN 218351473 U CN218351473 U CN 218351473U
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Abstract
The utility model provides a reverse conduction voltage drop SiC MOSFET device, which comprises a cell; the cell comprises an N-type pressure-resistant layer, an N-type buffer in contact with the back surface of the N-type pressure-resistant layer, a substrate in contact with the back surface of the N-type buffer, and a drain metal layer in contact with the back surface of the substrate, wherein the front surface of the N-type pressure-resistant layer is in contact with the base region; the front surface of the unit cell is also provided with n deep grooves for dividing the base region, and the source metal in the deep grooves is contacted with the source metal layer. The shielding area and the communicating area of the utility model are connected to form the electrical contact of the grounding, thereby avoiding the problem caused by the grounding of the terminal area; and the number of the grooves can be adjusted to adjust the density of the grooves, and the reverse conduction voltage drop and the specific conduction resistance of the device can be flexibly adjusted.
Description
Technical Field
The utility model relates to a reverse SiC MOSFET device that switches on pressure drop.
Background
The semiconductor power device is a core component of an electronic power technology, and generally, an electronic power system requires that the power device has the characteristics of on-resistance, high voltage resistance, reverse on-voltage drop, high switching speed, easiness in driving and the like. SiC MOSFETs have significant advantages over silicon-based devices in terms of power density, losses, and heat dissipation due to the inherent advantages of their materials, such as their critical breakdown field strength being about 10 times that of silicon and their thermal conductivity being about 3 times that of silicon. However, the trench gate oxide field strength is too high for off-state withstand voltage due to high critical breakdown field strength (about 3 E6V/cm), which causes a series of reliability problems. The suppression of the electric field in the oxide layer must be considered in the SiC MOSFET cell design. For example, a SiC trench gate power MOSFET device with publication number CN111697077a, currently, the most common and effective method is to provide a grounded P-type electric field shielding region at the bottom of the trench gate. The electric field shielding region is typically grounded through a junction termination. With the increase of chip current, the distance from the cell region to the junction terminal region is increased, which causes the increase of the distributed resistance of the long-distance P-type electric field shielding region, so that the grounding effect is deteriorated, and finally, the increase of the dynamic resistance and the increase of dynamic loss of the SiC MOSFET are caused. Therefore, this scheme may limit the current size of a single chip.
For example, a semiconductor disclosed in CN109427869a has a trench unit on an N-type substrate and a P-type electric field shielding region in the trench, but the P-type electric field shielding region is not electrically connected to a source metal layer, so that the distributed resistance of the long-distance P-type electric field shielding region is increased, and the grounding effect is deteriorated.
In addition, the SiC material has a large forbidden bandwidth characteristic, so that the reverse conduction voltage drop of the integrated anti-parallel PiN diode is about 3V, and the reverse conduction loss of the integrated anti-parallel PiN diode is too high. Therefore, for example, the trench gate VDMOS device integrating the Schottky Diode with the publication number CN103441148B integrates the anti-parallel Schottky Diode with low conduction voltage drop in the same chip, namely the Schottky Barrier Diode, SBD becomes an important development direction of the SiC MOSFET. However, the leakage current of the introduced schottky diode is sharply increased under an off-state strong electric field, thereby increasing off-state loss and reducing breakdown voltage. Therefore, it is necessary to provide a P-type electric field shielding region around the schottky junction to suppress the schottky barrier lowering effect, reduce off-state leakage current, and avoid breakdown voltage drop.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a reverse conduction voltage drop's SiC MOSFET device.
The utility model discloses a following technical scheme can realize.
The utility model provides a reverse conduction voltage drop SiC MOSFET device, which comprises a cell; the cell comprises an N-type pressure-resistant layer, an N-type buffer in contact with the back surface of the N-type pressure-resistant layer, a substrate in contact with the back surface of the N-type buffer, and a drain metal layer in contact with the back surface of the substrate, wherein the front surface of the N-type pressure-resistant layer is in contact with the base region; the cell structure is characterized in that n deep grooves are further processed on the front side of the cell to divide the base region, a first doping region is arranged at the upper end of the base region at the edge of the cell, a first doping region and a second doping region are arranged on the base region between adjacent deep grooves, a shielding region is arranged at the lower end of each deep groove, a polysilicon gate or source metal is filled in each deep groove, a gate dielectric layer is arranged between each polysilicon gate and each deep groove, the bottom of each gate dielectric layer is provided with the shielding region, each shielding region is electrically connected with the source metal layer through a communicating region on the side face of each gate dielectric layer, and the source metal in each deep groove is in contact with the source metal layer.
And a passivation layer covers the upper end of the polysilicon gate.
The number of the n deep grooves is more than 2.
And taking the first deep groove at any edge of the cell as the 1 st deep groove, filling polysilicon gates in the 1 st to the (n-1) th deep grooves, and filling active metal in the nth deep groove.
The substrate and the second doped region are both N-type heavily doped semiconductors, and the first doped region is a P-type heavily doped semiconductor.
One end of each of the first doping region and the base region is in contact with the communicating region, the adjacent first doping region and the adjacent second doping region are in contact, and one end of the second doping region is in contact with the gate dielectric layer.
The shielding region is a P-type electric field shielding region.
The communication area is a P-type electric field communication area.
Further, an N-type current circuit area with the doping concentration higher than that of the voltage-resisting layer is arranged below the P-type base area. The concentration of the N-type current path area is at least twice of that of the voltage-resisting area.
The beneficial effects of the utility model reside in that: the shielding region and the communication region are connected to form grounded electrical contact, so that the problem caused by the need of grounding of the terminal region is avoided; and the number of the grooves can be adjusted to adjust the density of the grooves, and the reverse conduction voltage drop and the specific conduction resistance of the device can be flexibly adjusted.
Drawings
Fig. 1 is a schematic structural diagram of a single-trench gate device of the present invention;
fig. 2 is a schematic structural diagram of the multi-groove gate device of the present invention;
fig. 3 is a schematic structural diagram of the single-trench gate device of the present invention for increasing the N-type current path region;
fig. 4 is a schematic structural diagram of the multi-groove gate device of the present invention for increasing the N-type current path region;
in the figure: the structure comprises a 1-N type voltage-resistant layer, a 2-N type buffer, a 3-substrate, a 4-drain electrode metal layer, a 5-shielding region, a 6-communication region, a 7-base region, a 8-first doping region, a 9-second doping region, a 10-gate dielectric layer, a 11-polysilicon gate, a 12-passivation layer, a 13-source electrode metal layer and a 14-N type current path region.
Detailed Description
The technical solutions of the present invention are further described below, but the scope of protection claimed is not limited to the described ones.
Example 1
The present embodiment provides a reverse turn-on voltage drop SiC mosfet device, which has a structure as shown in fig. 1, and it should be noted that, in order to avoid redundancy of reference numerals, the same reference numerals are used for semiconductor regions of the same type; specifically, the unit cell includes:
1. a reverse conducting voltage drop SiC MOSFET device, the cellular structure of which comprises:
an N-type voltage-resistant layer 1;
the N-type buffer layer 2 is arranged on the lower surface of the N-type voltage-resisting layer, the N-type heavily doped semiconductor substrate 3 is arranged on the lower surface of the N-type buffer layer, and the drain metal 4 is arranged on the lower surface of the N-type heavily doped semiconductor;
a P-type electric field shielding region 5,P type electric field communicating region 6 and a P-type semiconductor base region 7 are arranged in the N-type voltage-resistant layer 1;
the surface of the cell is provided with a first deep groove and a second deep groove; the first deep groove is composed of a gate dielectric layer 10 positioned on the wall of the groove and a polysilicon gate 11 positioned in the groove, and a passivation layer 12 covers the upper surface of the first deep groove; the second deep groove is filled with source metal same as the source metal layer 13; the bottom parts of the first deep groove and the second deep groove are both provided with a P-type electric field shielding region 5, and the P-type electric field shielding region at the bottom part of the first deep groove is electrically connected with a source metal layer 13 on the surface through a P-type electric field communication region 6;
the P-type electric field communication region 6 is in contact with the side wall of the first deep groove and the P-type electric field shielding region 5 at the bottom of the first deep groove, and the upper surface of the P-type electric field communication region is covered with a passivation layer 12;
the P-type electric field communication region 6, the first deep groove and the second deep groove separate the P-type semiconductor base region 7, and a 1 st P-type semiconductor base region sub-region, a 2 nd P-type semiconductor base region sub-region and a 3 rd P-type semiconductor base region sub-region are sequentially formed from left to right;
a 1 st heavily doped P-type semiconductor region 8 is arranged on the upper surface of the 1 st P-type semiconductor base region, and a source metal layer 13 covers the upper surface of the 1 st heavily doped P-type semiconductor region; the 1 st heavily doped P-type semiconductor region 8 is in contact with the P-type electric field communication region 6;
the upper surface of the 2 nd P-type semiconductor base region is provided with a 1 st heavily doped N-type semiconductor region 9 and a 2 nd heavily doped P-type semiconductor region 8 which are adjacent, the 1 st heavily doped N-type semiconductor region 9 is contacted with the gate medium 10, and the upper surfaces of the two are covered with a source metal layer 13;
the upper surface of the 3 rd P-type semiconductor base region is provided with a 3 rd heavily doped P-type semiconductor region 8, and the upper surface of the 3 rd heavily doped P-type semiconductor region is covered with a source metal layer 13.
The doping concentration of the first doping region and the second doping region is 1e19 cm -3 。
And part of the side wall metal of the source metal layer 13 in the second deep groove is in direct contact with the N-type voltage-withstanding region 1 and forms an N-type Schottky diode.
In the embodiment, the reverse conduction voltage drop SiC MOSFET device forms an antiparallel schottky diode by contacting the source metal in the deep trench with the N-type voltage-withstanding region 1, and is used for reducing the reverse conduction voltage drop of the device; the P-type electric field shielding region 5 shields the electric field intensity of the gate oxide layer and the Schottky junction surface at a lower value, so that the off-state leakage current is maintained at a lower value, and the breakdown voltage of the device is prevented from being reduced, and the P-type electric field shielding region 5 forms grounded electrical contact through an electric field communication region 6, so that the problem of increased dynamic resistance caused by the grounding of a longer junction terminal region is avoided.
Example 2
The present embodiment provides a reverse turn-on voltage drop SiC mosfet device, which has a structure as shown in fig. 2, and specifically, the cell includes:
an N-type voltage-resistant layer 1;
the N-type buffer layer 2 is arranged on the lower surface of the N-type voltage-resistant layer, the N-type heavily doped semiconductor substrate 3 is arranged on the lower surface of the N-type buffer layer, and the drain metal 4 is arranged on the lower surface of the N-type heavily doped semiconductor;
a P-type electric field shielding region 5,P type electric field communication region 6 and a P-type semiconductor base region 7 are arranged in the N-type voltage-resisting layer 1;
the surface of the cell is provided with n deep grooves, wherein n is more than or equal to 2, and the 1 st deep groove and the 2 nd deep groove … … are arranged from left to right in sequence; the 1 st to n-1 th deep grooves adopt the same structure and are composed of gate dielectric layers 10 positioned on the groove walls and polysilicon gates 11 positioned in the grooves, and passivation layers 12 cover the upper surfaces of the deep grooves; the source metal same as the source metal layer 13 is filled in the nth deep groove; the bottom parts of the n deep grooves are provided with P-type electric field shielding regions 5, and the P-type electric field shielding regions at the bottom parts of the ith (i =1,2, … … n-1) deep groove are electrically connected with the source metal layer 13 on the surface through the ith P-type electric field communication region 6;
the ith P-type electric field communication region is contacted with the ith deep groove and the P-type electric field shielding region 5 at the bottom of the ith deep groove, and the upper surface of the ith P-type electric field communication region is covered with a passivation layer 12;
the n-1P-type electric field communication regions and the n deep grooves divide the P-type semiconductor base region 7 to sequentially form a 1 st P-type semiconductor base region sub-region, a 2 nd P-type semiconductor base region sub-region … …, an nth P-type semiconductor base region sub-region and an n +1 th P-type semiconductor sub-region;
a 1 st heavily doped P-type semiconductor region 8 is arranged on the upper surface of the 1 st P-type semiconductor base region, and a source metal layer 13 covers the upper surface of the 1 st heavily doped P-type semiconductor region;
the upper surfaces of the 2 nd to nth P-type semiconductor base region sub-regions are respectively provided with a 1 st to nth-1 heavy doping N-type semiconductor region 9 and a 2 nd to nth heavy doping P-type semiconductor region 8 which are adjacent, the upper surfaces of the two are covered with a source metal layer 13, and the 1 st to nth-1 heavy doping N-type semiconductor regions 9 are contacted with the gate medium 10 of the 1 st to nth grooves respectively;
the 1 st to the n-1 st heavily doped P-type semiconductor regions 8 are respectively contacted with the 1 st to the n-1 st P-type electric field communication regions 6;
the n +1 th heavily doped P-type semiconductor region 8 is arranged on the upper surface of the n +1 th P-type semiconductor base region sub-region, and the source metal layer 13 covers the upper surface of the n +1 th heavily doped P-type semiconductor region.
The source metal layer 13 is located in the nth deep trench, and part of the sidewall metal is in direct contact with the N-type voltage-withstanding region 1 and forms an N-type schottky diode.
In the SiC MOSFET device with reverse conduction voltage drop in this embodiment, the source metal 13 is in contact with the N-type voltage-withstanding region 1 to form an antiparallel schottky diode for reducing the reverse conduction voltage drop of the device; the P-type electric field shielding region 5 shields the electric field intensity of the gate oxide layer and the Schottky junction surface at a lower value, so that the off-state leakage current is maintained at a lower value, and the breakdown voltage of the device is prevented from being reduced; in addition, the channel density can be flexibly adjusted by adjusting the number of the grooves, and the reverse conduction voltage drop and the specific conduction resistance of the device can be further flexibly adjusted.
Example 3
As shown in fig. 3, this embodiment is the same as embodiment 1, except that an N-type current path region 14 is disposed under the P-type base region 7, and the doping concentration of the N-type current path region 14 is at least two times higher than that of the N-type voltage-withstanding region 1.
In addition to the benefits of embodiment 1, the addition of the heavily doped N-type semiconductor layer 14 can reduce the JFET resistance introduced between the two trenches due to the existence of the P-type electric field shielding region and the connection region, and is beneficial to further reducing the trench-to-trench spacing, increasing the channel density, and reducing the channel resistance.
Example 4
As shown in fig. 4, this embodiment is the same as embodiment 1, except that an N-type current path region 14 is disposed under the P-type base region 7, and the doping concentration of the N-type current path region 14 is at least two times higher than that of the N-type voltage-withstanding region 1.
In addition to the benefits of embodiment 1, the addition of the heavily doped N-type semiconductor layer 14 can reduce the JFET resistance introduced between the two trenches due to the existence of the P-type electric field shielding region and the connection region, and is beneficial to further reducing the trench-to-trench spacing, increasing the channel density, and reducing the channel resistance.
Claims (8)
1. A reverse conduction voltage drop SiC MOSFET device is characterized in that: the cell comprises an N-type voltage-resistant layer (1), an N-type buffer (2) contacted with the back surface of the N-type voltage-resistant layer (1), a substrate (3) contacted with the back surface of the N-type buffer (2), and a drain metal layer (4) contacted with the back surface of the substrate (3), wherein the front surface of the N-type voltage-resistant layer (1) is contacted with a base region (7); the cell structure is characterized in that n deep grooves are further processed in the front of the cell to divide the base region (7), a first doping region (8) is arranged at the upper end of the base region (7) at the edge of the cell, a first doping region (8) and a second doping region (9) are arranged on the base region (7) between the adjacent deep grooves, a shielding region (5) is arranged at the lower end of each deep groove, a polycrystalline silicon gate (11) or source metal is filled in each deep groove, a gate dielectric layer (10) is arranged between each polycrystalline silicon gate (11) and each deep groove, the bottom of each gate dielectric layer (10) is provided with the shielding region (5), the shielding region (5) is electrically connected with a source metal layer (13) through a communicating region (6) on the side face of each gate dielectric layer (10), and the source metal in each deep groove is in contact with the source metal layer (13).
2. The reverse conduction voltage drop SiC MOSFET device of claim 1, wherein: and a passivation layer (12) is covered on the upper end of the polysilicon gate (11).
3. The reverse conduction voltage drop SiC MOSFET device of claim 1, wherein: the number of the n deep grooves is more than 2.
4. The reverse conduction voltage drop SiC MOSFET device of claim 3, wherein: and the first deep groove at any edge of the cell is taken as the 1 st deep groove, the 1 st to the (n-1) th deep grooves are filled with a polysilicon gate (11), and the nth deep groove is filled with active electrode metal.
5. The reverse conduction voltage drop SiC MOSFET device of claim 1, wherein: the substrate (3) and the second doped region (9) are N-type heavily doped semiconductors; the first doping region (8) is a P-type heavily doped semiconductor.
6. The reverse conduction voltage drop SiC MOSFET device of claim 1, wherein: one end of each of the first doping region (8) and the base region (7) is in contact with the communicating region (6), the adjacent first doping region (8) and the adjacent second doping region (9) are in contact, and one end of the second doping region (9) is in contact with the gate dielectric layer (10).
7. The reverse conduction voltage drop SiC MOSFET device of claim 1, wherein: the shielding region (5) is a P-type electric field shielding region.
8. The reverse conduction voltage drop SiC MOSFET device of claim 1, wherein: the communication area (6) is a P-type electric field communication area.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221230477.5U CN218351473U (en) | 2022-05-20 | 2022-05-20 | Reverse conduction voltage drop SiC MOSFET device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221230477.5U CN218351473U (en) | 2022-05-20 | 2022-05-20 | Reverse conduction voltage drop SiC MOSFET device |
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| CN218351473U true CN218351473U (en) | 2023-01-20 |
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