JP3420469B2 - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JP3420469B2 JP3420469B2 JP18529397A JP18529397A JP3420469B2 JP 3420469 B2 JP3420469 B2 JP 3420469B2 JP 18529397 A JP18529397 A JP 18529397A JP 18529397 A JP18529397 A JP 18529397A JP 3420469 B2 JP3420469 B2 JP 3420469B2
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- semiconductor element
- electroless nickel
- nickel plating
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は半導体素子を収容す
るための半導体素子収納用パッケージや混成集積回路基
板等に用いられる配線基板に関し、より詳細には半導体
素子がフリップチップ方式により搭載接続される配線基
板に関するものである。
【０００２】
【従来の技術】近年、半導体素子収納用パッケージや混
成集積回路基板等に用いられる配線基板への半導体素子
の搭載方法としては、配線基板の表面に設けた配線導体
と接続する接続パッドに半導体素子の電極を半田や銀ペ
ースト等の導電性接合材を介し直接接続するいわゆるフ
リップチップ方式のボンディングが多用されつつある。
【０００３】このフリップチップボンディング用途の半
導体素子収納用パッケージや混成集積回路基板等に用い
られる配線基板には、一般に酸化アルミニウム質焼結体
等の電気絶縁材料から成る絶縁基体と、該絶縁基体の内
部及び／または表面にタングステン、モリブデン、マン
ガン等の高融点金属から成る配線導体と、前記絶縁基体
の上面に前記配線導体と電気的接続をもって形成され、
タングステン、モリブデン、マンガン等の金属材料から
成る接続パッドとから構成されており、絶縁基体表面の
接続パッドに半導体素子の電極を半田ボール等から成る
導電性接合材を介し接続させることによって半導体素子
が配線基板上に搭載されるとともに半導体素子の各電極
が配線導体に接続されるようになっている。
【０００４】なお、前記接続パッドを形成するタングス
テン、モリブデン、マンガン等の金属材料は半田ボール
等から成る導電性接合材と濡れ性が悪く、接続パッドに
導電性接合材を強固に接合させることができないことか
ら接続パッドの表面には導電性接合材と濡れ性が良い金
めっき層が下地に無電解ニッケルめっき層を介在させて
被着されている。
【０００５】
【発明が解決しようとする課題】しかしながら、この従
来の配線基板においては、接続パッド上に被着させたニ
ッケルめっき層が無電解めっき法で形成されており、該
無電解ニッケルめっき層の表面粗さは中心線平均粗さ
（Ｒａ）でＲａ＜０．４μｍの極めて平滑なものとなっ
ている。そのためこの無電解ニッケルめっき層上に金め
っき層を被着させると無電解ニッケルめっき層と金めっ
き層との密着面積が狭いものとなって両者の密着強度が
弱いものとなり、その結果、接続パッドに半導体素子の
電極を半田ボール等から成る導電性接合材を介して接続
させると金めっき層が無電解ニッケルめっき層より剥離
し、半導体素子の電極を接続パッドを介して所定の配線
導体に電気的接続することができないという欠点を有し
ていた。
【０００６】本発明は上記欠点に鑑み案出されたもの
で、その目的は接続パッド上に被着されている無電解ニ
ッケルめっき層と金めっき層との密着強度を強いものと
し、接続パッドに半導体素子の電極を半田ボール等から
成る導電性接合材を介して接続しても金めっき層が無電
解ニッケルめっき層より剥離することはなく、半導体素
子の電極を接続パッドを介して所定の配線導体に確実、
強固に電気的接続することができる配線基板を提供する
ことにある。
【０００７】
【課題を解決するための手段】本発明は、絶縁基体と、
該絶縁基体の上面から下面にかけて形成されている高融
点金属から成る配線導体と、該配線導体の前記上面に露
出する領域により構成され、表面に無電解ニッケルめっ
き層と金めっき層とが順次被着されている、半導体素子
の電極が導電性接合材を介して接続される接続パッドと
から成る配線基板であって、前記無電解ニッケルめっき
層は、厚みが２．０μｍ〜８．０μｍであるとともに、
その表面の粗さがブラスト処理を施すことによって中心
線平均粗さ（Ｒａ）で０．５μｍ≦Ｒａ≦１．５μｍと
されていることを特徴とするものである。
【０００８】本発明の配線基板によれば、接続パッドに
被着させた厚みが２．０μｍ〜８．０μｍである無電解
ニッケルめっき層の表面を、ブラスト処理を施すことに
よって中心線平均粗さ（Ｒａ）で０．５μｍ≦Ｒａ≦
１．５μｍの範囲に適度に粗らしたことから、無電解ニ
ッケルめっき層と該無電解ニッケルメッキ層上に被着さ
れる金めっき層との密着面積が広いものとなって両者の
密着強度が強くなり、その結果、接続パッドに半導体素
子の電極を半田ボール等から成る導電性接合材を介して
接続しても無電解ニッケルめっき層と金めっき層との間
に剥離が発生することはなく、これによって半導体素子
の電極を接続パッドを介して所定の配線導体に確実、強
固に電気的接続することが可能となる。
【０００９】
【発明の実施の形態】次に本発明を添付図面に基づき詳
細に説明する。図１及び図２は本発明の配線基板を半導
体素子収納用パッケージの絶縁基体に適用した場合の一
実施例を示し、図中、１は絶縁基体、２は蓋体である。
この絶縁基体１と蓋体２とで半導体素子３を収容するた
めの容器４が構成される。
【００１０】前記絶縁基体１は半導体素子３を支持する
支持部材として作用し、上面の略中央部に半導体素子３
が搭載実装される。
【００１１】前記絶縁基体１は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば、酸化アルミニウム質焼結体か
ら成る場合には、酸化アルミニウム、酸化珪素、酸化マ
グネシウム、酸化カルシウム等の原料粉末に適当な有機
バインダー、溶剤等を添加混合して泥漿物を作るととも
に該泥漿物をドクターブレード法やカレンダーロール法
を採用することによってセラミックグリーンシート（セ
ラミック生シート）と成し、しかる後、前記セラミック
グリーンシートに適当な打ち抜き加工を施すとともにこ
れを複数枚積層し、約１６００℃の温度で焼成すること
によって製作される。
【００１２】また前記絶縁基体１はその上面で半導体素
子３が搭載実装される領域から内部を通り下面にかけて
複数の配線導体５が形成してあり、該配線導体５の絶縁
基体１上面に露出する部位には半導体素子３の各電極が
接続され、また絶縁基体１の下面に導出する部位には外
部リード端子６が銀ロウ等のロウ材を介してロウ付けさ
れている。
【００１３】前記配線導体５は半導体素子３の各電極を
外部電気回路に接続される外部リード端子６に接続する
ための導電路として作用し、半導体素子３の各電極を配
線導体５に接続することによって半導体素子３の各電極
は配線導体５及び外部リード端子６を介して外部電気回
路に接続されることとなる。
【００１４】前記配線導体５はタングステン、モリブデ
ン、マンガン等の高融点金属から成り、例えば、タング
ステンやモリブデン等の金属粉末に適当な有機バインダ
ー及び溶剤を添加混合して金属ペーストを作成し、この
金属ペーストを絶縁基体１となるセラミックグリーンシ
ートの上下面及びセラミックグリーンシートに予め形成
しておいた貫通孔内にスクリーン印刷法により所定パタ
ーンに印刷、充填することによって絶縁基体１の上面か
ら内部を通り下面にかけて所定パターンに形成される。
【００１５】また前記配線導体５は図２に示す如く、絶
縁基体１の上面に露出する領域が接続パッド７を構成
し、該接続パッド７には半導体素子３の下面に設けた電
極８が半田ボール等から成る導電性接合材９を介して接
続され、これによって半導体素子３の各電極８が接続パ
ッド７及び導電性接合材９を介して配線導体５に電気的
に接続されることとなる。
【００１６】前記接続パッド７は更にその上面に無電解
ニッケルめっき層１０と金めっき層１１が順次被着され
ており、該無電解ニッケルめっき層１０は金めっき層１
１をタングステンやモリブデン等から成る接続パッド７
に強固に接合させる作用を為し、また金めっき層１１は
半導体素子３の各電極８を導電性接合材９を介して接続
パッド７に強固に接合させる作用を為す。
【００１７】前記無電解ニッケルめっき層１０は、例え
ば、硫酸ニッケル２０〜４０グラム／リットル、コハク
酸ナトリウム４０〜６０グラム／リットル、ホウ酸２５
〜３５グラム／リットル、塩化アンモニウム２５〜３５
グラム／リットル、ジメチルアミンボラン２．５〜４．
５グラム／リットル等から成る無電解ニッケルめっき液
を準備するとともに、接続パッド７の表面を脱脂、酸処
理した後、触媒剤を含有する溶液に浸漬して活性処理を
し、しかる後、接続パッド７を６０〜６５℃に設定され
た前記無電解ニッケルめっき液中に３０〜６０分間浸漬
させることによって接続パッド７の表面に所定厚み（２
μｍ〜８μｍ）に被着される。
【００１８】また前記金めっき層１１は、例えば、水酸
化カリウム２０〜４０グラム／リットル、エチレンジア
ミン四酢酸３０〜５０グラム／リットル、リン酸二水素
カリウム１５〜４５グラム／リットル、シアン化カリウ
ム０．０１〜０．１グラム／〜リットル、シアン化金カ
リウム１〜４グラム／リットル等から成る金めっき液
（液温：８５〜９５℃）を準備し、これに表面に無電解
ニッケルめっき層１０が被着されている接続パッド７を
５〜１５分間浸漬させることによって無電解ニッケルめ
っき層１０上に所定厚み（０．０２μｍ〜０．３μｍ）
に被着される。
【００１９】なお、前記無電解ニッケルめっき層１０は
その厚みが２．０μｍ未満となると接続パッド７に金メ
ッキ層１１を強固に被着させるのが困難になり、また８
μｍを超えると無電解ニッケルめっき層１０を形成する
際に大きな応力が発生するとともにこれが無電解ニッケ
ルめっき層１０の内部に内在し、該内在応力によって接
続パッド７とむ電解ニッケルめっき層１９との密着の信
頼性が大きく低下してしまう傾向にある。従って、前記
無電解ニッケルめっき層１０はその厚みを２．０μｍ〜
８．０μｍの範囲としておくことが好ましい。
【００２０】また、前記金めっき層１１はその厚みが
０．０２μｍ未満となると下地の無電解ニッケルめっき
層１０を完全に被覆することができなくなり、これによ
って無電解ニッケルめっき層１０が酸化を受け、酸化ニ
ッケルを形成して導電性接合材９との接合強度が劣化し
てしまう傾向にあり、また０．３μｍを超えると金めっ
き層１１の一部が導電性接合材９の内部に拡散して導電
性接合材９の機械的強度を低下させ、接続パッド７と半
導体素子３の各電極８との電気的接続の信頼性が劣化し
てしまう傾向にある。従って、前記金めっき層１１はそ
の厚みを０．０２μｍ〜０．３μｍの範囲としておくこ
とが好ましい。
【００２１】更に前記無電解ニッケルめっき層１０はそ
の表面の粗さが中心線平均粗さ（Ｒａ）で０．５μｍ≦
Ｒａ≦１．５μｍの範囲としてあり、表面を適度に粗ら
していることから無電解ニッケルめっき層１０と該無電
解ニッケルめっき層１０上に被着される金めっき層１１
との密着面積が広いものとなって両者の密着強度が強く
なり、その結果、接続パッド７に半導体素子３の各電極
８を半田ボール等から成る導電性接合材９を介して接続
しても無電解ニッケルめっき層１０と金めっき層１１と
の間には剥離が発生することはなく、これによって半導
体素子３の各電極８を接続パッド７を介して所定のメタ
ライズ配線層５に確実、強固に電気的接続することが可
能となる。
【００２２】前記無電解ニッケルめっき層１０の表面粗
さは中心線平均粗さ（Ｒａ）で０．５μｍ＞Ｒａとなる
と無電解ニッケルめっき層１０と金めっき層１１との密
着面積が狭いものとなって両者の密着強度が弱いものと
なり、接続パッド７に半導体素子３の電極８を半田ボー
ル等から成る導電性接合材９を介して接続させると金め
っき層１１が無電解ニッケルめっき層１０より剥離し、
半導体素子３の電極８を接続パッド７を介して所定の配
線導体５に電気的接続することができなくなり、またＲ
ａ＞１．５μｍとなると金めっき層１１の表面が粗くな
り、導電性接合材９を構成する半田ボール等の濡れ性が
阻害されて、金めっき層１１に導電性接合材９を強固に
接合させるのが困難となってしまう。従って、前記無電
解ニッケルめっき層１０の表面粗さは中心線平均粗さ
（Ｒａ）で０．５μｍ≦Ｒａ≦１．５μｍの範囲に特定
される。
【００２３】更に前記無電解ニッケルめっき層１０の表
面粗さを中心線平均粗さ（Ｒａ）で０．５μｍ≦Ｒａ≦
１．５μｍの範囲とするには無電解ニッケルめっき層１
０の表面に＃１５００程度のメディアを２．０〜４．０
ｋｇ／ｃｍ2の圧力で吹きつけする、所謂、ブラスト処
理を施すことによって行われる。
【００２４】また一方、前記絶縁基体１の下面に導出し
ている配線導体５には外部リード端子６が銀ロウ等のロ
ウ材を介して取着されており、該外部リード端子６は半
導体素子３の各電極８を外部電気回路に電気的に接続さ
せる作用を為す。
【００２５】前記外部リード端子６は鉄−ニッケル−コ
バルト合金や鉄−ニッケル合金等の金属材料から成り、
例えば、鉄−ニッケル−コバルト合金等から成るインゴ
ット（塊）に圧延加工法や打ち抜き加工法等、従来周知
の金属加工法を施すことによって所定の形状に形成され
る。
【００２６】前記外部リード端子６の配線導体５への取
着は配線導体５上に外部リード端子６を間に銀ロウ等か
ら成るロウ材の箔を挟んで載置させ、しかる後、これら
を約９００℃の温度に加熱し、前記ロウ材の箔を溶融さ
せることによって行われる。
【００２７】この場合、配線導体５の表面にロウ材に対
し濡れ性が良いニッケルをめっき法により予め１〜２０
μｍの厚みに被着させておくと配線導体５に対する外部
リード端子６のロウ材を介しての取着が強固となる。従
って、外部リード端子６がロウ材を介して取着される配
線導体５の表面にはロウ材に対して濡れ性が良いニッケ
ルをめっき法により１〜２０μｍの厚みに被着させてお
くことが好ましい。また配線導体５に取着された外部リ
ード端子６はその表面に良導電性で、かつ耐蝕性に優れ
るニッケル、金等の金属をめっき法により１〜２０μｍ
の厚みに被着させておくと、外部リード端子６の酸化腐
蝕を有効に防止することができるとともに外部電気回路
との電気的接続を良好となすことができる。従って、前
記外部リード端子６はその表面にニッケル、金等をめっ
き法により１〜２０μｍの厚みに被着させておくことが
好ましい。
【００２８】前記外部リード端子６が取着された絶縁基
体１は更にその上面外周部に椀状をなす蓋体２の下面が
ガラス、樹脂、ロウ材等から成る封止材を介して接合さ
れ、これによって絶縁基体１と蓋体２とから成る容器４
の内部が気密に封止される。
【００２９】前記蓋体２は容器４の内部に半導体素子３
を気密に収容する作用を為し、銅や鉄−ニッケル−コバ
ルト合金、鉄−ニッケル合金等の金属材料、或いは酸化
アルミニウム質焼結体等のセラミック焼結体で形成され
ている。
【００３０】かくして上述の半導体素子収納用パッケー
ジによれば、絶縁基体１上面に半導体素子３を、該半導
体素子３の各電極８を接続パッド７に半田ボール等から
成る導電性接合材９を介し接続させることによって搭載
実装し、しかる後、前記絶縁基体１の上面に椀状の蓋体
２をガラス、樹脂、ロウ材等から成る封止材を介して接
合させ、絶縁基体１と蓋体２とから成る容器４内部に半
導体素子３を気密に収容することによって最終製品とし
ての半導体装置となる。
【００３１】なお、本発明は上述した実施例に限定され
るものではなく、本発明の要旨を逸脱しない範囲であれ
ば種々の変更は可能であり、例えば、上述の実施例では
本発明の配線基板を半導体素子を収容する半導体素子収
納用パッケージに適用した場合を例に挙げて説明した
が、これを半導体素子が搭載される混成集積回路基板に
適用した場合も同様である。
【００３２】
【発明の効果】本発明の配線基板によれば、接続パッド
に被着させた厚みが２．０μｍ〜８．０μｍである無電
解ニッケルめっき層の表面を、ブラスト処理を施すこと
によって中心線平均粗さ（Ｒａ）で０．５μｍ≦Ｒａ≦
１．５μｍの範囲に適度に粗らしたことから、無電解ニ
ッケルめっき層と該無電解ニッケルメッキ層上に被着さ
れる金めっき層との密着面積が広いものとなって両者の
密着強度が強くなり、その結果、接続パッドに半導体素
子の電極を半田ボール等から成る導電性接合材を介して
接続しても無電解ニッケルめっき層と金めっき層との間
に剥離が発生することはなく、これによって半導体素子
の電極を接続パッドを介して所定の配線導体に確実、強
固に電気的接続することが可能となる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device and a wiring board used for a hybrid integrated circuit board, and more particularly to a semiconductor device. The present invention relates to a wiring board on which elements are mounted and connected by a flip chip method. 2. Description of the Related Art In recent years, as a method of mounting a semiconductor element on a wiring board used for a package for housing a semiconductor element, a hybrid integrated circuit board, or the like, a connection pad for connecting to a wiring conductor provided on the surface of the wiring board has In recent years, so-called flip-chip bonding, in which electrodes of a semiconductor element are directly connected via a conductive bonding material such as solder or silver paste, has been widely used. [0003] A wiring substrate used for a package for housing a semiconductor element for flip-chip bonding, a hybrid integrated circuit board, or the like generally includes an insulating base made of an electrically insulating material such as an aluminum oxide sintered body, and an insulating base made of the insulating base. A wiring conductor made of a refractory metal such as tungsten, molybdenum, or manganese inside and / or on the surface, and an electrical connection with the wiring conductor on the upper surface of the insulating base;
A connection pad made of a metal material such as tungsten, molybdenum, and manganese.The semiconductor element is connected to the connection pad on the surface of the insulating base via a conductive bonding material such as a solder ball. Each electrode of the semiconductor element is mounted on a wiring board and connected to a wiring conductor. The metal material such as tungsten, molybdenum, manganese or the like which forms the connection pad has poor wettability with a conductive bonding material such as a solder ball, so that the conductive bonding material is strongly bonded to the connection pad. Since the connection pad cannot be formed, a gold plating layer having good wettability with a conductive bonding material is attached to the surface of the connection pad with an electroless nickel plating layer interposed therebetween. [0005] However, in this conventional wiring board, the nickel plating layer deposited on the connection pad is formed by an electroless plating method. Is extremely smooth with a center line average roughness (Ra) of Ra <0.4 μm. Therefore, when a gold plating layer is applied on this electroless nickel plating layer, the adhesion area between the electroless nickel plating layer and the gold plating layer becomes small, and the adhesion strength between the two becomes weak. When the electrodes of the semiconductor element are connected to each other via a conductive bonding material made of solder balls or the like, the gold plating layer is peeled off from the electroless nickel plating layer, and the electrodes of the semiconductor element are electrically connected to predetermined wiring conductors via connection pads. However, there was a drawback that the connection could not be established. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to increase the adhesion strength between an electroless nickel plating layer and a gold plating layer adhered on a connection pad, and Even when the electrodes of the semiconductor element are connected via a conductive bonding material such as a solder ball, the gold plating layer does not peel off from the electroless nickel plating layer, and the electrodes of the semiconductor element are connected to the predetermined wiring via the connection pads. Secure to conductor,
An object of the present invention is to provide a wiring board capable of firmly connecting electrically. [0007] The present invention provides an insulating substrate,
A wiring conductor made of a refractory metal formed from the upper surface to the lower surface of the insulating base, and a region exposed on the upper surface of the wiring conductor. An electroless nickel plating layer and a gold plating layer are sequentially coated on the surface. A connection board to which an electrode of the semiconductor element is connected via a conductive bonding material, wherein the electroless nickel plating layer has a thickness of 2.0 μm to 8.0 μm. With
The surface is characterized in that the center line average roughness (Ra) is set to 0.5 μm ≦ Ra ≦ 1.5 μm by blasting. According to the wiring board of the present invention, the surface of the electroless nickel plating layer having a thickness of 2.0 μm to 8.0 μm attached to the connection pad is subjected to a blast treatment to obtain a center line average roughness. (Ra) 0.5 μm ≦ Ra ≦
Since it was appropriately roughened in the range of 1.5 μm, the adhesion area between the electroless nickel plating layer and the gold plating layer deposited on the electroless nickel plating layer became large, and the adhesion strength between the two was reduced. As a result, even if the electrodes of the semiconductor element are connected to the connection pads via a conductive bonding material such as a solder ball, no separation occurs between the electroless nickel plating layer and the gold plating layer. This makes it possible to reliably and firmly electrically connect the electrodes of the semiconductor element to predetermined wiring conductors via the connection pads. Next, the present invention will be described in detail with reference to the accompanying drawings. FIGS. 1 and 2 show an embodiment in which the wiring board of the present invention is applied to an insulating base of a package for housing a semiconductor element. In the drawings, reference numeral 1 denotes an insulating base, and 2 denotes a lid.
The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3. The insulating base 1 functions as a support member for supporting the semiconductor element 3, and the semiconductor element 3
Is mounted. The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a glass ceramic sintered body, and the like. When it is made of an aluminum oxide sintered body, an appropriate organic binder, a solvent, etc. are added to and mixed with raw material powders of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. to form a slurry, and the slurry is doctored. A ceramic green sheet (ceramic green sheet) is formed by employing a blade method or a calender roll method. Thereafter, the ceramic green sheet is subjected to an appropriate punching process and a plurality of the green sheets are laminated, and a temperature of about 1600 ° C. It is manufactured by firing. A plurality of wiring conductors 5 are formed on the upper surface of the insulating substrate 1 from the region where the semiconductor element 3 is mounted and mounted on the upper surface to the lower surface through the inside, and the wiring conductors 5 are exposed on the upper surface of the insulating substrate 1. Each electrode of the semiconductor element 3 is connected to the portion, and an external lead terminal 6 is brazed to a portion extending to the lower surface of the insulating base 1 via a brazing material such as silver brazing. The wiring conductor 5 functions as a conductive path for connecting each electrode of the semiconductor element 3 to an external lead terminal 6 connected to an external electric circuit, and connects each electrode of the semiconductor element 3 to the wiring conductor 5. As a result, each electrode of the semiconductor element 3 is connected to an external electric circuit via the wiring conductor 5 and the external lead terminal 6. The wiring conductor 5 is made of a metal having a high melting point, such as tungsten, molybdenum, or manganese. For example, a metal paste such as tungsten or molybdenum is added to an appropriate organic binder and a solvent to form a metal paste. The paste is printed and filled in a predetermined pattern by screen printing into the upper and lower surfaces of the ceramic green sheet to be the insulating substrate 1 and the through holes formed in the ceramic green sheet in advance, so that the paste passes from the upper surface of the insulating substrate 1 to the inside. A predetermined pattern is formed over the lower surface. As shown in FIG. 2, the region of the wiring conductor 5 exposed on the upper surface of the insulating substrate 1 constitutes a connection pad 7, on which an electrode 8 provided on the lower surface of the semiconductor element 3 is soldered. The electrodes 8 of the semiconductor element 3 are electrically connected to the wiring conductors 5 via the connection pads 7 and the conductive bonding material 9. . The connection pad 7 is further provided with an electroless nickel plating layer 10 and a gold plating layer 11 sequentially on the upper surface thereof, and the electroless nickel plating layer 10
1 is a connection pad 7 made of tungsten, molybdenum, etc.
The gold plating layer 11 functions to firmly join the electrodes 8 of the semiconductor element 3 to the connection pads 7 via the conductive bonding material 9. The electroless nickel plating layer 10 is made of, for example, nickel sulfate 20 to 40 g / l, sodium succinate 40 to 60 g / l, boric acid 25
~ 35 g / l, ammonium chloride 25 ~ 35
Grams / liter, dimethylamine borane 2.5-4.
An electroless nickel plating solution of 5 g / liter or the like is prepared, the surface of the connection pad 7 is degreased and acid-treated, and then immersed in a solution containing a catalyst agent to perform an activation treatment. 7 is immersed in the electroless nickel plating solution set at 60 to 65 ° C. for 30 to 60 minutes, so that the surface of the connection pad 7 has a predetermined thickness (2
μm to 8 μm). The gold plating layer 11 may be made of, for example, potassium hydroxide 20 to 40 g / l, ethylenediaminetetraacetic acid 30 to 50 g / l, potassium dihydrogen phosphate 15 to 45 g / l, potassium cyanide 0.01 to 45 g / l. A gold plating solution (liquid temperature: 85 to 95 ° C.) composed of 0.1 g / 〜l, potassium gold cyanide 1４4 g / l, etc. is prepared, and the electroless nickel plating layer 10 is adhered to the surface. A predetermined thickness (0.02 μm to 0.3 μm) is formed on the electroless nickel plating layer 10 by immersing the connection pad 7 that has been formed for 5 to 15 minutes.
Is adhered to. When the thickness of the electroless nickel plating layer 10 is less than 2.0 μm, it becomes difficult to firmly attach the gold plating layer 11 to the connection pad 7.
When the thickness exceeds μm, a large stress is generated when the electroless nickel plating layer 10 is formed, and this stress is present inside the electroless nickel plating layer 10, and the connection stress between the connection pad 7 and the electrolytic nickel plating layer 19 due to the intrinsic stress is generated. Tends to be greatly reduced. Therefore, the electroless nickel plating layer 10 has a thickness of 2.0 μm to
It is preferable to set the thickness in the range of 8.0 μm. If the thickness of the gold plating layer 11 is less than 0.02 μm, the gold plating layer 11 cannot completely cover the underlying electroless nickel plating layer 10, whereby the electroless nickel plating layer 10 is oxidized. , Nickel oxide is formed, and the bonding strength with the conductive bonding material 9 tends to be deteriorated. When the thickness exceeds 0.3 μm, a part of the gold plating layer 11 diffuses into the conductive bonding material 9. Accordingly, the mechanical strength of the conductive bonding material 9 is reduced, and the reliability of the electrical connection between the connection pad 7 and each electrode 8 of the semiconductor element 3 tends to be deteriorated. Therefore, it is preferable that the thickness of the gold plating layer 11 be in the range of 0.02 μm to 0.3 μm. The surface roughness of the electroless nickel plating layer 10 is 0.5 μm ≦ center line average roughness (Ra).
Ra ≦ 1.5 μm, and the surface is appropriately roughened, so that the electroless nickel plating layer 10 and the gold plating layer 11 deposited on the electroless nickel plating layer 10
And the adhesion strength between them is increased, and as a result, even if each electrode 8 of the semiconductor element 3 is connected to the connection pad 7 via the conductive bonding material 9 made of a solder ball or the like. No separation occurs between the electroless nickel plating layer 10 and the gold plating layer 11, so that each electrode 8 of the semiconductor element 3 is securely and firmly attached to the predetermined metallized wiring layer 5 via the connection pad 7. It is possible to make an electrical connection. When the surface roughness of the electroless nickel plating layer 10 is 0.5 μm> Ra in center line average roughness (Ra), the surface area of adhesion between the electroless nickel plating layer 10 and the gold plating layer 11 is small. When the electrode 8 of the semiconductor element 3 is connected to the connection pad 7 via the conductive bonding material 9 composed of a solder ball or the like, the gold plating layer 11 Peel off,
The electrode 8 of the semiconductor element 3 cannot be electrically connected to the predetermined wiring conductor 5 via the connection pad 7, and
When a> 1.5 μm, the surface of the gold plating layer 11 becomes rough, and the wettability of the solder balls and the like constituting the conductive bonding material 9 is hindered, and the conductive bonding material 9 is firmly bonded to the gold plating layer 11. It will be difficult to make it. Therefore, the surface roughness of the electroless nickel plating layer 10 is specified in the range of 0.5 μm ≦ Ra ≦ 1.5 μm in center line average roughness (Ra). Further, the surface roughness of the electroless nickel plating layer 10 is determined by calculating a center line average roughness (Ra) as 0.5 μm ≦ Ra ≦
To make the thickness 1.5 μm, the electroless nickel plating layer 1
No. 1500 media on the surface of 2.0 to 2.0 to 4.0
The spraying is performed by applying a so-called blast treatment at a pressure of kg / cm 2 . On the other hand, an external lead terminal 6 is attached to the wiring conductor 5 extending to the lower surface of the insulating base 1 via a brazing material such as silver brazing, and the external lead terminal 6 is a semiconductor element. The third electrode 8 serves to electrically connect each electrode 8 to an external electric circuit. The external lead terminal 6 is made of a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy.
For example, it is formed into a predetermined shape by subjecting an ingot made of an iron-nickel-cobalt alloy or the like to a conventionally known metal working method such as a rolling method or a punching method. The external lead terminals 6 are attached to the wiring conductor 5 by placing the external lead terminals 6 on the wiring conductor 5 with a brazing material foil made of silver brazing or the like interposed therebetween. This is performed by heating to a temperature of about 900 ° C. to melt the brazing material foil. In this case, nickel having good wettability with respect to the brazing material is previously plated on the surface of the wiring conductor 5 with a plating method.
If it is applied to a thickness of μm, the attachment of the external lead terminal 6 to the wiring conductor 5 via the brazing material becomes strong. Therefore, nickel having good wettability to the brazing material is preferably applied to the surface of the wiring conductor 5 to which the external lead terminals 6 are attached via the brazing material to a thickness of 1 to 20 μm by plating. preferable. The external lead terminals 6 attached to the wiring conductors 5 are plated with a metal such as nickel or gold, which has good conductivity and excellent corrosion resistance, by a plating method to a thickness of 1 to 20 μm.
When it is adhered to the thickness, the external lead terminal 6 can be effectively prevented from being oxidized and corroded, and good electrical connection with an external electric circuit can be achieved. Therefore, it is preferable that nickel, gold or the like is applied to the surface of the external lead terminal 6 by plating so as to have a thickness of 1 to 20 μm. The insulating base 1 to which the external lead terminals 6 are attached is further joined to the outer periphery of the upper surface thereof by a lower surface of a bowl-shaped lid 2 via a sealing material made of glass, resin, brazing material or the like. Thereby, the container 4 comprising the insulating base 1 and the lid 2
Is hermetically sealed. The lid 2 has a semiconductor element 3 inside a container 4.
And is made of a metal material such as copper, an iron-nickel-cobalt alloy, an iron-nickel alloy, or a ceramic sintered body such as an aluminum oxide sintered body. Thus, according to the package for housing a semiconductor element described above, the semiconductor element 3 is provided on the upper surface of the insulating base 1, the electrodes 8 of the semiconductor element 3 are connected to the connection pads 7 via the conductive bonding material 9 made of solder balls or the like. Then, the bowl-shaped lid 2 is joined to the upper surface of the insulating base 1 via a sealing material made of glass, resin, brazing material, or the like. A semiconductor device as a final product is obtained by hermetically housing the semiconductor element 3 in the container 4 composed of The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. Although the case where the substrate is applied to a semiconductor element housing package for housing a semiconductor element has been described as an example, the same applies to a case where the substrate is applied to a hybrid integrated circuit board on which semiconductor elements are mounted. According to the wiring board of the present invention, the surface of the electroless nickel plating layer having a thickness of 2.0 μm to 8.0 μm adhered to the connection pad is subjected to a blast treatment. 0.5 μm ≦ Ra ≦ in centerline average roughness (Ra)
Since it was appropriately roughened in the range of 1.5 μm, the adhesion area between the electroless nickel plating layer and the gold plating layer deposited on the electroless nickel plating layer became large, and the adhesion strength between the two was reduced. As a result, even if the electrodes of the semiconductor element are connected to the connection pads via a conductive bonding material made of solder balls or the like, no separation occurs between the electroless nickel plating layer and the gold plating layer. This makes it possible to reliably and firmly electrically connect the electrodes of the semiconductor element to predetermined wiring conductors via the connection pads.
【図面の簡単な説明】
【図１】本発明の配線基板の実施の形態の一例を示す断
面図である。
【図２】図１の要部拡大断面図である。
【符号の説明】
１・・・・・絶縁基体
２・・・・・蓋体
３・・・・・半導体素子
４・・・・・容器
５・・・・・配線導体
６・・・・・外部リード端子
７・・・・・接続パッド
８・・・・・半導体素子の電極
９・・・・・導電性接合材
１０・・・・無電解ニッケルめっき層
１１・・・・金めっき層BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an example of an embodiment of a wiring board of the present invention. FIG. 2 is an enlarged sectional view of a main part of FIG. [Description of Signs] 1 ... Insulating base 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Wiring conductor 6 ... External lead terminal 7 Connection pad 8 Electrode 9 of semiconductor element Conductive bonding material 10 Electroless nickel plating layer 11 Gold plating layer
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/447 H01L 21/449 H01L 21/60 H01L 21/603 H01L 21/607 H01L 23/12 - 23/15 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/447 H01L 21/449 H01L 21/60 H01L 21/603 H01L 21/607 H01L 23/12-23 / Fifteen
Claims (1)
かけて形成されている高融点金属から成る配線導体と、
該配線導体の前記上面に露出する領域により構成され、
表面に無電解ニッケルめっき層と金めっき層とが順次被
着されている、半導体素子の電極が導電性接合材を介し
て接続される接続パッドとから成る配線基板であって、
前記無電解ニッケルめっき層は、厚みが２．０μｍ〜
８．０μｍであるとともに、その表面の粗さがブラスト
処理を施すことによって中心線平均粗さ（Ｒａ）で０．
５μｍ≦Ｒａ≦１．５μｍとされていることを特徴とす
る配線基板。(57) [Claims] (1) An insulating base and an upper surface to a lower surface of the insulating substrate.
A wiring conductor made of a refractory metal formed over
Is constituted by a region exposed on the upper surface of the wiring conductors,
An electroless nickel plating layer and a gold plating layer are sequentially deposited on the surface, and a wiring board comprising connection pads to which electrodes of a semiconductor element are connected via a conductive bonding material,
The electroless nickel plating layer has a thickness of 2.0 μm or more.
8.0 μm and the surface roughness is blast
By performing the treatment, the center line average roughness (Ra) is set to 0.
Wiring board characterized that you have been a 5μm ≦ Ra ≦ 1.5μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18529397A JP3420469B2 (en) | 1997-07-10 | 1997-07-10 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18529397A JP3420469B2 (en) | 1997-07-10 | 1997-07-10 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1131754A JPH1131754A (en) | 1999-02-02 |
| JP3420469B2 true JP3420469B2 (en) | 2003-06-23 |
Family
ID=16168332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18529397A Expired - Fee Related JP3420469B2 (en) | 1997-07-10 | 1997-07-10 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3420469B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012086724A1 (en) * | 2010-12-24 | 2012-06-28 | 旭硝子株式会社 | Connected substrate, method of manufacturing thereof, element substrate, and light-emitting apparatus |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4075306B2 (en) * | 2000-12-19 | 2008-04-16 | 日立電線株式会社 | Wiring board, LGA type semiconductor device, and method of manufacturing wiring board |
| KR100688755B1 (en) | 2005-03-21 | 2007-03-02 | 삼성전기주식회사 | Method for forming solder ball pad in BGA printed circuit board and BGA printed circuit board manufactured therefrom |
-
1997
- 1997-07-10 JP JP18529397A patent/JP3420469B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012086724A1 (en) * | 2010-12-24 | 2012-06-28 | 旭硝子株式会社 | Connected substrate, method of manufacturing thereof, element substrate, and light-emitting apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1131754A (en) | 1999-02-02 |
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