JP3323607B2 - Method for manufacturing semiconductor memory device - Google Patents
Method for manufacturing semiconductor memory deviceInfo
- Publication number
- JP3323607B2 JP3323607B2 JP28304793A JP28304793A JP3323607B2 JP 3323607 B2 JP3323607 B2 JP 3323607B2 JP 28304793 A JP28304793 A JP 28304793A JP 28304793 A JP28304793 A JP 28304793A JP 3323607 B2 JP3323607 B2 JP 3323607B2
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- JP
- Japan
- Prior art keywords
- dielectric constant
- memory device
- film
- semiconductor memory
- insulating film
- Prior art date
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Description
【０００１】[0001]
【産業上の利用分野】本発明は，DRAM(ダイナミックラ
ンダムアクセスメモリ)等大容量小型の半導体記憶装置
記憶装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-capacity and small-sized semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】Pb(Zr,Ti)O3 (PZT)等の高誘電率誘電体
は，公知の１トランジスタ１キャパシタよりなるDRAM用
メモリセルのキャパシタ用絶縁膜材料，あるいは強誘電
性を用いる不揮発性メモリ用誘電体膜として有用である
ことが知られている。この作製方法については，例えば
アイイーイーイー・インターナショナル・エレクトロン
デバイス・ミーティング・テクニカルダイジェスト1992
年266頁から270頁(IEEEIEDM Technical Digest, pp.226
-270, 1992)の図１に示されているように，セル毎に分
離形成された下部電極上に公知の堆積方法によって高誘
電率誘電体を形成し，しかるのちにプレートと呼ばれる
上部電極を形成する。不揮発性メモリについても，例え
ばジャーナル・オブ・バキュウム・サイエンス・ テク
ノロジーA 1992年第10巻1554頁から1561頁(Journal of
Vacuum Science Technology, A, Vol. 10, pp. 1554 -
1561, 1992)の第１図に示されているように，分離され
た下部電極と上部電極とに挟まれた強誘電体を用いてい
る。2. Description of the Related Art A high dielectric constant dielectric such as Pb (Zr, Ti) O3 (PZT) is known as a material for an insulating film for a capacitor of a DRAM memory cell comprising one transistor and one capacitor, or a nonvolatile material using ferroelectricity. It is known that it is useful as a dielectric film for nonvolatile memory. This manufacturing method is described in, for example, IEE International Electron Device Meeting Technical Digest 1992
Pages 266 to 270 (IEEEIEDM Technical Digest, pp.226)
-270, 1992), a high dielectric constant dielectric is formed by a known deposition method on a lower electrode separately formed for each cell, and then an upper electrode called a plate is formed. Form. For non-volatile memory, for example, see Journal of Vacuum Science Technology A, Vol. 19, 1992, pages 1554 to 1561 (Journal of Vacuum Science Technology A).
Vacuum Science Technology, A, Vol. 10, pp. 1554-
1561, 1992), a ferroelectric material sandwiched between a separated lower electrode and upper electrode is used.
【０００３】[0003]
【発明が解決しようとする課題】以上の従来技術では，
明示的に述べられていないものの，図から明らかに，隣
接するコンデンサとの距離は充分大きく，従って，隣接
電極間分離が問題になる事はなかったと推測される。本
発明の対象である１ギガビットDRAMのような高集積の装
置では，分離幅が0.2μm以下と非常に小さくなるため，
電極や誘電体の膜厚が分離幅と同程度になり，これに伴
った作製上，回路動作上の問題が生じる。例えば図２に
示したような構造をとると隣接電極間の結合容量が上部
電極と下部電極の容量に対して大きくなり，回路動作上
の不安定要因となる事が明らかになった。In the above prior art,
Although not explicitly stated, it is apparent from the figure that the distance between adjacent capacitors is sufficiently large, and therefore, it is presumed that separation between adjacent electrodes did not become a problem. In a highly integrated device such as a 1-gigabit DRAM, which is the object of the present invention, the separation width is extremely small at 0.2 μm or less.
The thicknesses of the electrodes and dielectrics become almost equal to the separation width, which causes problems in fabrication and circuit operation. For example, when the structure as shown in FIG. 2 is adopted, it has been clarified that the coupling capacitance between the adjacent electrodes becomes larger than the capacitance of the upper electrode and the lower electrode, which becomes an unstable factor in the circuit operation.
【０００４】これを解決するためには，CVD法による高
誘電率膜作製法を用いてステップカバレジを確保し，図
３のような構造を採り，隣接電極間の電気的結合を遮断
する方法が有効であった。ただし，この場合，溝底面の
高誘電率誘電体を取り除く際の加工寸法が0.1μm以下と
極めて小さく，かつアスペクト比の大きな加工になるた
めに，安定な加工が難しい。そこで図４に示したように
溝底面加工を省略した構造を採る。特に鉛を構成元素に
含むPZTの様な高誘電率材料のCVD法では，堆積下地の材
料に堆積膜の組成が影響を受けるという特性を持つ。図
４の場合では，底面がシリコン酸化物を主成分とするの
に対し，電極部分は白金であるために，底面と電極表面
に同時に堆積を行うと，底面部分では鉛を過剰に含む誘
電体が堆積する。この結果，隣接電極間の直流的なリー
クやモホロジー悪化といった弊害が生まれる。In order to solve this problem, there is a method in which a step coverage is secured by using a high dielectric constant film forming method by a CVD method, a structure as shown in FIG. 3 is adopted, and electric coupling between adjacent electrodes is cut off. Was effective. However, in this case, since the processing dimension for removing the high dielectric constant dielectric material from the bottom of the groove is extremely small, that is, 0.1 μm or less, and the processing has a large aspect ratio, stable processing is difficult. Therefore, a structure in which the groove bottom processing is omitted as shown in FIG. 4 is adopted. In particular, the CVD method of a high dielectric constant material such as PZT containing lead as a constituent element has a characteristic that the composition of the deposited film is affected by the material of the deposition base. In the case of FIG. 4, since the bottom surface is mainly composed of silicon oxide, while the electrode portion is made of platinum, if deposition is performed simultaneously on the bottom surface and the electrode surface, the dielectric material containing excessive lead on the bottom surface portion Accumulates. As a result, adverse effects such as DC leakage between adjacent electrodes and deterioration of morphology occur.
【０００５】本発明の目的は，CVDの選択性に起因する
素子分離上の課題を解決することにある。[0005] An object of the present invention is to solve the problem of element isolation caused by the selectivity of CVD.
【０００６】[0006]
【課題を解決するための手段】上記目的を達するため
に，本発明の一実施形態によれば，下部電極として白金
を用い，この白金の形成前にチタン酸化物を10nm堆積
し，図１に示すような，溝底面部分にチタン酸化物が存
在する構造を作る。この構造上にCVD法で高誘電率絶縁
膜を50nm形成する。According to one embodiment of the present invention, platinum is used as a lower electrode, and titanium oxide is deposited to a thickness of 10 nm before the formation of platinum. As shown in the figure, a structure in which titanium oxide is present at the bottom of the groove is made. On this structure, a high dielectric constant insulating film is formed to a thickness of 50 nm by a CVD method.
【０００７】[0007]
【作用】図１の構造上に堆積した高誘電率絶縁膜は，白
金上では化学量論組成を満たすとともに溝底面では化学
量論組成よりもチタン原子が過剰な組成となる。底面の
非化学量論組成膜は，誘電率が低く絶縁性が高い膜とな
るので，隣接電極間の交流的直流的な電気的絶縁が保た
れる。また，結晶化の程度も小さいので，平滑なモホロ
ジーを有する膜が形成される。The high-dielectric-constant insulating film deposited on the structure of FIG. 1 satisfies the stoichiometric composition on platinum and has a composition in which titanium atoms are more excessive than the stoichiometric composition at the bottom of the groove. Since the non-stoichiometric composition film on the bottom surface has a low dielectric constant and a high insulating property, AC and DC electrical insulation between adjacent electrodes is maintained. Further, since the degree of crystallization is small, a film having a smooth morphology is formed.
【０００８】なお，本発明が解決する問題点は，分離幅
0.2μm以下のような非常に高集積度の記憶装置を検討し
て初めて顕在化するものである。また，上記選択性は，
このような高集積記憶装置に必要な100nm以下といった
極めて薄い高誘電率誘電体のCVD技術を開発して初めて
明らかになるものである。これら技術なしでは，前掲し
た問題点を把握することはできず，従って本発明の思想
に到達することもないと考えられる。The problem solved by the present invention is that the separation width
This becomes apparent only after studying very high-density storage devices of 0.2 μm or less. The above selectivity is
It becomes clear only after the development of a CVD technique for an extremely thin dielectric having a high dielectric constant of 100 nm or less required for such a highly integrated memory device. Without these techniques, the above-mentioned problems cannot be grasped, and therefore, it is considered that the concept of the present invention is not reached.
【０００９】[0009]
【実施例】本発明の一実施例を図１に示す。例えばMOS
トランジスタやバイポーラトランジスタからなる能動素
子，この能動素子への信号線，電源供給線等の配線部
分，これらを支持するシリコン基板からなる能動素子層
(101)の上に，本発明によるキャパシタを構成する。キ
ャパシタ下部電極(104)と能動素子層(101)の間，及び下
部電極相互の電気的絶縁をとる層間絶縁層(102)の上
に，10nm程度と薄いTiO2があり，この２層を貫通して電
気的な接続をとる導電体プラグ(105)が配置され，下部
電極(104)と能動素子層(101)の間の導通を確保してい
る。FIG. 1 shows an embodiment of the present invention. For example, MOS
Active elements such as transistors and bipolar transistors, signal lines to these active elements, wiring such as power supply lines, and active element layers composed of a silicon substrate that supports them
A capacitor according to the present invention is formed on (101). TiO 2 as thin as about 10 nm is provided between the capacitor lower electrode (104) and the active element layer (101), and on the interlayer insulating layer (102) for electrically insulating the lower electrodes from each other. A conductive plug (105) for electrical connection is arranged to ensure conduction between the lower electrode (104) and the active element layer (101).
【００１０】まず図１に示した構造の作製法を図５を用
いて述べる。能動素子層(101)を公知な方法で作製した
後，層間絶縁層(102)を作製する。ここではモノシラ
ン，ホスフィン，酸素を原料とする減圧CVD法により，
基板温度450℃で300nmの燐ガラス膜(102)を堆積した。
この層間絶縁層には，他の層間絶縁材料，例えば硼素燐
添加ガラス膜等公知な材料が用いられ，製法としては，
常圧のCVD法等，他の公知なCVD法による製法が適用でき
る。次に，二酸化チタン膜(103)を10nm堆積した。ここ
では，チタンイソプロポキシド(Ti(i-OC3H7)4)を原料と
するMOCVD法を用いた。チタンイソプロポキシドは常温
で液体であるため，原料を35℃の恒温槽内で加熱し，蒸
気圧を高めてArをキャリアガスとして3cc/min流すこと
により，反応室内に導入した。膜の酸素空孔を埋めるた
め，堆積時に酸素を100cc/min程度供給している。基板
温度は450℃で，堆積時圧力は2Torrとした。10分間の堆
積により約10nmの二酸化チタン膜を得た。二酸化チタン
膜の堆積に用いられるCVD原料は他にチタンブトキシド
等のアルコキシド原料，Ti(DPM)2(i-OC3H7)2等の錯体原
料，塩化チタンなどのハロゲン化物原料が適用できる。
また，通常のSiO2 CVDから容易に類推されるように，常
圧CVD，活性な酸素を用いるCVD法によっても良質な二酸
化チタン膜が形成できる。ここでは量産性を考慮してCV
D法を用いたが，反応性スパッタ法など公知な物理的成
膜法，ゾルゲル法などスピンコートによる化学的成膜
法，金属チタン堆積後に熱酸化する方法も適用できる。First, a method for manufacturing the structure shown in FIG. 1 will be described with reference to FIG. After forming the active element layer (101) by a known method, an interlayer insulating layer (102) is formed. Here, a low pressure CVD method using monosilane, phosphine, and oxygen as raw materials is used.
A 300-nm phosphor glass film (102) was deposited at a substrate temperature of 450 ° C.
For this interlayer insulating layer, a known material such as another interlayer insulating material, for example, a boron-phosphorus-doped glass film is used.
Other known CVD methods such as a normal pressure CVD method can be applied. Next, a titanium dioxide film (103) was deposited to a thickness of 10 nm. Here, the MOCVD method using titanium isopropoxide (Ti (i-OC 3 H 7 ) 4 ) as a raw material was used. Since titanium isopropoxide is liquid at room temperature, the raw material was heated in a constant temperature bath at 35 ° C, the vapor pressure was increased, and Ar was supplied as a carrier gas at a flow rate of 3 cc / min, thereby introducing the raw material into the reaction chamber. Oxygen is supplied at about 100 cc / min during deposition to fill the oxygen vacancies in the film. The substrate temperature was 450 ° C. and the deposition pressure was 2 Torr. An about 10 nm titanium dioxide film was obtained by deposition for 10 minutes. In addition, as a CVD material used for depositing a titanium dioxide film, an alkoxide material such as titanium butoxide, a complex material such as Ti (DPM) 2 (i-OC 3 H 7 ) 2 , and a halide material such as titanium chloride can be used.
Further, as easily inferred from normal SiO 2 CVD, a high-quality titanium dioxide film can also be formed by normal pressure CVD and CVD using active oxygen. Here, CV is considered in consideration of mass productivity.
Although the D method was used, a known physical film forming method such as a reactive sputtering method, a chemical film forming method by spin coating such as a sol-gel method, and a method of performing thermal oxidation after depositing titanium metal can also be applied.
【００１１】次に導電体プラグ(105)を形成する為の穴
(スルーホール)を，二酸化チタン膜(103)と層間絶縁層
(102)に開ける。公知なレジストを用いたフォトリソグ
ラフィー工程により，穴開け部分以外をレジストでマス
クした後に，公知なドライエッチング技術，例えばCHF3
をエッチングガスとしたリアクティブイオンエッチング
により穴開けを行った。Next, a hole for forming a conductor plug (105)
(Through hole) with titanium dioxide film (103) and interlayer insulating layer
Open at (102). After a portion other than the hole is masked with a resist by a photolithography process using a known resist, a known dry etching technique, for example, CHF 3
Holes were formed by reactive ion etching using as an etching gas.
【００１２】次に導電体プラグ(105)の形成を行う。こ
れには，公知なCVD法により，タングステンをスルーホ
ールに埋め込んだ。または，多結晶または非晶質シリコ
ンでも実現できる。(この際には，次に示す白金電極(10
4)とシリコンのシリサイド化反応を抑制するために，適
当な反応抑止層が必要である。)次に白金電極(104)の堆
積を行う。ここでは，RFスパッタ法にて，150 nm の白
金を堆積した。白金の堆積法としては，RFスパッタ法の
他に，DCスパッタ，CVD法でも実施できる。公知なレジ
ストを用いたフォトリソグラフィー工程により，溝形成
部分以外をレジストでマスクした後に，堆積した白金膜
のパターン形成は，公知なドライエッチング法により行
う。Arガスによるスパッタ法で，0.2 μm幅の溝を作製
した。Next, a conductor plug (105) is formed. For this, tungsten was buried in the through holes by a known CVD method. Alternatively, it can be realized by polycrystalline or amorphous silicon. (In this case, the platinum electrode (10
In order to suppress the silicidation reaction of 4) and silicon, an appropriate reaction suppression layer is required. Next, a platinum electrode (104) is deposited. Here, 150 nm of platinum was deposited by RF sputtering. Platinum can be deposited by DC sputtering or CVD in addition to RF sputtering. After a portion other than the groove formation portion is masked with a resist by a photolithography process using a known resist, the pattern formation of the deposited platinum film is performed by a known dry etching method. A groove with a width of 0.2 μm was fabricated by sputtering with Ar gas.
【００１３】以上のようにして，図１の構造を得た。As described above, the structure shown in FIG. 1 is obtained.
【００１４】次に図１の構造に対して高誘電率誘電体膜
を堆積するプロセスについて，図６を用い述べることに
する。高誘電率誘電体膜(601)としては，PZTを用い，作
製プロセスには，MOCVD法を用いた。まずMOCVD法の概要
を説明する。原料には，鉛の錯体として公知のPb(DP
M)2，ジルコニウムの錯体として公知のZr(DPM)4，チタ
ンには，アルコキシド原料Ti(i-OC3H7)4を用いた。それ
ぞれを別々の金属製容器に封入し，それぞれ，140℃，1
55℃，及び35℃に加熱し，蒸気圧を高めた。さらに反応
室への輸送効率を上げるために，アルゴンをキャリアガ
スとした輸送方式を用いた。また，酸化物であるPZTの
特性を向上させるために，酸素も供給している。キャリ
アガスと酸素の供給量は，それぞれ10cc-100cc，500cc
とした。キャリアガス量は，電極白金上でもっとも誘電
率が高くなる様に調整した。基板温度を550℃として，P
ZTを上記条件で堆積した場合の堆積速度は，3nm/min -
7nm/minの程度であった。約10分の堆積により，50nmのP
ZT薄膜(601)を堆積した。さらにMOCVD法により白金(60
2)を堆積し，図６に示す構造を作製した。Next, a process of depositing a high dielectric constant dielectric film on the structure of FIG. 1 will be described with reference to FIG. PZT was used as the high dielectric constant dielectric film (601), and the MOCVD method was used for the fabrication process. First, the outline of the MOCVD method will be described. Raw materials include Pb (DP
Alkoxide raw material Ti (i-OC 3 H 7 ) 4 was used for M) 2 , Zr (DPM) 4 known as a zirconium complex, and titanium. Each is sealed in a separate metal container, each at 140 ° C, 1
Heated to 55 ° C and 35 ° C to increase vapor pressure. To further increase the efficiency of transport to the reaction chamber, a transport method using argon as a carrier gas was used. Oxygen is also supplied to improve the properties of oxide PZT. The supply amounts of carrier gas and oxygen are 10cc-100cc and 500cc respectively.
And The carrier gas amount was adjusted so that the dielectric constant was highest on the platinum electrode. When the substrate temperature is 550 ° C, P
When ZT was deposited under the above conditions, the deposition rate was 3 nm / min-
It was about 7 nm / min. By depositing for about 10 minutes, 50nm P
A ZT thin film (601) was deposited. Furthermore, platinum (60
2) was deposited to produce the structure shown in FIG.
【００１５】この膜の白金電極上における比誘電率は50
0，単位面積当りの静電容量は，9μF/cm2であった。白
金電極の平面投影面積0.1μm2の場合，１つの白金電極
に対する容量値20fFが得られ，これは例えば1GビットDR
AMに必要な１ビット当りの静電容量に匹敵する。隣接電
極間の結合容量は，この容量値の数%であり，電気的な
結合は小さかった。これは，溝底面部において二酸化チ
タンと堆積膜のPZTとが反応し，誘電率が低く絶縁耐圧
の高いパイロクロア構造及びこれとチタン酸化物との混
合物(603)に変化したためである。この誘電体の誘電率
は，約50になっていることが電気的測定より分かった。The relative permittivity of this film on the platinum electrode is 50
0, the capacitance per unit area was 9 μF / cm 2 . When the planar projected area of the platinum electrode is 0.1 μm 2 , a capacitance value of 20 fF for one platinum electrode is obtained.
Equivalent to the capacitance per bit required for AM. The coupling capacitance between adjacent electrodes was several percent of this capacitance value, and the electrical coupling was small. This is because titanium dioxide reacts with PZT of the deposited film at the bottom of the groove to change into a pyrochlore structure having a low dielectric constant and a high withstand voltage and a mixture (603) of the same with titanium oxide. Electrical measurements showed that the dielectric constant of the dielectric was about 50.
【００１６】図７は，ここで述べたPZT薄膜形成プロセ
スを用いなかった場合に，生じた膜平滑性に関する問題
点を示した図である。このように，二酸化チタン(103)
を用いない場合には，溝部分のモホロジーが悪化(701)
し，結果として上部白金電極が溝底部に到達しない。こ
のため，１ビット当り静電容量が本発明による場合と比
較して50%以下になってしまうのみならず，隣接電極間
の電気的結合が増大するために，隣接電極の電位により
電極に蓄積される電荷量が変動すると言う結果となっ
た。また，隣接電極間の耐圧が低下し，2Vの電位差を与
えると10-6A/cm2にも及ぶ漏れ電流が観測される場合も
あった。FIG. 7 is a view showing a problem concerning the film smoothness that occurs when the PZT thin film forming process described here is not used. Thus, titanium dioxide (103)
If not used, the morphology of the groove will deteriorate (701)
As a result, the upper platinum electrode does not reach the groove bottom. As a result, not only does the capacitance per bit become 50% or less than in the case of the present invention, but also the electric coupling between adjacent electrodes increases, so that the electric potential of the adjacent electrodes causes the accumulation in the electrodes. As a result, the amount of charge applied fluctuates. In addition, the breakdown voltage between adjacent electrodes was reduced, and a leakage current as high as 10 −6 A / cm 2 was sometimes observed when a potential difference of 2 V was applied.
【００１７】上記実施例は，電極材料として白金，高誘
電率材料としてPZT，溝底部材料として二酸化チタンを
用いたが，次に示す様な材料の変更を行っても実施可能
である。電極材料としては，パラジウム，ニッケルの単
体金属，白金，パラジウム，ニッケルを主成分とする合
金，また，バナジウム，クロム，鉄，ルテニウム，イン
ジウム，錫，レニウム，イリジウム，鉛，銅，パラジウ
ムの酸化物及びこれらの酸化物を主成分とする混合酸化
物(酸化物超伝導体を含む)。さらに，チタン，バナジウ
ム，ジルコニウム，ニオブ，ハフニウム，タンタルの窒
化物。また，高誘電率材料としては，酸化物高誘電率材
料で次の形であらわされる材料が有効である。(A1A2..)
(B1B2..)Ox (A1, A2 .. = Ca, Sr, Cd, Ba, Pb, La, B
i, Tl, Na, K; B1, B2 .. = Ta, Ti, Zr, Hf, Fe, Nb,
Sn, U, Al, Mn, W, Yb, Sc, U, In, Sb, Co, Zn, Li, M
o, Ni, Co)また，これを主成分とする材料にさらに他の
元素を混合した場合にも有効である。溝底部材料として
は，上記B1,B2,..として挙げた元素の酸化物を主成分と
する材料が有効であった。In the above embodiment, platinum is used as the electrode material, PZT is used as the high dielectric constant material, and titanium dioxide is used as the bottom material of the groove. However, the present invention can also be implemented by changing the following materials. Electrode materials include simple metals of palladium and nickel, alloys containing platinum, palladium, and nickel as main components, and oxides of vanadium, chromium, iron, ruthenium, indium, tin, rhenium, iridium, lead, copper, and palladium. And mixed oxides containing these oxides as main components (including oxide superconductors). Furthermore, nitrides of titanium, vanadium, zirconium, niobium, hafnium, and tantalum. As the high dielectric constant material, an oxide high dielectric constant material represented by the following form is effective. (A1A2 ..)
(B1B2 ..) Ox (A1, A2 .. = Ca, Sr, Cd, Ba, Pb, La, B
i, Tl, Na, K; B1, B2 .. = Ta, Ti, Zr, Hf, Fe, Nb,
Sn, U, Al, Mn, W, Yb, Sc, U, In, Sb, Co, Zn, Li, M
o, Ni, Co) It is also effective when a material containing the same as a main component is further mixed with another element. As a material for the groove bottom, a material containing oxides of the above-mentioned elements B1, B2,.
【００１８】図８には，本発明を用いて作製したDRAMの
メモリセル部分の断面図を示す。本図はDRAMの例である
が，同様な構成により，不揮発性メモリとして動作させ
ることも可能であり，本発明が有効であることに変わり
はない。FIG. 8 is a sectional view of a memory cell portion of a DRAM manufactured by using the present invention. Although this drawing is an example of a DRAM, it is possible to operate as a nonvolatile memory with a similar configuration, and the present invention is still effective.
【００１９】[0019]
【発明の効果】本発明によれば，高集積の半導体記憶装
置が実現できる。According to the present invention, a highly integrated semiconductor memory device can be realized.
【図１】本発明の素子分離用堆積下地構造の断面図。FIG. 1 is a cross-sectional view of a deposition base structure for element isolation according to the present invention.
【図２】公知な素子分離方法を，高集積記憶装置に適用
した場合の断面図。FIG. 2 is a cross-sectional view when a known element isolation method is applied to a highly integrated storage device.
【図３】CVD法で公知な堆積下地上に絶縁膜を堆積した
後に，溝底部をエッチングして作製したキャパシタの断
面図。FIG. 3 is a cross-sectional view of a capacitor manufactured by depositing an insulating film on a known deposition base by a CVD method and then etching a groove bottom.
【図４】公知な堆積下地上にCVD法で絶縁膜を堆積した
場合のキャパシタ断面形状(下地によるCVDの選択性が無
いとしたとき)。FIG. 4 is a cross-sectional view of a capacitor when an insulating film is deposited on a known deposition underlayer by a CVD method (assuming that there is no CVD selectivity by the underlayer).
【図５】本発明の素子分離用堆積下地形成の方法の例。FIG. 5 is an example of a method of forming a deposition underlayer for element isolation according to the present invention.
【図６】本発明の素子分離用堆積下地上にCVD法で形成
した絶縁膜を用いたキャパシタ断面図。FIG. 6 is a cross-sectional view of a capacitor using an insulating film formed by a CVD method on an element isolation deposition base of the present invention.
【図７】公知な堆積下地上にCVD法で絶縁膜を堆積した
場合のキャパシタ断面図。FIG. 7 is a cross-sectional view of a capacitor when an insulating film is deposited on a known deposition base by a CVD method.
【図８】本発明によるDRAMメモリセル部の断面図。FIG. 8 is a sectional view of a DRAM memory cell unit according to the present invention.
101…能動素子層，102…素子分離層，103…二酸化チタ
ン膜，104…白金下部電極，105…導電性プラグ，201…
能動素子層，202…導電性プラグ，203…素子分離層，20
4…白金下部電極，205…高誘電率絶縁膜，206…上部白
金電極，301…能動素子層，302…導電性プラグ，303…
素子分離層，304…白金下部電極，305…高誘電率絶縁
膜，306…上部白金電極，401…能動素子層，402…導電
性プラグ，403…素子分離層，404…白金下部電極，405
…高誘電率絶縁膜，406…上部白金電極，601…高誘電率
絶縁膜，602…上部白金電極，603…低誘電率高耐圧誘電
体膜，701…組成異常低耐圧膜，801…シリコン基板，80
2…素子領域分離膜，803…MOSトランジスタゲート電
極，804…MOSトランジスタソース(ドレイン)，805…MOS
トランジスタソース(ドレイン)，806…信号配線,807…
信号配線。101 active element layer, 102 element isolation layer, 103 titanium dioxide film, 104 lower platinum electrode, 105 conductive plug, 201
Active element layer, 202: conductive plug, 203: element isolation layer, 20
4 ... Platinum lower electrode, 205 ... High dielectric constant insulating film, 206 ... Upper platinum electrode, 301 ... Active element layer, 302 ... Conductive plug, 303 ...
Element separation layer, 304: platinum lower electrode, 305: high dielectric constant insulating film, 306: upper platinum electrode, 401: active element layer, 402: conductive plug, 403: element separation layer, 404: platinum lower electrode, 405
... High dielectric constant insulating film, 406: Upper platinum electrode, 601: High dielectric constant insulating film, 602: Upper platinum electrode, 603: Low dielectric constant high withstand voltage dielectric film, 701: Abnormal composition low withstand voltage film, 801: Silicon substrate , 80
2… Element region isolation film, 803… MOS transistor gate electrode, 804… MOS transistor source (drain), 805… MOS
Transistor source (drain), 806 ... signal wiring, 807 ...
Signal wiring.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−121761（ＪＰ，Ａ) 特開 昭62−104081（ＪＰ，Ａ) 特開 平２−191330（ＪＰ，Ａ) 特開 平２−132791（ＪＰ，Ａ) 特開 平６−145992（ＪＰ，Ａ) 特開 平７−50395（ＪＰ，Ａ) 特表 平７−504783（ＪＰ，Ａ) 国際公開93／18530（ＷＯ，Ａ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/105 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/108 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-121761 (JP, A) JP-A-62-104081 (JP, A) JP-A-2-191330 (JP, A) JP-A-2- 132791 (JP, A) JP-A-6-145992 (JP, A) JP-A-7-50395 (JP, A) JP-A-7-504783 (JP, A) International publication 93/18530 (WO, A1) ( 58) Field surveyed (Int.Cl. 7 , DB name) H01L 27/105 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/108
Claims (8)
子に接続する導電性プラグを形成する工程と、 上記第２の絶縁膜上で上記導電性プラグに接続する 複
数の下部キャパシタ電極を形成する工程と、 上記下部キャパシタ電極上および、上記下部キャパシタ
電極間に配置された上記第２の絶縁膜の露出部分上に高
誘電率膜を形成する工程と、 上記高誘電率膜上に上部キャパシタ電極を形成する工程
とを含み、 上記高誘電率膜は、上記下部キャパシタ電極間の上記第
２の絶縁膜と接する部分において反応して上記高誘電率
膜に比べて低い誘電率と高い絶縁耐圧を有する膜に変化
した構造を形成することを特徴とする半導体記憶装置の
製造方法。A step of forming an active element layer; a step of forming a first insulating film on the active element layer; and a step of forming a second insulating film on the first insulating film. Forming a conductive plug connected to the active element through the first insulating film and the second insulating film; and a plurality of lower capacitor electrodes connected to the conductive plug on the second insulating film. Forming a high dielectric constant film on the lower capacitor electrode and on an exposed portion of the second insulating film disposed between the lower capacitor electrodes; Forming an upper capacitor electrode, wherein the high dielectric constant film reacts at a portion between the lower capacitor electrodes in contact with the second insulating film and has a lower dielectric constant and a higher dielectric constant than the high dielectric constant film. Structure changed to a film with dielectric strength Method of manufacturing a semiconductor memory device characterized by forming a.
法において、 上記第２の絶縁膜は、二酸化チタンを含
み、 上記高誘電率膜は、ＰＺＴを含むことを特徴とす
る半導体記憶装置の製造方法。2. The semiconductor memory device according to claim 1, wherein said second insulating film includes titanium dioxide, and said high dielectric constant film includes PZT. Manufacturing method.
製造方法において、 上記高誘電率膜に比べて低い誘電
率と高い絶縁耐圧を有する膜に変化した構造は、パイロ
クロア構造であることを特徴とする半導体記憶装置の製
造方法。3. The method for manufacturing a semiconductor memory device according to claim 1, wherein the structure changed to a film having a lower dielectric constant and a higher withstand voltage than the high dielectric constant film is a pyrochlore structure. A method for manufacturing a semiconductor memory device, comprising:
法において、 上記導電性プラグは、タングステンを含
むことを特徴とする半導体記憶装置の製造方法。4. The method of manufacturing a semiconductor memory device according to claim 1, wherein said conductive plug includes tungsten.
法において、 上記第２の絶縁膜は、ＣＶＤ法、スパッ
タ法により形成することを特徴とする半導体記憶装置の
製造方法。5. The method of manufacturing a semiconductor memory device according to claim 1, wherein said second insulating film is formed by a CVD method or a sputtering method.
法において、 上記下部キャパシタ電極は、パラジウム
またはニッケルまたは白金・パラジウム・ニッケルのい
ずれかの合金またはチタン・バナジウム・ジルコニウム
・ニオブ・タンタルのいずれかの窒化物を含むことを特
徴とする半導体記憶装置の製造方法。6. The method of manufacturing a semiconductor memory device according to claim 1, wherein said lower capacitor electrode is made of palladium, nickel, an alloy of platinum, palladium, nickel, or titanium, vanadium, zirconium, niobium, tantalum. A method for manufacturing a semiconductor memory device, comprising any one of nitrides.
法において、 上記複数の下部キャパシタ電極の分離幅
は、０．２μｍ以下であることを特徴とする半導体記憶
装置の製造方法。7. The method of manufacturing a semiconductor memory device according to claim 1, wherein a separation width of said plurality of lower capacitor electrodes is 0.2 μm or less.
法において、 上記高誘電率膜の膜厚は、１００ｎｍ以
下であることを特徴とする半導体記憶装置の製造方法。8. The method for manufacturing a semiconductor memory device according to claim 1, wherein said high dielectric constant film has a thickness of 100 nm or less.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28304793A JP3323607B2 (en) | 1993-11-12 | 1993-11-12 | Method for manufacturing semiconductor memory device |
| US08/281,568 US5499207A (en) | 1993-08-06 | 1994-07-28 | Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same |
| KR1019940019094A KR100333161B1 (en) | 1993-08-06 | 1994-08-02 | Semiconductor memory and improved manufacturing method with improved insulation between electrodes |
| US08/592,464 US5736449A (en) | 1993-08-06 | 1996-01-26 | Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28304793A JP3323607B2 (en) | 1993-11-12 | 1993-11-12 | Method for manufacturing semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07142598A JPH07142598A (en) | 1995-06-02 |
| JP3323607B2 true JP3323607B2 (en) | 2002-09-09 |
Family
ID=17660529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28304793A Expired - Fee Related JP3323607B2 (en) | 1993-08-06 | 1993-11-12 | Method for manufacturing semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3323607B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3113173B2 (en) * | 1995-06-05 | 2000-11-27 | シャープ株式会社 | Nonvolatile random access memory and method of manufacturing the same |
| JP3650005B2 (en) * | 1995-06-05 | 2005-05-18 | シャープ株式会社 | Nonvolatile random access memory and manufacturing method thereof |
| JPH10261772A (en) | 1997-01-14 | 1998-09-29 | Mitsubishi Electric Corp | Semiconductor storage device and its manufacture |
| JPH11126728A (en) * | 1997-08-25 | 1999-05-11 | Lucent Technol Inc | Thin-film capacitor and manufacture thereof |
| JP3244049B2 (en) | 1998-05-20 | 2002-01-07 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| KR100335775B1 (en) * | 1999-06-25 | 2002-05-09 | 박종섭 | Method of manufacturing a capacitor in a semiconductor device |
| JP2001168306A (en) | 1999-12-09 | 2001-06-22 | Toshiba Corp | Non-volatile semiconductor memory device and its manufacturing method |
| KR100376257B1 (en) * | 2000-12-21 | 2003-03-17 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in semiconductor device |
| KR100979231B1 (en) * | 2003-06-25 | 2010-08-31 | 주식회사 하이닉스반도체 | Method of manufacturing FeRAM device |
| JPWO2005122260A1 (en) * | 2004-06-11 | 2008-04-10 | 富士通株式会社 | Capacitance element, integrated circuit and electronic device |
| US20100001371A1 (en) * | 2007-12-05 | 2010-01-07 | Rohm Co., Ltd. | Semiconductor device having capacitor including a high dielectric film and manufacture method of the same |
-
1993
- 1993-11-12 JP JP28304793A patent/JP3323607B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07142598A (en) | 1995-06-02 |
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