KR100376257B1 - Method of manufacturing a capacitor in semiconductor device - Google Patents
Method of manufacturing a capacitor in semiconductor device Download PDFInfo
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- KR100376257B1 KR100376257B1 KR10-2000-0079504A KR20000079504A KR100376257B1 KR 100376257 B1 KR100376257 B1 KR 100376257B1 KR 20000079504 A KR20000079504 A KR 20000079504A KR 100376257 B1 KR100376257 B1 KR 100376257B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로서, 캐패시터의 하부전극과 콘택플러그 사이에 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물을 형성하거나, 또는 콘택플러그를 구성하는 확산방지막을 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물로 형성함으로써, 캐패시터를 형성하기 위한 소정의 열처리공정시, 주입되는 산소가 캐패시터의 하부로 침투되는 것을 방지하게 되어 콘택플러그의 소정 부위가 산화되는 것을 방지할 수 있는 반도체 소자의 캐패시터 제조 방법을 제공함에 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a small amount of heat-resistant material (Ti, Ta, W), O And a small amount of heat-resistant materials (Ti, Ta, W), O, and N on the semi-precious metal materials (Ru, Ir, Rh, Os, Re) to form a new composition to which N is added or to form a contact plug. By forming this new composition, it is possible to prevent oxygen from being injected into the lower portion of the capacitor during a predetermined heat treatment process for forming the capacitor, thereby preventing the oxidization of a predetermined portion of the contact plug. It is to provide a capacitor manufacturing method.
Description
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로서, 특히 캐패시터의 하부전극과 콘택플러그 사이에 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물을 형성하거나, 또는 콘택플러그를 구성하는 확산방지막을 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물로 형성함으로써, 캐패시터를 형성하기 위한 소정의 열처리공정시, 주입되는 산소가 캐패시터의 하부로 침투되는 것을 방지하게 되어 콘택플러그의 소정 부위가 산화되는 것을 방지할 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and in particular, a small amount of heat-resistant material (Ti, Ta, W) between a quasi-noble metal material (Ru, Ir, Rh, Os, Re) between a lower electrode and a contact plug of a capacitor A small amount of heat-resistant materials (Ti, Ta, W), O and N are added to the semi-precious metal materials (Ru, Ir, Rh, Os, Re) to form a new composition containing O and N, or to form a diffusion preventing film constituting the contact plug. By forming a new composition to which N is added, a semiconductor device capable of preventing oxygen from being injected into the lower portion of the capacitor during a predetermined heat treatment process for forming a capacitor, thereby preventing a predetermined portion of the contact plug from being oxidized. It relates to a method for producing a capacitor.
DRAM의 집적도가 증가하면서 보다 높은 유전율과 작은 누설전류 특성이 요구됨에 따라 캐패시터의 구조는 누설전류가 작은 MIM 구조로의 변화가 요구되고 있다. 현재 MIM 구조의 캐패시터 하부전극으로는 귀금속물질이 사용되고 있다. 이러한, 하부전극은 CVD 방법에 의해 증착되는데, CVD를 이용한 하부전극의 형성공정시 주입되는 산소에 의해 하부전극의 아래층에 형성된 확산방지막이 산화되어 전기적 특성을 열화시키는 문제가 발생하게 된다.As the integration of DRAMs increases, higher dielectric constants and smaller leakage current characteristics are required, and therefore, the capacitor structure needs to be changed to a MIM structure with a small leakage current. Currently, precious metal materials are used as capacitor lower electrodes of the MIM structure. The lower electrode is deposited by a CVD method, and the diffusion barrier layer formed on the lower layer of the lower electrode is oxidized by oxygen injected during the formation of the lower electrode using CVD, thereby deteriorating electrical characteristics.
DRAM에서 캐패시터의 하부전극은 반도체 기판과 다결정 실리콘, 오믹콘택층 및 확산방지막으로 형성된 콘택플러그를 통하여 접촉된다. DRAM이 고집적화됨에 따라 Ta2O5, BST, ((Ba,Sr)TiO3), STO(SrTiO3)등의 유전율이 높은 새로운 유전체물질이사용되어야 하나 콘택 플러그와의 반응을 통한 부피감소 및 플러그 산화에 의한 콘택저항의 증가가 문제시되고 있다. 이를 막기 위해 금속물질로 구성된 하부전극과 반도체 기판의 접합영역을 전기적으로 접속시키기 위한 콘택 플러그의 최상단에는 Ti, Ta 및 W와 같은 다결정 또는 TiN, TaN 및 WN과 같은 질화막 또는 TiAlN, TiSiN, WSiN 및 TaSiN과 같은 삼원계 질화막으로 구성된 확산방지막이 형성된다. 그러나, 확산방지막 형성 후에 이루어지는 후속 열처리공정시, 주입되는 산소와 확산방지막에 함유된 물질들이 반응하여 소정의 산화물이 생성된다. 이런 산화물에 의해 캐패시터의 전기적특성이 열화되는 문제가 발생된다.The lower electrode of the capacitor in the DRAM contacts the semiconductor substrate through a contact plug formed of polycrystalline silicon, an ohmic contact layer, and a diffusion barrier. As DRAMs are highly integrated, new dielectric materials with high dielectric constants such as Ta 2 O 5 , BST, ((Ba, Sr) TiO 3 ) and STO (SrTiO 3 ) should be used, but volume reduction and plug through reaction with contact plug An increase in contact resistance due to oxidation is a problem. To prevent this, at the top of the contact plug for electrically connecting the lower electrode made of a metal material and the junction region of the semiconductor substrate, a polycrystal such as Ti, Ta and W or a nitride film such as TiN, TaN and WN or TiAlN, TiSiN, WSiN and A diffusion barrier film formed of a ternary nitride film such as TaSiN is formed. However, in the subsequent heat treatment process after the formation of the diffusion barrier film, the injected oxygen and the materials contained in the diffusion barrier film react to produce a predetermined oxide. This oxide causes a problem that the electrical characteristics of the capacitor deteriorate.
특히, 캐패시터의 유전체막을 형성하기 위한 열처리공정시, 가해지는 고온과 산소에 의해 하부전극을 경유하여 산소가 확산방지막이 형성된 방향으로 확산하여 확산방지막을 산화시켜 확산방지막의 상부표면에 부도체의 산화막이 형성된다. 이 산화막에 의해 캐패시터의 하부전극과 반도체 기판에 형성된 접합영역간의 전기적인 콘택저항이 증가하게 되는 문제가 발생한다.In particular, during the heat treatment process for forming the dielectric film of the capacitor, oxygen diffuses through the lower electrode through the lower electrode by the high temperature and oxygen applied to oxidize the diffusion barrier to oxidize the diffusion barrier so that the oxide film of the non-conductor is formed on the upper surface of the diffusion barrier. Is formed. This oxide film causes a problem that the electrical contact resistance between the lower electrode of the capacitor and the junction region formed in the semiconductor substrate increases.
따라서, 본 발명의 목적은 캐패시터를 형성하기 위한 소정의 열처리공정시, 캐패시터의 하부에 형성된 콘택플러그의 소정 부위가 산화되어 전기적인 특성이 감소되는 것을 방지하기 위한 반도체 소자의 캐패시터 제조 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method of manufacturing a capacitor of a semiconductor device for preventing the electrical properties of the contact plug formed under the capacitor from being oxidized during a predetermined heat treatment process for forming the capacitor. have.
본 발명의 또 다른 목적은 캐패시터의 하부전극과 콘택플러그 사이에 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물을 형성하거나, 또는 콘택플러그를 구성하는 확산방지막을 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물로 형성함으로써, 캐패시터를 형성하기 위한 소정의 열처리공정시, 주입되는 산소가 캐패시터의 하부로 침투되는 것을 방지하게 되어 콘택플러그의 소정 부위가 산화되는 것을 방지할 수 있는 반도체 소자의 캐패시터 제조 방법을 제공함에 있다.It is still another object of the present invention that a small amount of heat-resistant materials (Ti, Ta, W), O and N are added to the semi-precious metal materials (Ru, Ir, Rh, Os, Re) between the lower electrode of the capacitor and the contact plug. The diffusion barrier layer forming the composition or forming the contact plug is a new composition in which a small amount of heat-resistant substances (Ti, Ta, W), O and N are added to the semi-noble metal substances (Ru, Ir, Rh, Os, Re). By providing a capacitor, a method of manufacturing a capacitor of a semiconductor device capable of preventing oxygen from being injected into a lower portion of the capacitor during a predetermined heat treatment process for forming a capacitor and preventing a predetermined portion of the contact plug from being oxidized. have.
도 1(a) 내지 도 1(c)는 본 발명의 제 1 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a semiconductor device sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to a first embodiment of the present invention.
도 2(a) 내지 도 2(b)는 본 발명의 제 2 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도.2 (a) to 2 (b) are cross-sectional views of semiconductor devices sequentially shown for explaining a method of manufacturing a capacitor of a semiconductor device according to a second embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1,11 : 반도체 기판 2,12 : 층간절연층1,11 semiconductor substrate 2,12 interlayer insulating layer
3,13 : 다결정 실리콘 4,14 : 오믹콘택층3,13 polycrystalline silicon 4,14 ohmic contact layer
5 : 확산방지막 6,16 : 콘택플러그5: diffusion barrier 6,16: contact plug
7, 15 : 보호층 8,17 : 하부전극7, 15: protective layer 8, 17: lower electrode
9,18 : 유전체막 10,19 : 상부전극9,18 dielectric film 10,19 upper electrode
본 발명은 소정의 구조가 형성된 반도체 기판 상부에 절연막을 형성한 후, 상기 절연막의 소정 영역을 식각하여 상기 반도체 기판의 소정 영역을 노출시키는 콘택홀을 형성하는 단계와; 상기 콘택홀을 메우도록 콘택플러그를 형성하는 단계와; 상기 콘택플러그 상부에 준귀금속물질에 소량의 내열물질, O 및 N이 첨가된 보호층을 형성하는 단계와; 상기 보호층 상부에 하부전극, 유전체막 및 상부전극을 순차적으로 형성하는 단계를 포함한다.The present invention provides a method for manufacturing a semiconductor device, comprising: forming an insulating layer on an upper surface of a semiconductor substrate on which a predetermined structure is formed, and then forming a contact hole for etching a predetermined region of the insulating layer to expose a predetermined region of the semiconductor substrate; Forming a contact plug to fill the contact hole; Forming a protective layer having a small amount of heat-resistant material, O and N added to the quasi-noble metal material on the contact plug; And sequentially forming a lower electrode, a dielectric film, and an upper electrode on the protective layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(c)는 본 발명의 제 1 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of semiconductor devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to a first embodiment of the present invention.
도 1(a)를 참조하면, 우선 소정의 구조가 형성된 반도체 기판(1) 상부에 층간절연층(2)이 형성된다. 층간절연층(2)은 반도체 기판(1)의 소정 부분이 노출되도록 패터닝되어 자신의 소정 부위에 콘택홀이 형성된다. 콘택홀이 형성된 반도체 기판(1) 상부에는 콘택홀을 메우도록 콘택플러그(6)가 형성된다.Referring to FIG. 1A, an interlayer insulating layer 2 is first formed on a semiconductor substrate 1 on which a predetermined structure is formed. The interlayer insulating layer 2 is patterned so that a predetermined portion of the semiconductor substrate 1 is exposed so that contact holes are formed in a predetermined portion thereof. The contact plug 6 is formed on the semiconductor substrate 1 on which the contact hole is formed to fill the contact hole.
콘택플러그(6)는 다결정 실리콘(3), 오믹콘택층(4) 및 확산방지막(5)이 형성된 적층구조로 형성된다.The contact plug 6 is formed in a laminated structure in which the polycrystalline silicon 3, the ohmic contact layer 4, and the diffusion barrier film 5 are formed.
오믹콘택층(4)은 확산방지막(5)과 다결정 실리콘(3)간에 상호 접촉력을 높이기 위해 TiSi2가 일반적으로 사용된다. 확산방지막(5)은 Ti, Ta 및 W와 같은 다결정 또는 TiN, TaN 및 WN과 같은 질화막 또는 TiAlN, TiSiN, WSiN 및 TaSiN과 같은 삼원계 질화막으로 형성된다.In the ohmic contact layer 4, TiSi 2 is generally used to increase the mutual contact force between the diffusion barrier film 5 and the polycrystalline silicon 3. The diffusion barrier 5 is formed of polycrystals such as Ti, Ta and W or nitride films such as TiN, TaN and WN or ternary nitride films such as TiAlN, TiSiN, WSiN and TaSiN.
도 1(b)를 참조하면, 콘택플러그(6)를 포함하는 전체 구조 상부에 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물이 25∼500℃의 온도범위에서 200∼1000Å의 두께로 PVD(Physical Vapor Deposition) 또는 CVD(Chemical Vapor Deposition) 또는 ALD(Atomic Layer Deposition)에 의해 보호층(7)이 증착된다.Referring to FIG. 1 (b), a small amount of heat-resistant materials (Ti, Ta, W), O, and quasi-noble metal materials (Ru, Ir, Rh, Os, Re) on the entire structure including the contact plug 6 A new composition containing N is deposited on the protective layer 7 by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) to a thickness of 200 to 1000 kPa over a temperature range of 25 to 500 ° C. do.
보호층(7)은 조성비가 50∼90at%인 Ru, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Ru, 10∼50at%인 Ta, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Ru, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Ir, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Ir, 10∼50at%인 Ta, 1∼20at%인 O 및10∼80at%인 N으로 증착되거나, 50∼90at%인 Ir, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Rh, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Rh, 10∼50at%인 Ta, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Rh, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Os, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Os, 10∼50at%인, 1∼20at%인 O Ta 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Os, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Re, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Re, 10∼50at%인 Ta, 1∼20at%인 O 및 10∼80at%인 N으로 증착되거나, 50∼90at%인 Re, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 증착된다.The protective layer 7 is deposited with Ru of 50 to 90 at%, Ti of 10 to 50 at%, O of 1 to 20 at% and N of 10 to 80 at%, or Ru of 50 to 90 at%, 10 to 50 at% Phosphorus Ta, deposited at 1-20 at% O and 10-80 at% N, deposited at 50-90 at% Ru, 10-50 at% W, 1-20 at% O and 10-80 at% N , 50 to 90 at% Ir, 10 to 50 at% Ti, 1 to 20 at% O and 10 to 80 at% N, 50 to 90 at% Ir, 10 to 50 at% Ta, 1 to 20 at% Phosphorous O and 10 to 80 at% N, 50 to 90 at% Ir, 10 to 50 at% W, 1 to 20 at% O and 10 to 80 at% N, or 50 to 90 at% Rh 10 to 50 at% Ti, 1 to 20 at% O and 10 to 80 at% N, or 50 to 90 at% Rh, 10 to 50 at% Ta, 1 to 20 at% O and 10 to 80 at% Deposited with phosphorus N, 50 to 90 at% Rh, 10 to 50 at% W, 1 to 20 at% O and 10 to 80 at% N, 50 to 90 at% Os, 10 to 50 at% Ti Or deposited with O at 1-20 at% and N at 10-80 at%, or Os at 50-90 at%, 10-50 at% Deposited with 20 at% O Ta and 10 to 80 at% N, 50 to 90 at% Os, 10 to 50 at% W, 1 to 20 at% O and 10 to 80 at% N, or 50 to 90 at % Re, 10 to 50 at% Ti, 1 to 20 at% O and 10 to 80 at% N, or 50 to 90 at% Re, 10 to 50 at% Ta, 1 to 20 at% O and 10 It is deposited with N of -80 at%, or Re of 50-90 at%, W of 10-50 at%, O of 1-20 at%, and N of 10-80 at%.
도 1(c)를 참조하면, 이후, 보호층(7)을 포함한 전체 구조 상부에 귀금속물질 또는 준금속물질 또는 귀금속 물질 또는 전도성 물질이 증착된 후, 소정의 식각공정에 의해 보호층(7)과 함께 패터닝되어 하부전극(8)이 형성된다.Referring to FIG. 1C, after the noble metal material, the metalloid material, the noble metal material or the conductive material is deposited on the entire structure including the protective layer 7, the protective layer 7 is formed by a predetermined etching process. And the lower electrode 8 is formed together.
하부전극(8)을 포함한 전체 구조 상부에 유전체막(9) 및 상부전극(10)이 순차적으로 형성된다.The dielectric film 9 and the upper electrode 10 are sequentially formed on the entire structure including the lower electrode 8.
여기서, 유전체막(9)은 열처리공정에 의해 열처리되는데, 열처리공정은 상부전극(10)이 형성전 또는 형성후에 이루어진다.Here, the dielectric film 9 is heat treated by a heat treatment process, which is performed before or after the upper electrode 10 is formed.
열처리공정은 600∼800℃의 온도범위와 O2, N2, NH4, Ar과 O2가 소정 비율로혼합된 혼합가스, N2와 O2가 소정 비율로 혼합된 혼합가스, Ar과 O2의 혼합 플라즈마, N2와 O2의 혼합 플라즈마, N2O 플라즈마, NH4플라즈마 및 자외선 오존 분위기중 어느 하나의 분위기에서 이루어진다.The heat treatment process includes a temperature range of 600 to 800 ° C. and a mixed gas in which O 2 , N 2 , NH 4 , Ar and O 2 are mixed at a predetermined ratio, a mixed gas in which N 2 and O 2 are mixed at a predetermined ratio, Ar and O 2 , a mixed plasma of N 2 and O 2 , an N 2 O plasma, an NH 4 plasma, and an ultraviolet ozone atmosphere.
도 2(a) 및 도 2(b)는 본 발명의 제 2 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도이다.2 (a) and 2 (b) are cross-sectional views of semiconductor devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to a second embodiment of the present invention.
도 2(a)를 참조하면, 우선 소정의 구조가 형성된 반도체 기판(11) 상부에 층간절연층(12)이 형성된다. 층간절연층(12)은 반도체 기판(11)의 소정 부분이 노출되도록 패터닝되어 자신의 소정 부위에 콘택홀이 형성된다. 콘택홀이 형성된 반도체 기판(11) 상부에는 콘택홀을 매립하도록 콘택플러그(16)와 보호층(15)이 순차적으로 형성된다.Referring to FIG. 2A, an interlayer insulating layer 12 is first formed on a semiconductor substrate 11 having a predetermined structure. The interlayer insulating layer 12 is patterned so that a predetermined portion of the semiconductor substrate 11 is exposed to form contact holes in its predetermined portion. The contact plug 16 and the protective layer 15 are sequentially formed on the semiconductor substrate 11 on which the contact holes are formed so as to fill the contact holes.
콘택플러그(16)는 다결정 실리콘(13) 및 오믹콘택층(14)의 적층 구조로 형성된다.The contact plug 16 is formed of a laminated structure of the polycrystalline silicon 13 and the ohmic contact layer 14.
오믹콘택층(14)은 보호층(15)과 다결정 실리콘(13)간에 상호 접촉력을 높이기 위해 TiSi2가 일반적으로 사용된다.In the ohmic contact layer 14, TiSi 2 is generally used to increase the mutual contact force between the protective layer 15 and the polycrystalline silicon 13.
보호층(15)은 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물이 25∼500℃의 온도범위에서 PVD(Physical Vapor Deposition) 또는 CVD(Chemical Vapor Deposition) 또는 ALD(Atomic Layer Deposition)에 의해 200∼1000Å의 두께로 증착된 후, 패터닝되어 형성된다.The protective layer 15 is a new composition in which a small amount of heat-resistant materials (Ti, Ta, W), O, and N are added to the quasi-noble metal materials (Ru, Ir, Rh, Os, Re) in a temperature range of 25 to 500 ° C. Physical vapor deposition (PVD) or chemical vapor deposition (CVD) or atomic layer deposition (ALD) is deposited to a thickness of 200 to 1000 Å, followed by patterning.
여기서, 보호층(15)은 조성비가 50∼90at%인 Ru, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Ru, 10∼50at%인 Ta, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Ru, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Ir, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Ir, 10∼50at%인 Ta, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Ir, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Rh, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Rh, 10∼50at%인 Ta, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Rh, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Os, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Os, 10∼50at%인, 1∼20at%인 O Ta 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Os, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Re, 10∼50at%인 Ti, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Re, 10∼50at%인 Ta, 1∼20at%인 O 및 10∼80at%인 N으로 형성되거나, 50∼90at%인 Re, 10∼50at%인 W, 1∼20at%인 O 및 10∼80at%인 N으로 형성된다.The protective layer 15 is formed of Ru having a composition ratio of 50 to 90 at%, Ti of 10 to 50 at%, O of 1 to 20 at%, and N of 10 to 80 at%, or Ru of 10 to 80 at%, or 10 to 50 at%. 50 at% Ta, 1 to 20 at% O and 10 to 80 at% N or 50 to 90 at% Ru, 10 to 50 at% W, 1 to 20 at% O and 10 to 80 at% N Formed from 50 to 90 at% Ir, 10 to 50 at% Ti, 1 to 20 at% O and 10 to 80 at% N, 50 to 90 at% Ir, 10 to 50 at% Ta, 1 to 20 at% O and 10 to 80 at% N, 50 to 90 at% Ir, 10 to 50 at% W, 1 to 20 at% O and 10 to 80 at% N, or 50 to 90 at% Phosphorus Rh, 10 to 50 at% Ti, 1 to 20 at% O and 10 to 80 at% N, or 50 to 90 at% Rh, 10 to 50 at% Ta, 1 to 20 at% O and 10 to 80 at% N, 50 to 90 at% Rh, 10 to 50 at% W, 1 to 20 at% O and 10 to 80 at% N, 50 to 90 at% Os, 10 to 50 at% Ti, which is formed from 1 to 20 at% O and 10 to 80 at% N, or 50 to 90 at% Os, 10 50 at%, 1 to 20 at% O Ta and 10 to 80 at% N, or 50 to 90 at% Os, 10 to 50 at% W, 1 to 20 at% O and 10 to 80 at% N Formed from 50 to 90 at% Re, 10 to 50 at% Ti, 1 to 20 at% O and 10 to 80 at% N, 50 to 90 at% Re, 10 to 50 at% Ta, 1 to 20 at% O and 10 to 80 at% N, or 50 to 90 at% Re, 10 to 50 at% W, 1 to 20 at% O and 10 to 80 at% N.
도 2(b)를 참조하면, 이후, 콘택플러그(16)를 포함한 전체 구조 상부에 귀금속물질 또는 준금속물질 또는 귀금속 물질 또는 전도성 물질이 증착된 후, 소정의 식각공정에 의해 패터닝되어 하부전극(17)이 형성된다.Referring to FIG. 2 (b), after the precious metal material, the metalloid material, the precious metal material or the conductive material is deposited on the entire structure including the contact plug 16, the lower electrode may be patterned by a predetermined etching process. 17) is formed.
하부전극(17)을 포함한 전체 구조 상부에 유전체막(18) 및 상부전극(19)이 순차적으로 형성된다.The dielectric film 18 and the upper electrode 19 are sequentially formed on the entire structure including the lower electrode 17.
여기서, 유전체막(18)은 열처리공정에 의해 열처리되는데, 열처리공정은 상부전극(19)이 형성전 또는 형성후에 이루어진다.Here, the dielectric film 18 is heat treated by a heat treatment process, which is performed before or after the upper electrode 19 is formed.
열처리공정은 600∼800℃의 온도범위와 O2, N2, NH4, Ar과 O2가 소정 비율로 혼합된 혼합가스, N2와 O2가 소정 비율로 혼합된 혼합가스, Ar과 O2의 혼합 플라즈마, N2와 O2의 혼합 플라즈마, N2O 플라즈마, NH4플라즈마 및 자외선 오존 분위기중 어느 하나의 분위기에서 이루어진다.The heat treatment process is a temperature range of 600 to 800 ℃ and O 2 , N 2 , NH 4 , a mixed gas in which Ar and O 2 are mixed in a predetermined ratio, a mixed gas in which N 2 and O 2 is mixed in a predetermined ratio, Ar and O 2 , a mixed plasma of N 2 and O 2 , an N 2 O plasma, an NH 4 plasma, and an ultraviolet ozone atmosphere.
전술한 바와 같이, 본 발명은 캐패시터의 하부전극과 콘택플러그 사이에 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물을 형성하거나, 콘택플러그를 구성하는 확산방지막을 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물로 형성한다.As described above, in the present invention, a small amount of heat-resistant materials (Ti, Ta, W), O, and N are added to the quasi-noble metal materials (Ru, Ir, Rh, Os, and Re) between the lower electrode of the capacitor and the contact plug. Form a new composition or use a diffusion barrier to form a contact plug into a new composition containing a small amount of heat-resistant materials (Ti, Ta, W), O and N added to the quasi-noble metals (Ru, Ir, Rh, Os, Re). Form.
상술한 바와 같이, 본 발명은 본 발명은 캐패시터의 하부전극과 콘택플러그 사이에 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물을 형성하거나, 또는 콘택플러그를 구성하는 확산방지막을 준귀금속물질(Ru, Ir, Rh, Os, Re)에 소량의 내열물질(Ti, Ta, W), O 및 N이 첨가된 새로운 조성물로 형성함으로써, 캐패시터를 형성하기 위한 소정의 열처리공정시, 주입되는 산소가 캐패시터의 하부로 침투되는 것을 방지하게 되어 콘택플러그의 소정 부위가 산화되는 것을 방지할 수 있다. 이로 인해, 콘택플러그와 캐패시터의 계면특성이 개선되어 캐패시터의 전기적특성을 향상시킬 수 있다.As described above, the present invention is a small amount of heat-resistant material (Ti, Ta, W), O and N in the quasi-noble metal material (Ru, Ir, Rh, Os, Re) between the lower electrode of the capacitor and the contact plug A small amount of heat-resistant materials (Ti, Ta, W), O, and N are added to the semi-precious metal materials (Ru, Ir, Rh, Os, Re) to form the new composition to be added or to form a diffusion plug forming the contact plug. By forming the new composition, it is possible to prevent the oxygen to be injected into the lower portion of the capacitor during the predetermined heat treatment process for forming the capacitor and to prevent the oxidized portion of the contact plug. As a result, the interface characteristics of the contact plug and the capacitor may be improved, thereby improving the electrical characteristics of the capacitor.
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| JPH10242409A (en) * | 1996-12-26 | 1998-09-11 | Sony Corp | Electronic material and its manufacturing method, dielectric capacitor, non-volatile memory, and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142598A (en) * | 1993-11-12 | 1995-06-02 | Hitachi Ltd | Semiconductor memory device and manufacture thereof |
| JPH09102591A (en) * | 1995-07-28 | 1997-04-15 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH1022469A (en) * | 1996-06-28 | 1998-01-23 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH10242408A (en) * | 1996-12-26 | 1998-09-11 | Sony Corp | Dielectric capacitor, non-volatile memory and semiconductor device |
| JPH10242409A (en) * | 1996-12-26 | 1998-09-11 | Sony Corp | Electronic material and its manufacturing method, dielectric capacitor, non-volatile memory, and semiconductor device |
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