JP3242478B2 - High voltage semiconductor device - Google Patents
High voltage semiconductor deviceInfo
- Publication number
- JP3242478B2 JP3242478B2 JP00797693A JP797693A JP3242478B2 JP 3242478 B2 JP3242478 B2 JP 3242478B2 JP 00797693 A JP00797693 A JP 00797693A JP 797693 A JP797693 A JP 797693A JP 3242478 B2 JP3242478 B2 JP 3242478B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- semiconductor device
- breakdown voltage
- substrate
- high breakdown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、高耐圧半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device.
【０００２】[0002]
【従来の技術】従来、半導体装置、特に集積化された半
導体素子において、高耐圧を必要とする場合、素子のブ
レークダウン電圧を高めるため、半導体基板の表面と導
電配線の間の絶縁層用として基板上に形成されるシリコ
ン酸化膜を厚く形成することが行われている。2. Description of the Related Art Conventionally, when a high withstand voltage is required in a semiconductor device, especially an integrated semiconductor device, it is used as an insulating layer between the surface of a semiconductor substrate and conductive wiring in order to increase the breakdown voltage of the device. 2. Description of the Related Art A thick silicon oxide film is formed on a substrate.
【０００３】例えば、半導体基板として、支持体層上に
絶縁膜で電気的に分離された半導体分離島が形成されて
なる誘電体分離基板を用いた高耐圧半導体装置の場合
は、図３および図４に示すような構成が取られている。
従来、図３および図４の高耐圧半導体装置５１は、誘電
体分離基板（以下、適宜「ＤＩ基板」と言う）５２の単
結晶シリコンからなるｎ型分離島（半導体分離島）５３
にｐｎ接合が作り込まれている。ＤＩ基板５２は、通
常、ポリシリコン層（支持体層）５５上に絶縁膜５４で
電気的に分離された複数のｎ型分離島５３が形成されて
なる（図３，４の場合は便宜上１個だけを示す）基板で
あり、異なるｎ型分離島に作り込まれた半導体素子同士
の間では相互干渉が起こり難いという利点がある。For example, in the case of a high breakdown voltage semiconductor device using a dielectric isolation substrate in which a semiconductor isolation island electrically separated by an insulating film is formed on a support layer as a semiconductor substrate, FIGS. The configuration shown in FIG.
Conventionally, the high breakdown voltage semiconductor device 51 shown in FIGS. 3 and 4 has an n-type isolation island (semiconductor isolation island) 53 made of single crystal silicon of a dielectric isolation substrate (hereinafter, appropriately referred to as a “DI substrate”) 52.
A pn junction is formed. The DI substrate 52 is generally formed by forming a plurality of n-type isolation islands 53 electrically separated by an insulating film 54 on a polysilicon layer (support layer) 55 (in FIGS. This is an advantage in that mutual interference hardly occurs between semiconductor elements formed in different n-type isolation islands.
【０００４】半導体装置５１では、ｎ型分離島５３の表
面部分にはｐ型領域６３とｎ+ 型領域６４が形成されて
おり、かつ、ｎ型分離島５３表面では、ｐ型領域６３に
コンタクトする電極６６とｎ+ 型領域６４にコンタクト
する電極６７が絶縁層６９を介して分離島外に引き出さ
れている。しかしながら、この半導体装置５１では、ｐ
ｎ接合が逆バイアスされた場合、電極６６とｎ型分離島
５３の表面の間の電位差は大きくて、ここでのブレーク
ダウン電圧を高めるため、絶縁層６９であるシリコン酸
化膜の厚みを厚くして、電極６６とｎ型分離島５３の表
面の間の電界を緩和するようにしていた。In the semiconductor device 51, a p-type region 63 and an n + -type region 64 are formed on a surface portion of the n-type isolation island 53, and a contact is made with the p-type region 63 on the surface of the n-type isolation island 53. The electrode 66 and the electrode 67 contacting the n + -type region 64 are drawn out of the isolation island via the insulating layer 69. However, in this semiconductor device 51, p
When the n-junction is reverse-biased, the potential difference between the electrode 66 and the surface of the n-type isolation island 53 is large, and the thickness of the silicon oxide film as the insulating layer 69 is increased to increase the breakdown voltage. Thus, the electric field between the electrode 66 and the surface of the n-type isolation island 53 is reduced.
【０００５】[0005]
【発明が解決しようとする課題】上記のＩＣ構成の半導
体装置において、より高耐圧化を図る時には、それに相
応した厚いシリコン酸化膜を基板であるウエハ全面に形
成することになるが、シリコン酸化膜厚みがどんどん厚
く（２〜３μｍ以上）なると、以下の問題を生じるよう
になる。In the semiconductor device having the above-mentioned IC structure, when a higher breakdown voltage is to be achieved, a thick silicon oxide film corresponding thereto is formed on the entire surface of the wafer as a substrate. As the thickness increases (2 to 3 μm or more), the following problem occurs.
【０００６】すなわち、ウエハのシリコンと表面の酸化
シリコンとの熱膨張率の差に起因して厚いシリコン酸化
膜の場合、ウエハが大きく反り、それ以降のウエハ加工
プロセスが処理困難になる。特に、ＤＩ基板５２の場合
は反りが大きい。この発明は、上記事情に鑑み、半導体
基板用のウエハの反りを抑えつつ耐圧向上の図れる製造
容易な高耐圧半導体装置を提供することを課題とする。That is, in the case of a thick silicon oxide film due to the difference in the coefficient of thermal expansion between the silicon of the wafer and the silicon oxide on the surface, the wafer is greatly warped and the subsequent wafer processing becomes difficult. Particularly, in the case of the DI substrate 52, the warpage is large. SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a high-breakdown-voltage semiconductor device which is easy to manufacture and can improve the withstand voltage while suppressing the warpage of a semiconductor substrate wafer.
【０００７】[0007]
【課題を解決するための手段】前記課題を解決するた
め、この発明にかかる高耐圧半導体装置では、半導体基
板を備え、この基板の表面に絶縁層を介して複数の導電
配線が設けられている構成において、前記導電配線のう
ち半導体基板との間に大きい電位差が生じる導電配線の
下の絶縁層だけは部分的に他の部分より厚みが厚くなっ
ており、前記厚みの厚い絶縁層部分は酸化膜からなって
いるとともに厚みの薄い絶縁層部分は少なくとも酸化防
止層を設けるようにしている。In order to solve the above-mentioned problems, a high breakdown voltage semiconductor device according to the present invention includes a semiconductor substrate, and a plurality of conductive wirings are provided on the surface of the substrate via an insulating layer. In the structure, only the insulating layer under the conductive wiring in which a large potential difference is generated between the conductive wiring and the semiconductor substrate is partially thicker than other portions, and the thick insulating layer portion is oxidized. The insulating layer portion made of a film and having a small thickness is provided with at least an antioxidant layer.
【０００８】この発明の高耐圧半導体装置は、ＤＩ基板
を用いたＩＣ構成のものがあげられるが、これに限ら
ず、通常のシリコン半導体基板を用いたものであっても
よい。この発明の高耐圧半導体装置の基板表面の絶縁層
では、厚みの厚い絶縁層部分の酸化膜厚みＬＡと、少な
くとも酸化防止層を含む厚みの薄い絶縁層部分の厚みＬ
Ｂは、ＬＡ／５≦ＬＢ≦ＬＡ／３の関係であることが好
ましい。The high breakdown voltage semiconductor device of the present invention has an IC configuration using a DI substrate. However, the present invention is not limited to this, and a normal silicon semiconductor substrate may be used. In the insulating layer on the substrate surface of the high breakdown voltage semiconductor device according to the present invention, the oxide film thickness LA of the thick insulating layer portion and the thickness L of the thin insulating layer portion including at least the antioxidant layer are provided.
It is preferable that B has a relationship of LA / 5 ≦ LB ≦ LA / 3.
【０００９】厚い絶縁層部分の酸化膜としてはシリコン
酸化膜があげられ、薄い絶縁層部分の酸化防止層として
は窒化膜などの絶縁物層があげられる。薄い絶縁層部分
の形態は、酸化防止層だけの形態、酸化防止層と薄い酸
化膜層の積層形態があるが、要は酸化防止層があればよ
い。なお、電極形成後に、保護膜である絶縁性パッシベ
ーション膜を厚い絶縁層部分と薄い絶縁層部分の両方に
積層するようにしてもよい。A silicon oxide film is used as the oxide film in the thick insulating layer portion, and an insulating layer such as a nitride film is used as the oxidation preventing layer in the thin insulating layer portion. As the form of the thin insulating layer portion, there are a form of only the antioxidant layer and a laminated form of the antioxidant layer and the thin oxide film layer. After the electrodes are formed, an insulating passivation film serving as a protective film may be laminated on both the thick insulating layer portion and the thin insulating layer portion.
【００１０】この発明の高耐圧半導体装置の基板表面の
絶縁層での厚い絶縁層部分の面積占有率は、絶縁層全体
の１／５以下が好ましく、絶縁層全体の１／１０以下で
あることがより好ましい。[0010] The area occupancy of the thick insulating layer in the insulating layer on the substrate surface of the high breakdown voltage semiconductor device of the present invention is preferably 1/5 or less of the entire insulating layer, and 1/10 or less of the entire insulating layer. Is more preferred.
【００１１】[0011]
【作用】この発明の場合、高耐圧半導体装置の基板表面
の絶縁層の厚い部分は、導電配線のうち半導体基板との
間に大きい電位差が生じる導電配線の下の絶縁層だけで
ある。酸化シリコンは熱膨張率がシリコンのそれの約１
／５と小さく、高温で形成した場合に室温に戻すと、ウ
エハに引っ張り応力が発生する。この応力は酸化膜が厚
くなるほど大きくなるが、この発明の場合のように、基
板の全表面ではなくて、基板表面との間に大きい電位差
が生じる導電配線の下だけの部分面の酸化膜厚みが厚く
なるだけだと、熱膨張率の差による応力が減少するた
め、ＤＩ基板の場合であっても、ウエハの反り量の増加
を抑えられる。勿論、必要な導電配線の下には厚い絶縁
層があるため、耐圧は高い。According to the present invention, the thick portion of the insulating layer on the substrate surface of the high breakdown voltage semiconductor device is only the insulating layer below the conductive wiring where a large potential difference occurs between the conductive wiring and the semiconductor substrate. Silicon oxide has a coefficient of thermal expansion of about 1 that of silicon.
When the temperature is returned to room temperature when formed at a high temperature, tensile stress is generated in the wafer. This stress increases as the thickness of the oxide film increases. However, as in the case of the present invention, the oxide film thickness of the partial surface only under the conductive wiring where a large potential difference occurs between the substrate surface and the entire surface of the substrate is generated. If the thickness is only increased, the stress due to the difference in the coefficient of thermal expansion decreases, so that even in the case of a DI substrate, an increase in the amount of warpage of the wafer can be suppressed. Needless to say, the withstand voltage is high because there is a thick insulating layer below the necessary conductive wiring.
【００１２】この発明の高耐圧半導体装置を得るには、
厚みの厚い領域と厚みの薄い領域のある絶縁層に作製す
る必要があるが、厚みの薄い絶縁層部分は酸化防止層を
少なくとも含むため、この酸化防止層を少なくとも形成
しておいて、ウエハを酸化処理して酸化防止層の未形成
域に厚い酸化膜を形成することで容易に作製できる。し
たがって、この発明の高耐圧半導体装置は製造も容易で
ある。In order to obtain the high breakdown voltage semiconductor device of the present invention,
Although it is necessary to manufacture the insulating layer with a thick region and a thin region, the thin insulating layer portion includes at least an antioxidant layer. It can be easily manufactured by forming a thick oxide film in an area where an antioxidant layer is not formed by performing an oxidation treatment. Therefore, the high breakdown voltage semiconductor device of the present invention is easy to manufacture.
【００１３】[0013]
【実施例】以下、この発明の高耐圧半導体装置の実施例
を説明する。この発明は下記の実施例に限らない。図１
および図２は実施例にかかる高耐圧半導体装置１の要部
構成をあらわしている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the high breakdown voltage semiconductor device of the present invention will be described below. The present invention is not limited to the following embodiments. FIG.
FIG. 2 and FIG. 2 show a main configuration of the high breakdown voltage semiconductor device 1 according to the embodiment.
【００１４】実施例の高耐圧半導体装置１は、ＤＩ基板
２の単結晶シリコンからなるｎ型分離島３にｐｎ接合が
作り込まれている。ＤＩ基板２は、通常、ポリシリコン
層５上に絶縁膜４で電気的に分離された複数のｎ型分離
島３が形成されてなる（図１の場合は便宜上１個だけを
示す）基板であり、他のｎ型分離島にも半導体素子が作
り込まれている。In the high breakdown voltage semiconductor device 1 of the embodiment, a pn junction is formed in an n-type isolation island 3 made of single crystal silicon of a DI substrate 2. The DI substrate 2 is generally a substrate in which a plurality of n-type isolation islands 3 electrically separated by an insulating film 4 are formed on a polysilicon layer 5 (only one is shown in FIG. 1 for convenience). In addition, semiconductor elements have been built in other n-type isolation islands.
【００１５】高耐圧半導体装置１では、ｎ型分離島３の
表面部分にはｐ型領域１３とｎ+ 型領域１４が形成され
ており、かつ、ｎ型分離島３表面では、ｐ型領域１３に
コンタクトするアルミニウム製の電極（導電配線）１６
とｎ+ 型領域１４にコンタクトするアルミニウム製の電
極（導電配線）１７が絶縁層２０を介して分離島外に引
き出されている。この高耐圧半導体装置１では、ｐｎ接
合が逆バイアスされた場合、電極１６とｎ型分離島３の
表面の間の電位差は大きい。In the high breakdown voltage semiconductor device 1, a p-type region 13 and an n + -type region 14 are formed on the surface of the n-type isolation island 3, and the p-type region 13 is formed on the surface of the n-type isolation island 3. Electrode (conductive wiring) 16 contacting the surface
And an electrode (conductive wiring) 17 made of aluminum, which is in contact with the n + -type region 14, is drawn out of the isolation island via an insulating layer 20. In the high breakdown voltage semiconductor device 1, when the pn junction is reverse-biased, the potential difference between the electrode 16 and the surface of the n-type isolation island 3 is large.
【００１６】絶縁層２０は厚みの厚い絶縁層部分２１と
厚みの薄い絶縁層部分２２とからなり、厚い絶縁層部分
２１は酸化膜からなり、薄い絶縁層部分２２は酸化防止
層たる窒化膜である。厚い絶縁層部分２１は高電位差に
なる電極１６の下側だけに部分的に形成されていて、ウ
エハの反り量の低減と高耐圧の確保が図れることは前述
の通りであり、また、厚い絶縁層部分２１以外の部分は
薄い絶縁層部分２２が形成されていて、厚みの厚い・薄
いのある絶縁層２０が簡単に形成できることも前述の通
りである。The insulating layer 20 includes a thick insulating layer portion 21 and a thin insulating layer portion 22. The thick insulating layer portion 21 is formed of an oxide film, and the thin insulating layer portion 22 is formed of a nitride film serving as an antioxidant layer. is there. As described above, the thick insulating layer portion 21 is partially formed only on the lower side of the electrode 16 having a high potential difference, so that the amount of warpage of the wafer can be reduced and a high withstand voltage can be ensured. As described above, a thin insulating layer portion 22 is formed in portions other than the layer portion 21, and the thick and thin insulating layer 20 can be easily formed.
【００１７】この発明は、上記実施例に限らない。例え
ば、図１，２においてｐとｎとが逆である構成のものが
他の実施例として挙げられる。The present invention is not limited to the above embodiment. For example, a configuration in which p and n are opposite in FIGS.
【００１８】[0018]
【発明の効果】以上に述べたように、この発明にかかる
高耐圧半導体装置の場合、基板表面の絶縁層の厚い部分
は、半導体基板との間に大きい電位差が生じる導電配線
の下だけであるため、ウエハの反り量の増加の抑制と高
耐圧化とが図れるのに加え、薄い絶縁層部分には酸化防
止層があって、厚みの厚い領域と厚みの薄い領域のある
絶縁層を簡単に形成できるために製造し易く、したがっ
て、この発明の高耐圧半導体装置は非常に実用性が高
い。As described above, in the high breakdown voltage semiconductor device according to the present invention, the thick portion of the insulating layer on the surface of the substrate is only under the conductive wiring where a large potential difference is generated between the insulating layer and the semiconductor substrate. Therefore, in addition to suppressing the increase in the amount of warpage of the wafer and increasing the withstand voltage, the thin insulating layer portion has an antioxidant layer so that an insulating layer having a thick region and a thin region can be easily formed. Since it can be formed, it is easy to manufacture. Therefore, the high breakdown voltage semiconductor device of the present invention is very practical.
【図１】実施例の高耐圧半導体装置をあらわす断面図で
ある。FIG. 1 is a cross-sectional view illustrating a high breakdown voltage semiconductor device according to an embodiment.
【図２】実施例の高耐圧半導体装置をあらわす平面図で
ある。FIG. 2 is a plan view illustrating a high breakdown voltage semiconductor device according to an embodiment.
【図３】従来の高耐圧半導体装置をあらわす断面図であ
る。FIG. 3 is a cross-sectional view showing a conventional high breakdown voltage semiconductor device.
【図４】従来の高耐圧半導体装置をあらわす平面図であ
る。FIG. 4 is a plan view showing a conventional high breakdown voltage semiconductor device.
１ 高耐圧半導体装置 ２ ＤＩ基板（誘電体分離基板） ３ ｎ型分離島（半導体分離島） ４ 絶縁膜 ５ ポリシリコン層（支持体層） １３ ｐ型領域 １４ ｎ+ 型領域 １６ 電極（導電配線） １７ 電極（導電配線） ２０ 絶縁層 ２１ 厚みの厚い絶縁層部分 ２２ 厚みの薄い絶縁層部分REFERENCE SIGNS LIST 1 high withstand voltage semiconductor device 2 DI substrate (dielectric isolation substrate) 3 n-type isolation island (semiconductor isolation island) 4 insulating film 5 polysilicon layer (support layer) 13 p-type region 14 n + type region 16 electrode (conductive wiring) 17) Electrodes (conductive wiring) 20 Insulating layer 21 Thick insulating layer portion 22 Thin insulating layer portion
───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉浦 義幸 大阪府門真市大字門真1048番地松下電工 株式会社内 (56)参考文献 特開 昭56−79445（ＪＰ，Ａ) 特開 昭61−191042（ＪＰ，Ａ) 特開 平４−64247（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/762 H01L 21/768 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshiyuki Sugiura 1048 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd. (56) References JP-A-56-79445 (JP, A) JP, A) JP-A-4-64247 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/762 H01L 21/768
Claims (2)
た半導体分離島が形成された誘電体分離型の半導体基板
を備え、この基板の表面に絶縁層を介して複数の導電配
線が設けられている半導体装置において、前記導電配線
のうち半導体基板との間に大きい電位差が生じる前記半
導体分離島から直接引き出された導電配線の下の絶縁層
だけは部分的に他の部分より厚みが３〜５倍厚くなって
おり、前記厚みの厚い絶縁層部分は酸化膜からなってい
るとともに厚みの薄い絶縁層部分は少なくとも酸化防止
層が設けられていることを特徴とする高耐圧半導体装
置。An insulating film on a support layer, wherein the insulating layer is electrically separated from the support layer;
A semiconductor substrate having a dielectric isolation type semiconductor substrate having a semiconductor isolation island formed thereon, and a plurality of conductive wirings provided on a surface of the substrate via an insulating layer; The half where a large potential difference occurs between
Only the insulating layer below the conductive wiring directly drawn from the conductor isolation island is partially 3 to 5 times thicker than the other portions, and the thicker insulating layer portion is made of an oxide film. A high breakdown voltage semiconductor device, characterized in that at least an oxidation preventing layer is provided on a thin insulating layer portion.
面積が絶縁層全体の１／５以下であることを特徴とする
請求項１記載の高耐圧半導体装置。2. The occupation of said thick insulating layer portion.
The high breakdown voltage semiconductor device according to claim 1, wherein the area is 1/5 or less of the entire insulating layer .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00797693A JP3242478B2 (en) | 1993-01-20 | 1993-01-20 | High voltage semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00797693A JP3242478B2 (en) | 1993-01-20 | 1993-01-20 | High voltage semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06216233A JPH06216233A (en) | 1994-08-05 |
| JP3242478B2 true JP3242478B2 (en) | 2001-12-25 |
Family
ID=11680491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP00797693A Expired - Fee Related JP3242478B2 (en) | 1993-01-20 | 1993-01-20 | High voltage semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3242478B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0872884A1 (en) * | 1997-04-14 | 1998-10-21 | Harris Corporation | Method and semiconductor device having maximum terminal voltage |
| JPH1129733A (en) * | 1997-07-11 | 1999-02-02 | Mitsubishi Pencil Co Ltd | Ink composition for writing utensil |
-
1993
- 1993-01-20 JP JP00797693A patent/JP3242478B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06216233A (en) | 1994-08-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |