JPS5914650A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain high withstand voltage IC by providing a conductor which is ohmically connected to an n type island through an insulating film at the boundary of the surface of the n type island buried through an n<+> type layer and the insulating film and superposing wirings of the potential different from the island through an insulating film. CONSTITUTION:The surface of the boundary of nB type island 3a buried through an SiO2 film 4a and an n<+> type layer in a polysilicon supporting layer 2 is protected by a thermally oxidized film 5 at the time of forming pE type, pB type and nE type layers, and conductors 7 are deposited simultaneously with electrodes 6a-6c. The layers are insulated therebetween via a CVD SiO2 film 8, holes 9a- 9c are opened and wiring conductors 6'a-6'c which are connected to the electrodes 6a-6c are attached. When the wirings 6' pass over the end surface of the n<+> type layer, the conductors 7 are always existed downwardly. Accordingly, even if one of the wirings 6' is higher at the voltage than the layer 3a, the conductor 7 is disposed at the potential of the nB type layer. In this manner, an electric field is not concentrated in the n<+> type layer, and high withstand voltage can be provided even if the film 5 is thin.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置に係り、特に高耐圧化し、
好適な半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device with high breakdown voltage.
The present invention relates to a suitable semiconductor integrated circuit device.

従来、高耐圧半導体集積回路装置においては誘電体分離
構造が用いられている。コレクタ直列抵抗の低減及び配
線や基板の電位に依存する特性変動を減少させる目的で
高耐圧用誘電体分離基板で紘分離絶縁膜に沿−）７’Ｃ
単結晶島底測定に単結晶島と同一導電型の高不純物濃度
層が一般に設けである。一方誘電体分離基板の単結晶島
が算出している表面上の絶縁膜のうち上記高不純物濃度
層上及びその周辺の厚さを３．〜５μｍに厚膜化しない
と、表面絶縁膜上のアルミニウム（ＡＩ）等の配線が単
結晶島に対して高、電位（ｎ型単結晶島に対しては負の
電位）になりた場合高濃度不純物層に、電界が集中し高
耐圧が得られないという現像が起る。しかし表面絶縁膜
を厚−化することは半導体集積回路装置の製造プロセス
に無理が多く、とくに配線の断線を引き一起す原因とな
る。さらに断差が太き・い為多層配線構造を取ることが
困難で集積度金上げることができない。Conventionally, a dielectric isolation structure has been used in high voltage semiconductor integrated circuit devices. For the purpose of reducing the collector series resistance and characteristic fluctuations depending on the potential of wiring and the substrate, a dielectric isolation substrate for high voltage withstand voltage is used along the isolation insulating film.
To measure the bottom of a single crystal island, a high impurity concentration layer of the same conductivity type as the single crystal island is generally provided. On the other hand, the thickness of the insulating film on the surface of the dielectric isolation substrate, on which the single crystal island is calculated, on and around the high impurity concentration layer is 3. If the film is not thickened to ~5 μm, the wiring made of aluminum (AI) on the surface insulating film will have a high potential with respect to the single crystal island, and will have a high potential (negative potential with respect to the n-type single crystal island). Development occurs in which the electric field is concentrated in the concentrated impurity layer, making it impossible to obtain a high withstand voltage. However, increasing the thickness of the surface insulating film makes the manufacturing process of the semiconductor integrated circuit device unreasonable, and in particular may cause disconnection of wiring. Furthermore, because the difference is wide and narrow, it is difficult to create a multilayer wiring structure, and it is not possible to increase the degree of integration.

本発明の目的はかかる欠点を除去した半導体集積回路装
置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device that eliminates such drawbacks.

本発明の％微は単結晶島の底側面に単結晶と同一導電体
の高不純物濃度層を有する誘電体分離構造において高不
純物濃度層上表面絶縁膜の厚さは０．５〜２μｍ程度の
厚さに形成し、その上に単結晶島にオーミックコンタク
トされた導体を形成する。その導体の単結晶島側の切れ
目は高不純物層。In the present invention, in a dielectric isolation structure having a high impurity concentration layer of the same conductor as the single crystal on the bottom side of a single crystal island, the thickness of the insulating film on the top surface of the high impurity concentration layer is about 0.5 to 2 μm. A conductor is formed thereon in ohmic contact with the single crystal island. The cut on the single crystal island side of the conductor is a highly impurity layer.

炭層以外の表面絶縁膜上に存在する０ その導体上にはＣＶＤ８ｉ０！プラズマ窒化膜。0 present on the surface insulating film other than the carbon layer CVD8i0! on that conductor! Plasma nitride film.

ポリイミド等による絶縁膜を形成し単結晶島に対して高
電位（ｎ型単結晶島に対しては負の電位）となる配線は
全てこの層間絶縁膜上を通すようにする。An insulating film made of polyimide or the like is formed, and all wirings having a high potential with respect to the single crystal island (negative potential with respect to the n-type single crystal island) are passed over this interlayer insulating film.

このようにすれば高濃度不純物層に電界が集中すること
はなくなり高耐圧を得ることができる。In this way, the electric field is not concentrated on the high concentration impurity layer, and a high breakdown voltage can be obtained.

本発明によればフィールド酸化膜が薄くて済むため多層
配線技術を用いることができ、しかも浅接合化も可能で
あるので高集積度の高耐圧半導体装置を実現することが
できる。According to the present invention, since the field oxide film only needs to be thin, multilayer wiring technology can be used, and shallow junctions can also be formed, so that a highly integrated and high breakdown voltage semiconductor device can be realized.

次に図面を用いて本発明について説明する。Next, the present invention will be explained using the drawings.

第１図及び第２図は従来技術を用いて作られた高耐圧半
導体装置で第１図は第２図のＡＡ’の断面図である。図
において１は誘電体分離基板であり、多結晶支持領域２
、複数の単結晶シリコン領域３ａ〜３ｉ１島領域と各島
領域間を絶縁するための、絶縁分離膜４３〜４１から構
成されている。各島領域にはその底側面に単結島領域と
同一導電体の高不純物領域が形成されている。わかりよ
く説明する為にこの図においては単結晶島領域をｎ型半
導体領域、高濃度不純物領域なＡｓ、ＳｂＰ等管拡散又
はイオン注入したｎ＋領領域する。各島領域３ａ〜３Ｍ
には公知のホトリソグラフィ技術や選択拡散技術を用い
て所定の場所に不純物が拡散され、トランジスタやサイ
リスタ等の能動素子あるいは抵抗等の受動素子が組込ま
れている。図では島領域３ａにＰＥ　＊　ＰＢ　＊　　
ｎＢ　＠　　ｎｌの４層によりラテラルサイリスタが組
込まれている例が示されている。基板１の土庄表面には
シリコン酸化膜。1 and 2 are high-voltage semiconductor devices manufactured using conventional technology, and FIG. 1 is a cross-sectional view taken along line AA' in FIG. 2. In the figure, 1 is a dielectric isolation substrate, and a polycrystalline support region 2
, a plurality of single crystal silicon regions 3a to 3i1, and insulating isolation films 43 to 41 for insulating each island region from each other. A highly impurity region of the same conductor as the single island region is formed on the bottom side of each island region. For easy explanation, in this figure, the single crystal island region is an n-type semiconductor region, a high concentration impurity region such as As or SbP, or an n+ region formed by tube diffusion or ion implantation. Each island area 3a to 3M
Impurities are diffused into predetermined locations using known photolithography technology or selective diffusion technology, and active elements such as transistors and thyristors or passive elements such as resistors are incorporated. In the figure, PE * PB * is located in the island area 3a.
An example is shown in which a lateral thyristor is incorporated with four layers of nB@nl. There is a silicon oxide film on the Tonosho surface of the substrate 1.

シリコン酸化膜尋の絶縁膜が設けられており、絶縁膜５
に設けられた開□孔を通してＰＥ層やｎ１層にオーミ、
り４ンタクトする配線６Ｊｌｅ５ｂ、６ｃが絶縁膜５上
に延在している。ζこで絶縁膜５の膜厚が薄いと単結晶
島領域３ａに対し配線６ａ。An insulating film with a thickness of silicon oxide film is provided, and the insulating film 5
Through the open □ hole provided in the PE layer and N1 layer,
Wiring lines 6Jle5b and 6c which are in contact with each other extend on the insulating film 5. ζHere, if the insulating film 5 is thin, the wiring 6a is connected to the single crystal island region 3a.

６ｂ、６とのいずれかが負め高電位であるとき電極の電
界効果により配線の下側の単結晶領域３ａの表面付近の
電界は緩和するが高濃度不純物領域で電界集中を起こし
、耐圧が劣化する。When either 6b or 6 is at a negative high potential, the electric field near the surface of the single crystal region 3a below the wiring is relaxed due to the electric field effect of the electrode, but the electric field is concentrated in the high concentration impurity region, and the withstand voltage is reduced. to degrade.

従って高濃度不純物層域で電界集中を起させない為には
絶縁膜５の膜厚を厚くする必要があった。Therefore, in order to prevent electric field concentration from occurring in the high concentration impurity layer region, it was necessary to increase the thickness of the insulating film 5.

しかし、絶に膜５を厚ぐすることけ半導体集積装−〇製
門プロセスとして好ましくない。すなわち、熱酸化法に
よ秒形成しようとすると拡散の接合が深くなり集積度が
悪くなる。又、気相成長法により８１０．とか５ｉｓＮ
ｎを厚くつける方法をとっても配線の段切れを起しやす
゛い。　□ 第３図、及び第４図は本発明の一実施例を示す。However, since the film 5 is made thicker, this is not preferable as a semiconductor integrated device manufacturing process. That is, if a thermal oxidation method is used to form the semiconductor layer in seconds, the diffusion junction will become deep and the degree of integration will deteriorate. In addition, 810. Or 5isN
Even if the method of thickening n is used, it is easy to cause breaks in the wiring. □ FIGS. 3 and 4 show an embodiment of the present invention.

第３図は第４図のＢＢ／の断面図である。図中の番号の
うち４までは従来技術を用いた高耐圧装置の第１図及び
第２図と全く同じであるので説明を省略する。５はシリ
コン酸化膜、シリコン窒化膜。FIG. 3 is a cross-sectional view of BB/ in FIG. 4. Since the numbers up to 4 in the figure are exactly the same as those in FIGS. 1 and 2 of the high-voltage device using the prior art, their explanation will be omitted. 5 is a silicon oxide film and a silicon nitride film.

Ｐ２Ｏ勢の表面安定化膜であるが従来技術の場合と異な
るのはその厚さが０．５〜２μ程度のもので６３）Ｐｇ
　ｅ　Ｐｉ　＊　　ｎｍ　ｔ−不純物拡散及び酸化によ
り形成する際できる熱酸化膜の厚さに＃１は等しくな−
うていることである。６”＊６ｂｓ６ｃｐそれぞれＰｚ
　＊　”　ｇ　＠　Ｐ＠にオーミックコンタクトされた
電極で高耐圧素子用にフィールドプレー１構造になって
いる。７はｎ型単結晶島３ａにオーミックコンタクトさ
れたＡノ咎の導体でありｎ　高不純物濃度層上の表面安
定化膜５の上に存在する。This is a P2O-based surface stabilizing film, but the difference from the conventional technology is that its thickness is approximately 0.5 to 2μ.63) Pg
e Pi * nm t- #1 is not equal to the thickness of the thermal oxide film formed by impurity diffusion and oxidation.
It is singing. 6”*6bs6cp each Pz
* ” The electrode is in ohmic contact with g@P@, and has a field play 1 structure for high voltage elements. 7 is an A conductor that is in ohmic contact with the n-type single crystal island 3a, and is high in impurity. It exists on the surface stabilizing film 5 on the concentration layer.

この導体７はＯａ、ｆｉｂ、６ｃと同時に蒸着又はスパ
ッタにより形成される。８はＣＶＤ８ｉ０１゜プラズマ
窒化膜、ポリミド等からなる眉間絶縁膜である。５’ａ
　、　６’ｂ　、　６’ｃは配線用導体でありそれぞれ
の電極６ａ、６ｂ、６ｃと層間絶縁膜にあけられたスル
ーホール部９ｇ、９ｂ、９ｃにより接続されている。配
＄６’ａ、　６’ｂ　、　６’ｃがｎ　高不純物層上を
通るときその下側には必ず導体７が存在するようになっ
ている。このような構造をとれば配置６’ａ　、　６’
ｂ　、　６’ｃのいずれかがｎ型単結晶島３ａのｎＢに
対し高電位であっても電界分布は導体７が単結晶島３ａ
のｎＢの電位になっているので導体７の手前で止まり、
高不純物領域のｎ＋層内で電界集中が起らない。従って
表面安定化絶縁物５が薄くても高耐圧化が達成される。This conductor 7 is formed by vapor deposition or sputtering simultaneously with Oa, fib, and 6c. 8 is a glabellar insulating film made of CVD8i01° plasma nitride film, polymide, or the like. 5'a
, 6'b, and 6'c are wiring conductors, and are connected to the respective electrodes 6a, 6b, and 6c through through holes 9g, 9b, and 9c formed in the interlayer insulating film. When the traces 6'a, 6'b, and 6'c pass over the n-high impurity layer, the conductor 7 is always present below it. If such a structure is adopted, the arrangement 6'a, 6'
Even if either b or 6'c has a high potential with respect to nB of the n-type single crystal island 3a, the electric field distribution will be such that the conductor 7 is the same as the single crystal island 3a.
Since the potential is nB, it stops before the conductor 7,
Electric field concentration does not occur within the n+ layer of the highly impurity region. Therefore, even if the surface stabilizing insulator 5 is thin, a high breakdown voltage can be achieved.

このことは単結晶島がｐ型の場合も成り立つ。又、導体
７はＡＩ等の電極材のみでなく不純物をｄｅｐｅ　した
。This also holds true when the single crystal island is p-type. Furthermore, the conductor 7 was depeated not only from electrode materials such as AI but also from impurities.

多結晶Ｓｔでもよい。Polycrystalline St may also be used.

上記実施例からも明らかなように、本発明によれば高耐
圧半導体集積回路装置に多層配線構造が適用でき高集積
度のものが得られチップサイズを小さくすることが可能
となる。As is clear from the above embodiments, according to the present invention, a multilayer wiring structure can be applied to a high voltage semiconductor integrated circuit device, a high degree of integration can be obtained, and the chip size can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の高耐圧半導体集積回路装置の断面図、第
２図はその平面図、第３図は本発明実施例の半導体集積
回路装置の断面図、第４図はその平面図、である。 なお図において、１−・・・・・誘電体分離基板、２・
・・・・・多結晶支持体領域、３ａ〜３１単結晶島領域
、４ａ〜４１・・・・・・絶縁分離膜、５・・・・・・
絶縁膜、６ａ。 ５ｂ　、５ｃ・・・・・・電極及び一層目の配線、ｅ／
　ａ　、　５’　ｂ　＋６／ｃ・・・・・・２層目の配
線、７・・・・・・導体、８・・・・・：Ｎ間絶縁膜、
９　ａ　、　９　ｂ　、　９　ｃ−−−−°−スルーホ
ール、である。 第１図 第３図FIG. 1 is a sectional view of a conventional high-voltage semiconductor integrated circuit device, FIG. 2 is a plan view thereof, FIG. 3 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 4 is a plan view thereof. be. In the figure, 1-...dielectric isolation substrate, 2-...
...Polycrystal support region, 3a to 31 single crystal island region, 4a to 41...Insulating separation film, 5...
Insulating film, 6a. 5b, 5c... Electrode and first layer wiring, e/
a, 5' b +6/c... 2nd layer wiring, 7... Conductor, 8...: N interlayer insulating film,
9a, 9b, 9c---°-through hole. Figure 1 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 半導体支持体領域Ｋｌｌ＋ｘの絶縁膜を介して複数個の
増結晶領域が前記支持領域上の一主面に算出するように
埋設され、各領域には前記第１の絶縁膜に但りて各単結
晶島領域と同一導電型で高不紳物濃度の層を有し、前記
−主面表面上に第２の絶縁膜を有する誘電体分離基板に
多層配置ｆｉ構造を用いた半導体集積回路装置において
、前記高不純物濃度層を低不純物濃度単結晶領域の境界
上には前記第２の絶縁膜を介して前記各単結晶島領域に
オーミックコンタクトされた導体が存在し、且つ前記各
単結晶島領域の電位と異なる配線が第３の絶縁膜を介し
て前記導体上に存在することを特徴とする半導体集積回
路装置。A plurality of crystallization regions are embedded in one main surface of the support region via the insulating film of the semiconductor support region Kll+x, and each region is provided with a respective unit in the first insulating film. In a semiconductor integrated circuit device using a multilayer FI structure on a dielectric isolation substrate having a layer having the same conductivity type as the crystal island region and having a high impurity concentration, and having a second insulating film on the main surface. , a conductor is present on the boundary between the high impurity concentration layer and the low impurity concentration single crystal region, and is in ohmic contact with each of the single crystal island regions via the second insulating film; A semiconductor integrated circuit device, characterized in that a wiring having a different potential exists on the conductor via a third insulating film.