JP2998507B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2998507B2
JP2998507B2 JP5215520A JP21552093A JP2998507B2 JP 2998507 B2 JP2998507 B2 JP 2998507B2 JP 5215520 A JP5215520 A JP 5215520A JP 21552093 A JP21552093 A JP 21552093A JP 2998507 B2 JP2998507 B2 JP 2998507B2
Authority
JP
Japan
Prior art keywords
semiconductor element
electrode
metal projection
metal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5215520A
Other languages
Japanese (ja)
Other versions
JPH0766243A (en
Inventor
哲郎 河北
賢造 畑田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP5215520A priority Critical patent/JP2998507B2/en
Publication of JPH0766243A publication Critical patent/JPH0766243A/en
Application granted granted Critical
Publication of JP2998507B2 publication Critical patent/JP2998507B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関するものであり、特に半導体素子等の高密度化、薄型
化、小型化を達成するための実装技術に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a mounting technique for achieving high density, thinness, and miniaturization of a semiconductor element and the like.

【０００２】[0002]

【従来の技術】近年、半導体素子を多数個用いる電子機
器が急増してきている。例えば、メモリーカード、液晶
やＥＬディスプレイ等があり、これらはいずれも複数個
のＬＳＩチップを一定面積を有する基板上に高密度にし
かも薄型に搭載しなければならない。このようにＬＳＩ
チップを高密度に実装する有効な手段としてマイクロバ
ンプボンディング方式（以下ＭＢＢ方式と呼称する）が
ある。2. Description of the Related Art In recent years, electronic devices using a large number of semiconductor elements have been rapidly increasing. For example, there are a memory card, a liquid crystal display, an EL display, and the like, all of which require a plurality of LSI chips to be mounted on a substrate having a fixed area at a high density and a low thickness. Thus, LSI
As an effective means for mounting chips at high density, there is a micro-bump bonding method (hereinafter referred to as MBB method).

【０００３】この方式は、ＬＳＩチップのＡＬ電極上に
形成された金属突起電極と配線基板の配線電極とを光硬
化性の絶縁樹脂によって圧接する方式であり、樹脂の収
縮力のみで両者の電極同士を電気的に接続している。In this method, a metal projection electrode formed on an AL electrode of an LSI chip and a wiring electrode of a wiring board are pressed against each other with a photocurable insulating resin. They are electrically connected to each other.

【０００４】この方式では、ＬＳＩチップのＡＬ電極上
に金属突起電極を形成する必要があり、この金属突起を
形成する方法として、従来はＬＳＩチップのＡＬ電極上
にＣｒ−ＣｕやＴｉ−Ｐｄ等のバリヤメタルと呼ばれる
多層金属膜を形成し、この上に電解めっき法でバンプと
呼ばれる金属突起を形成する方法で行なっていた。In this method, it is necessary to form a metal projection electrode on the AL electrode of the LSI chip. As a method of forming the metal projection, conventionally, a Cr-Cu, Ti-Pd or the like is formed on the AL electrode of the LSI chip. In this method, a multilayer metal film called a barrier metal is formed, and a metal projection called a bump is formed thereon by electrolytic plating.

【０００５】しかし、このようにＬＳＩチップのＡＬ電
極上に金属突起を形成するのには、多数の蒸着工程やフ
ォトリソ工程、エッチング工程が実施される。そのた
め、これらの工程の途中において、ＬＳＩチップに損傷
を与え、歩留まりを低下させる原因になったり、全体的
に実装コストを高くするばかりか信頼性をも低下させる
ものであった。さらには、この金属突起を形成したＬＳ
Ｉチップを入手するのが困難であり、非常に汎用性に欠
けるといった欠点があった。However, in order to form the metal projection on the AL electrode of the LSI chip, a number of vapor deposition steps, photolithography steps, and etching steps are performed. Therefore, in the course of these steps, the LSI chip is damaged, which causes a reduction in the yield, and not only increases the mounting cost but also lowers the reliability as a whole. Further, the LS having the metal protrusion formed thereon
There is a drawback that it is difficult to obtain an I chip and the versatility is very low.

【０００６】これらの課題を解決する方法として、ＬＳ
ＩチップのＡＬ電極上に、別途作成された金属突起を転
写して、直接接合する方法がある。前述のＭＢＢ方式の
工程と合わせて、この工程を以下に、図３を用いて詳し
く説明する。As a method of solving these problems, LS
There is a method in which a separately formed metal projection is transferred onto the AL electrode of the I-chip and directly joined. This step, together with the above-described step of the MBB method, will be described below in detail with reference to FIG.

【０００７】図３は上記方法における工程断面図であ
り、２１は金属突起形成用基板、２２はＡｕよりなる金
属突起、２３は半導体素子、２４はＡｌよりなる半導体
素子の電極である。この時、金属突起形成用基板２１は
耐熱性のガラスで、熱膨張係数が4.0×10-6／℃程度の
ものを用いている。FIG. 3 is a sectional view of the process in the above method, wherein 21 is a substrate for forming a metal projection, 22 is a metal projection made of Au, 23 is a semiconductor element, and 24 is an electrode of a semiconductor element made of Al. At this time, the metal projection forming substrate 21 is made of heat-resistant glass having a thermal expansion coefficient of about 4.0 × 10 −6 / ° C.

【０００８】工程としては、まず図３（ａ）に示す様に
金属突起形成用基板２１と半導体素子２３とを、金属突
起形成用基板２１上の金属突起２２と半導体素子２３の
Ａｌ電極２４とが相対する様に位置合わせする。In the process, first, as shown in FIG. 3A, the metal projection forming substrate 21 and the semiconductor element 23 are connected to the metal projection 22 on the metal projection forming substrate 21 and the Al electrode 24 of the semiconductor element 23. Align so that they face each other.

【０００９】そして同図（ｂ）に示すように、金属突起
２２とＡｌ電極２４とをボンディングツール２５によっ
て加圧、加熱する。ボンディングツール２５は底面の平
面度が常温時で１μｍ以下程度のものを使用している。
この加圧、加熱により金属突起形成用基板２１上の金属
突起２２は半導体素子２３のＡｌ電極２４上に接合さ
れ、同図（ｃ）に示す様に、ボンディングツール２５に
付けられている真空吸着孔２６によって半導体素子２３
を吸着する事によって金属突起形成用基板２１から半導
体素子２３を引き剥すと金属突起２２はＡｌ電極２４に
転写、接合される。Then, as shown in FIG. 1B, the metal projection 22 and the Al electrode 24 are pressed and heated by a bonding tool 25. As the bonding tool 25, a tool having a flatness of the bottom surface of about 1 μm or less at room temperature is used.
By this pressurization and heating, the metal projection 22 on the metal projection forming substrate 21 is joined to the Al electrode 24 of the semiconductor element 23, and as shown in FIG. The semiconductor element 23 is formed by the hole 26.
When the semiconductor element 23 is peeled off from the metal projection forming substrate 21 by sucking the metal projections, the metal projections 22 are transferred and joined to the Al electrode 24.

【００１０】ここで、Ａｕからなる金属突起２２とＡｌ
電極２４とは両者の界面層でわずかのＡｕ−Ａｌ合金を
形成して接合されている。また、金属突起２２の形状や
大きさは形成時と転写後とではあまり変わらないもので
ある。すなわち、両者の界面層でわずかのＡｕーＡｌ合
金を形成するのに必要なだけの温度と圧力と時間だけし
かかけていない。具体的には温度は約３８０〜４６０
℃、圧力は１金属突起当り７〜１０ｇ、時間は１秒であ
る。Here, a metal projection 22 made of Au and Al
The electrode 24 is joined by forming a slight Au-Al alloy at the interface layer between them. Further, the shape and size of the metal projection 22 are not so different between the time of formation and the time of transfer. That is, only the temperature, pressure, and time necessary to form a small amount of Au-Al alloy at the interface layer between the two are required. Specifically, the temperature is about 380-460
C., pressure is 7 to 10 g per metal projection, and time is 1 second.

【００１１】次に、同図（ｄ）に示すように金属突起２
２が転写、接合された半導体素子２３とこの金属突起２
２に対応した位置に配線電極２７を有する配線基板２８
とを位置合わせするとともに、配線基板２８上の半導体
素子２３が位置する領域に光硬化性絶縁樹脂２９を塗布
する。Next, as shown in FIG.
2 is transferred and bonded to the semiconductor element 23 and the metal projection 2
2 having wiring electrode 27 at a position corresponding to 2
And a photo-curable insulating resin 29 is applied to a region on the wiring substrate 28 where the semiconductor element 23 is located.

【００１２】この後、同図（ｅ）に示すように常温の加
圧ツール３０によって金属突起２２を配線電極２７に圧
接する。この時、間に介在していた光硬化性絶縁樹脂２
９は周囲に押しやられて、金属突起２２と配線電極２７
とは電気的に完全に接続がとられた状態となる。また、
このとき金属突起２２は大きく変形させる必要がある。
たとえば、加圧前に約１０μｍ程度あった金属突起２２
は４〜５μｍ程度までに変形させる。これに必要な荷重
は１金属突起当り９０〜１００ｇである。Thereafter, as shown in FIG. 1E, the metal projection 22 is pressed against the wiring electrode 27 by the press tool 30 at room temperature. At this time, the photocurable insulating resin 2 interposed
9 is pushed to the periphery, and the metal protrusion 22 and the wiring electrode 27 are pressed.
Is a state in which the connection is completely established electrically. Also,
At this time, the metal projection 22 needs to be largely deformed.
For example, a metal protrusion 22 having a thickness of about 10 μm
Is deformed to about 4 to 5 μm. The load required for this is 90-100 g per metal projection.

【００１３】この後、同図（ｆ）に示すように配線基板
２８の裏面もしくは側面から紫外線３１を照射し、光硬
化性絶縁樹脂２９を硬化させる。この後、加圧を解除し
て接続は終了する（同図（ｇ））。Thereafter, as shown in FIG. 1F, ultraviolet rays 31 are irradiated from the back surface or side surface of the wiring board 28 to cure the photocurable insulating resin 29. Thereafter, the pressurization is released and the connection is terminated ((g) in the figure).

【００１４】このように従来技術では配線基板２８と半
導体素子２３との接合を無加熱で圧接し、両者を光硬化
性絶縁樹脂２９で固定することにより、従来までに課題
とされていた点を改善し、以下に示すような特徴を有し
ている。As described above, in the prior art, the bonding between the wiring board 28 and the semiconductor element 23 is press-contacted without heating, and the two are fixed with the photo-curable insulating resin 29, which has been a problem which has been a problem in the past. It has improved and has the following features.

【００１５】即ち、（ａ）無加熱接続であるため熱的ス
トレスを与えることなく接続できる。（ｂ）接続部が圧
接（接触）されているだけなので熱膨張係数の差による
接合部での熱的ストレスを受けない。（ｃ）接続部が金
属結合を有した接合ではないので狭ピッチに対応でき
る、と言う特徴を有している。(A) Since the connection is made without heating, connection can be made without applying thermal stress. (B) Since the connection portion is merely pressed (contacted), no thermal stress is applied to the connection portion due to a difference in thermal expansion coefficient. (C) It has a feature that it can cope with a narrow pitch because the connection portion is not a junction having a metal bond.

【００１６】[0016]

【発明が解決しようとする課題】しかしながら上記のよ
うな従来方法では、以下に示すような問題点がある。こ
れを図４とともに説明する。However, the above-mentioned conventional method has the following problems. This will be described with reference to FIG.

【００１７】まず、図４（ａ）に示す接合工程では、金
属突起形成用基板２１上に形成された金属突起２２は半
導体素子２３のＡｌ電極２４と位置合わせされ、半導体
素子２３の裏面より加熱されたボンディングツール２５
によって加圧する際、ボンディングツール２５から供給
される熱が半導体素子２３及び金属突起２２を介して金
属突起形成用基板２１に伝わる。この時金属突起形成用
基板２１は熱による膨張を起こし、上に凸の形状に変化
してしまう。First, in the bonding step shown in FIG. 4A, the metal projection 22 formed on the metal projection forming substrate 21 is aligned with the Al electrode 24 of the semiconductor element 23 and heated from the back surface of the semiconductor element 23. Bonding tool 25
When pressure is applied, the heat supplied from the bonding tool 25 is transmitted to the metal projection forming substrate 21 via the semiconductor element 23 and the metal projection 22. At this time, the metal projection forming substrate 21 expands due to heat, and changes to an upwardly convex shape.

【００１８】また、ボンディングツール２５は常温にて
そのボンディング面の平面度が維持されているが、ボン
ディングを行う温度である３８０〜４６０℃の高温では
その平面度は維持されない。一般的には常温で平面なボ
ンディング面は、高温になると材料の熱膨張係数の差に
より凸状に変形する。この状態で金属突起２２が半導体
素子２３のＡＬ電極２４上に転写接合されるため、転写
後の金属突起２２の形状は図４（ｂ）に示すように半導
体素子２３のコーナー部で金属突起２２の高さが高くな
る現象が生じる。The flatness of the bonding surface of the bonding tool 25 is maintained at a normal temperature, but the flatness is not maintained at a high temperature of 380 to 460 ° C., which is the bonding temperature. Generally, a bonding surface that is flat at normal temperature is deformed in a convex shape at a high temperature due to a difference in thermal expansion coefficient of a material. In this state, the metal projection 22 is transfer-bonded onto the AL electrode 24 of the semiconductor element 23, so that the shape of the metal projection 22 after the transfer is at the corner of the semiconductor element 23 as shown in FIG. A phenomenon occurs in which the height becomes higher.

【００１９】この時の高さばらつきは接合条件にもよる
が、金属突起２２の径が３０μｍで高さが１０μｍの場
合、約３μｍ程度生じる。これは次工程に用いるＭＢＢ
方式のようにフェイスダウンで配線基板に直接接合する
ものでは大きく影響し、接続不良を起こす原因となる。The height variation at this time is about 3 μm when the diameter of the metal projection 22 is 30 μm and the height is 10 μm, although it depends on the joining conditions. This is the MBB used in the next step
Direct bonding to the wiring board in a face-down manner, as in the system, has a large effect and causes a connection failure.

【００２０】また、フェイスダウン方式で接続する際、
電気的な接続を確実ならしめて、この接続不良をなくす
ために、過剰な荷重をかけて金属突起２２を大きく変形
させる場合があるが、これは接続部や半導体素子２３に
大きな歪みを与えるために接続信頼性を著しく低下させ
る原因となる。When connecting in a face-down manner,
In order to secure the electrical connection and eliminate this connection failure, an excessive load may be applied to the metal projection 22 to greatly deform it. This may cause a significant decrease in connection reliability.

【００２１】本発明は、上記課題を解決した半導体装置
の製造方法を提供することを目的とする。An object of the present invention is to provide a method of manufacturing a semiconductor device which solves the above problems.

【００２２】[0022]

【課題を解決するための手段】上記問題点を解決するた
めに本発明は、熱膨張係数が0.5×10-6／℃以下の絶縁
性基板上に半導体素子のＡｌ電極に対応した位置にのみ
形成された金属突起と前記半導体素子のＡｌ電極とを位
置合わせする工程、前記半導体素子の裏面より加熱され
た加圧面の平面度が0.5μｍ以下の加圧冶具によって加
圧する工程、加圧を除去し、前記絶縁性基板上に形成さ
れていた前記金属突起を前記半導体素子のＡｌ電極上に
転写、接合を完了する工程、前記金属突起と配線基板の
配線電極とを接続する工程とを備えたこと特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is directed to an insulating substrate having a coefficient of thermal expansion of 0.5 × 10 −6 / ° C. or less only at a position corresponding to an Al electrode of a semiconductor element. A step of aligning the formed metal protrusions with the Al electrode of the semiconductor element, a step of pressing with a pressing jig having a flatness of 0.5 μm or less in flatness of a pressing surface heated from the back surface of the semiconductor element, and removing the pressing. Transferring the metal protrusions formed on the insulating substrate onto the Al electrode of the semiconductor element, completing the bonding, and connecting the metal protrusions to the wiring electrodes of the wiring board. It is characterized.

【００２３】[0023]

【作用】本発明では金属突起をＡｌ電極上に転写、接合
する工程において、金属突起形成用基板に熱膨張係数が
0.5×10-6／℃以下の低熱膨張係数の基板を用い、ボン
ディングツールには接合温度で平面度が0.5μｍ以下の
ものを用いることによって、転写時の熱によって生じる
金属突起形成用基板及びボンディングツールの熱膨張を
抑え、転写後の金属突起の高さばらつきを0.5μｍ以下
を達成する。According to the present invention, in the step of transferring and joining metal projections on an Al electrode, the substrate for forming metal projections has a coefficient of thermal expansion.
A substrate of low thermal expansion coefficient of 0.5 × 10 -6 / ℃ or less by using those flatness of 0.5μm or less at the bonding temperature for the bonding tool, arising metal protrusion formed by the heat during transfer The thermal expansion of the substrate for use and the bonding tool is suppressed, and the variation in height of the metal projections after transfer is 0.5 μm or less.

【００２４】[0024]

【実施例】以下、本発明の一実施例を図１、２とともに
説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

【００２５】図１は本発明の一実施例における半導体装
置の製造方法の工程を説明する断面図である。製造方法
としてはまず、同図（ａ）に示すように金属突起形成用
基板２１と半導体素子２３とを、金属突起形成用基板２
１上の金属突起２２と半導体素子２３のＡｌ電極２４と
が相対する様に位置合わせする。FIG. 1 is a sectional view for explaining steps of a method of manufacturing a semiconductor device according to one embodiment of the present invention. As a manufacturing method, first, as shown in FIG. 2A, the metal projection forming substrate 21 and the semiconductor element 23 are connected to the metal projection forming substrate 2.
Positioning is performed such that the metal protrusion 22 on the first and the Al electrode 24 of the semiconductor element 23 face each other.

【００２６】ここで用いる金属突起形成用基板２１の詳
細な構造を図２に示す。金属突起形成用基板２１は３層
構造よりなっている。絶縁性基板４０上全面に透明導電
膜４１が形成されている。絶縁性基板４０には石英基板
を用いており、その熱膨張係数は0.5×10-6／℃であ
る。透明導電膜４１にはＩＴＯ（インジウムティンオキ
サイド）膜を用いた。FIG. 2 shows the detailed structure of the metal projection forming substrate 21 used here. The metal projection forming substrate 21 has a three-layer structure. A transparent conductive film 41 is formed on the entire surface of the insulating substrate 40. A quartz substrate is used as the insulating substrate 40, and its thermal expansion coefficient is 0.5 × 10 −6 / ° C. As the transparent conductive film 41, an ITO (indium tin oxide) film was used.

【００２７】この透明導電膜４１上に感光性の絶縁性樹
脂４２を形成し、半導体素子２３のＡｌ電極２４に対応
した位置にのみ露光、現像工程を施すことにより、開口
部４３を形成する。この後透明導電膜４１を一方の電極
としてＡｕの電解めっき法により開口部４３内部に金属
突起２２を形成した構造を有している。また、感光性の
絶縁性樹脂４２にはポジ型のフォトレジストやポリイミ
ド樹脂等を用いた。形成した金属突起２２を半導体素子
２３上に転写する場合には、めっき用のマスクに使用し
た絶縁性樹脂４２は除去して使用する。An opening 43 is formed by forming a photosensitive insulating resin 42 on the transparent conductive film 41 and exposing and developing only a position corresponding to the Al electrode 24 of the semiconductor element 23. Thereafter, the transparent conductive film 41 is used as one electrode to form a metal projection 22 inside the opening 43 by Au electroplating. In addition, a positive photoresist, a polyimide resin, or the like was used for the photosensitive insulating resin 42. When transferring the formed metal protrusion 22 onto the semiconductor element 23, the insulating resin 42 used for the plating mask is removed before use.

【００２８】そして同図（ｂ）に示すように、金属突起
２２とＡｌ電極２４とを加圧ツール４５によって加圧す
る。加圧ツール４５は約３８０℃〜４８０℃に加熱され
ているが、加圧面がこの加熱温度で平面度０．５μｍ以
下を保証されたものを用いている。また、加圧ツール４
５より供給されるされる熱は、半導体素子２３、ＡＬ電
極２４、金属突起２２を介して金属突起形成用基板２１
に伝わるが、この金属突起形成用基板２１には熱膨張係
数0.5×10-6／℃という低熱膨張係数の石英基板を用い
ているため、熱による膨張、変形というのは上記の温度
範囲ではほとんど無い。Then, as shown in FIG. 2B, the metal projection 22 and the Al electrode 24 are pressed by a pressing tool 45. The pressing tool 45 is heated to about 380 ° C. to 480 ° C., and a tool whose pressing surface has a flatness of 0.5 μm or less at this heating temperature is used. Pressing tool 4
5 is supplied to the metal projection forming substrate 21 through the semiconductor element 23, the AL electrode 24, and the metal projection 22.
However, since a quartz substrate having a low coefficient of thermal expansion of 0.5 × 10 −6 / ° C. is used for the metal projection forming substrate 21, expansion and deformation due to heat hardly occur in the above temperature range. There is no.

【００２９】これら２つの作用によって金属突起２２は
精度良くかつ高さばらつきもなくＡＬ電極２４上に転
写、接合される。この接合工程では金属突起形成用基板
２１上の金属突起２２と半導体素子２３のＡｌ電極２４
とはその界面で十分に両者が変形し合って圧接され、金
属突起２２とＡｌ電極２４の間にはＡｕ−Ａｌ合金が形
成される。By these two actions, the metal projection 22 is transferred and joined onto the AL electrode 24 with high accuracy and without any variation in height. In this bonding step, the metal projection 22 on the metal projection forming substrate 21 and the Al electrode 24 of the semiconductor element 23 are formed.
Are sufficiently deformed and pressed against each other at the interface, and an Au-Al alloy is formed between the metal projection 22 and the Al electrode 24.

【００３０】このときの荷重および加熱、時間はそれぞ
れ２０〜５０ｇ／バンプ、３８０〜４８０℃、１〜３ｓ
ｅｃである。特に荷重は金属突起のサイズによって異な
るがはぼＡｌ電極の厚みの約１／３〜２／３まで金属突
起が押し込まれる荷重に設定する必要がある。At this time, the load, heating and time are respectively 20 to 50 g / bump, 380 to 480 ° C., and 1 to 3 s.
ec. In particular, the load varies depending on the size of the metal projection, but it is necessary to set the load at which the metal projection is pushed down to about 1/3 to 2/3 of the thickness of the Al electrode.

【００３１】その後同図（ｃ）に示すように加圧ツール
４５を解除したのち真空吸着孔を有した搬送治具４４に
よって半導体素子２３を引き上げると金属突起２２のＡ
ｌ電極２４への転写、接合は完了している。Thereafter, as shown in FIG. 3C, after the pressing tool 45 is released, the semiconductor element 23 is pulled up by the transfer jig 44 having a vacuum suction hole , and the A of the metal projection 22 is removed.
The transfer and bonding to the 1 electrode 24 have been completed.

【００３２】次に、同図（ｄ）に示すように金属突起２
２が転写、接合された半導体素子２３とこの金属突起２
２に対応した位置に配線電極２７を有する配線基板２８
とを位置合わせする。この場合配線基板２８にはシリコ
ン基板やガラス基板を用い、配線電極２７材料としては
Ｃｒ−Ａｕ、Ｔｉ−Ｐｄ−Ａｕ、ＩＴＯ等を用いる。Next, as shown in FIG.
2 is transferred and bonded to the semiconductor element 23 and the metal projection 2
2 having wiring electrode 27 at a position corresponding to 2
And position. In this case, a silicon substrate or a glass substrate is used as the wiring substrate 28, and Cr-Au, Ti-Pd-Au, ITO, or the like is used as a material of the wiring electrode 27.

【００３３】この後、配線基板２８の配線電極２７が形
成されている領域に光硬化性絶縁樹脂２９を塗布する。
しかる後、同図（ｅ）に示すように常温の加圧ツール３
０によって半導体素子２３と配線基板２８を圧接し、配
線基板２８の裏面もしくは側面から紫外線３１を照射し
光硬化性絶縁樹脂２９を硬化させる（同図（ｆ））。こ
の後、加圧を解除して接続は終了する（同図（ｇ））。Thereafter, a photocurable insulating resin 29 is applied to the region of the wiring substrate 28 where the wiring electrodes 27 are formed.
Thereafter, as shown in FIG.
The semiconductor element 23 and the wiring board 28 pressed by 0, distribution
The photocurable insulating resin 29 is cured by irradiating ultraviolet rays 31 from the back surface or side surface of the wire substrate 28 (FIG. 4F). Thereafter, the pressurization is released and the connection is terminated ((g) in the figure).

【００３４】[0034]

【発明の効果】以上述べたように本発明には以下に示す
様な効果がある。半導体素子のＡＬ電極上に突起電極を
容易にかつ低コストで形成できる転写方式においてボン
ディングツールに接合温度での平面度が０．５μｍ以
下、金属突起形成用基板に熱膨張係数が0.5×10-6／℃
以下のものを用いることによって、基板上に精度良く形
成された金属突起を高さばらつきを生じること無く、高
精度で半導体素子のＡｌ電極上に転写接合できる。ま
た、金属突起とＡｌ電極両者の界面での接合においても
きわめて良好でかつ安定したＡｕ−Ａｌ接合を行うこと
が可能となり、信頼性も著しく向上させることができ
る。また、この方式により本発明をフリップチップ方式
やＭＢＢ方式に適用する場合、半導体装置全体の接続信
頼性を大幅に向上させることが出来る。As described above, the present invention has the following effects. In a transfer method in which a protruding electrode can be easily and inexpensively formed on an AL electrode of a semiconductor element, the flatness at a bonding temperature of a bonding tool is 0.5 μm or less, and the coefficient of thermal expansion is 0.5 × 10 − 6 / ℃
By using the following, it is possible to transfer and join a metal projection accurately formed on a substrate to an Al electrode of a semiconductor element with high accuracy without causing a height variation. In addition, it is possible to perform extremely good and stable Au-Al bonding even at the bonding at the interface between both the metal projection and the Al electrode, and it is possible to significantly improve the reliability. Further, when the present invention is applied to the flip-chip method or the MBB method by this method, the connection reliability of the entire semiconductor device can be greatly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施例における半導体装置の製造方法
を表す工程断面図FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図２】同実施例における金属突起形成用基板の断面図FIG. 2 is a sectional view of the substrate for forming metal protrusions in the embodiment.

【図３】従来例における半導体装置の製造方法を表す工
程断面図FIG. 3 is a process sectional view illustrating a method for manufacturing a semiconductor device in a conventional example.

【図４】同従来例における接合部の拡大断面図FIG. 4 is an enlarged sectional view of a joint in the conventional example.

【符号の説明】[Explanation of symbols]

２１ 金属突起形成用基板 ２２ 金属突起 ２３ 半導体素子 ２４ Ａｌ電極 ２５ ボンディングツール２６ 真空吸着孔 ２７ 配線電極 ２８ 配線基板 ２９ 光硬化性絶縁樹脂 ３０ 加圧ツール ３１ 紫外線 ４０ 絶縁性基板 ４１ 透明導電膜 ４２ 絶縁性樹脂 ４３ 開口部４４ 搬送治具 ４５ 加圧ツールReference Signs List 21 Metal projection forming substrate 22 Metal projection 23 Semiconductor element 24 Al electrode 25 Bonding tool 26 Vacuum suction hole 27 Wiring electrode 28 Wiring board 29 Photocurable insulating resin 30 Press tool 31 Ultraviolet 40 Insulating substrate 41 Transparent conductive film 42 Insulation Resin 43 Opening 44 Transporting jig 45 Pressing tool

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】熱膨張係数が0.5×10-6／℃以下の絶縁性
基板上に半導体素子のＡｌ電極に対応した位置に形成さ
れた金属突起と前記半導体素子のＡｌ電極とを位置合わ
せする工程と、その後、前記半導体素子の裏面より、加
熱された加圧面の平面度が0.5μｍ以下の加圧冶具によ
って加圧して、前記絶縁性基板上に形成された前記金属
突起と前記半導体素子のＡｌ電極との接触面とを接合す
る工程と、その後、前記半導体素子と前記絶縁性基板と
を離間せしめて、前記金属突起を前記絶縁性基板から剥
離して前記半導体素子側に転写する工程を有した半導体
装置の製造方法。A metal projection formed on an insulating substrate having a coefficient of thermal expansion of 0.5 × 10 −6 / ° C. or less at a position corresponding to an Al electrode of a semiconductor element is aligned with the Al electrode of the semiconductor element. And after that, from the back surface of the semiconductor element, the flatness of the heated pressing surface is pressurized by a pressing jig of 0.5 μm or less, and the metal projection formed on the insulating substrate and the semiconductor element are pressed. A step of joining the contact surface with the Al electrode, and thereafter, a step of separating the semiconductor element and the insulating substrate, separating the metal projection from the insulating substrate, and transferring the metal projection to the semiconductor element side. Of manufacturing a semiconductor device having the same. 【請求項２】熱膨張係数が0.5×10-6／℃以下の絶縁性
基板上に半導体素子のＡｌ電極に対応した位置に形成さ
れた金属突起と前記半導体素子のＡｌ電極とを位置合わ
せする工程と、その後、前記半導体素子の裏面より、加
熱された加圧面の平面度が0.5μｍ以下の加圧冶具によ
って加圧して、前記絶縁性基板上に形成された前記金属
突起と前記半導体素子のＡｌ電極との接触面とを接合す
る工程と、その後、前記半導体素子と前記絶縁性基板と
を離間せしめて、前記金属突起を前記絶縁性基板から剥
離して前記半導体素子側に転写する工程と、その後、前
記金属突起と配線基板の配線電極とを接続する工程とを
備えたこと特徴とする半導体装置の製造方法。2. The method according to claim 1, wherein the metal projection formed on the insulating substrate having a coefficient of thermal expansion of 0.5 × 10 −6 / ° C. or less at a position corresponding to the Al electrode of the semiconductor element is aligned with the Al electrode of the semiconductor element. And after that, from the back surface of the semiconductor element, the flatness of the heated pressing surface is pressurized by a pressing jig of 0.5 μm or less, so that the metal protrusions formed on the insulating substrate and the semiconductor element A step of joining the contact surface with the Al electrode, and thereafter, a step of separating the semiconductor element and the insulating substrate, separating the metal protrusion from the insulating substrate, and transferring the metal projection to the semiconductor element side. Connecting the metal protrusion to a wiring electrode of a wiring board, and thereafter, connecting the metal projection to a wiring electrode of the wiring board. 【請求項３】配線基板と半導体素子の間を絶縁性樹脂に
より固着することを特徴とした請求項２記載の半導体装
置の製造方法。3. The method according to claim 2, wherein the wiring substrate and the semiconductor element are fixed with an insulating resin.
JP5215520A 1993-08-31 1993-08-31 Method for manufacturing semiconductor device Expired - Fee Related JP2998507B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5215520A JP2998507B2 (en) 1993-08-31 1993-08-31 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5215520A JP2998507B2 (en) 1993-08-31 1993-08-31 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0766243A JPH0766243A (en) 1995-03-10
JP2998507B2 true JP2998507B2 (en) 2000-01-11

Family

ID=16673781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5215520A Expired - Fee Related JP2998507B2 (en) 1993-08-31 1993-08-31 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2998507B2 (en)

Also Published As

Publication number Publication date
JPH0766243A (en) 1995-03-10

Similar Documents

Publication Publication Date Title
JP2833326B2 (en) Electronic component mounted connector and method of manufacturing the same
JP2730357B2 (en) Electronic component mounted connector and method of manufacturing the same
JPH027180B2 (en)
JPH09330950A (en) Semiconductor device and its manufacture
JPH09129669A (en) Electric connection structure between semiconductor chip and substrate
JP2770821B2 (en) Semiconductor device mounting method and mounting structure
JP3269390B2 (en) Semiconductor device
JP2989696B2 (en) Semiconductor device and mounting method thereof
JP2003124262A (en) Method of manufacturing semiconductor device
JPH0357617B2 (en)
JP2998507B2 (en) Method for manufacturing semiconductor device
JPH06268098A (en) Manufacture of semiconductor integrated circuit device
JP2002231765A (en) Semiconductor device
JPH01192125A (en) Mounting structure of semiconductor device
JP2002134541A (en) Semiconductor device and its fabrication method and packaging structure of the device
JP2959215B2 (en) Electronic component and its mounting method
JP3752829B2 (en) Bonding method of liquid crystal display panel and semiconductor chip
KR20000011643A (en) Device and method for connecting two electronic components
JPH0714843A (en) Manufacture of semiconductor device
JP3051617B2 (en) Method for manufacturing semiconductor device
JP2674786B2 (en) IC mounting method and mounting apparatus
JPH05275485A (en) Protruding electrode and its manufacture and packaging body using said protruding electrode
JPH05326525A (en) Manufacture of bump electrode
JP2001284387A (en) Semiconductor device and method of manufacture, and mounting structure of the semiconductor device
JPH02280349A (en) Bump forming and connecting method

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees