JP2581542B2 - Semiconductor nonvolatile memory and method of manufacturing the same - Google Patents
Semiconductor nonvolatile memory and method of manufacturing the sameInfo
- Publication number
- JP2581542B2 JP2581542B2 JP61148649A JP14864986A JP2581542B2 JP 2581542 B2 JP2581542 B2 JP 2581542B2 JP 61148649 A JP61148649 A JP 61148649A JP 14864986 A JP14864986 A JP 14864986A JP 2581542 B2 JP2581542 B2 JP 2581542B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate electrode
- film
- control gate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】 この発明は、コンピューターなどの電子機器に用いら
れる半導体不揮発性メモリに関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory used for electronic equipment such as a computer.
この発明は、浮遊ゲート電極と制御ゲート電極とから
なる２層ゲート構造の半導体不揮発性メモリとその製造
方法において、２層ゲート構造形成後高温CVD膜で全面
形成することにより高集積化に容易な信頼性の高い半導
体不揮発性メモリを与えるものである。The present invention provides a semiconductor nonvolatile memory having a two-layer gate structure including a floating gate electrode and a control gate electrode, and a method for manufacturing the same. This provides a highly reliable semiconductor nonvolatile memory.
従来、第２図に示すように、ソース・ドレイン領域間
のチャネル領域上にゲート絶縁膜４を介して浮遊ゲート
電極５及び制御ゲート電極７を積層にした構造の半導体
不揮発性メモリにおいて、浮遊ゲート電極５の端部から
制御ゲート電極７への揮発電流を防ぐために、制御ゲー
ト電極７を形成した後に全面に高品質な熱酸化膜10を10
00℃以上で形成し、さらに全面に層間絶縁膜（例えばPS
G膜）９を形成した構造になっている。Conventionally, as shown in FIG. 2, in a semiconductor nonvolatile memory having a structure in which a floating gate electrode 5 and a control gate electrode 7 are laminated on a channel region between a source and a drain region via a gate insulating film 4, After the control gate electrode 7 is formed, a high-quality thermal oxide film 10 is deposited on the entire surface after the control gate electrode 7 is formed in order to prevent a volatile current from flowing from the end of the electrode 5 to the control gate electrode 7.
Formed at a temperature of at least 00 ° C.
G film) 9 is formed.
しかし、従来の半導体不揮発性メモリは、制御ゲート
電極７の形成後熱酸化膜10を形成するために、両ゲート
電極が酸化される結果、浮遊ゲート電極５及び制御ゲー
ト電極７の形状が熱酸化後変形してしまうために、微細
化パターンの形成が困難である。またソース・ドレイン
領域も熱酸化温度が1000℃以上と高いと、熱拡散によっ
てソース・ドレイン領域が大きくなってしまい高集積化
に適した半導体不揮発性メモリではなかった。However, in the conventional semiconductor non-volatile memory, both the gate electrodes are oxidized to form the thermal oxide film 10 after the formation of the control gate electrode 7, so that the shapes of the floating gate electrode 5 and the control gate electrode 7 are thermally oxidized. Since it is deformed later, it is difficult to form a miniaturized pattern. Also, if the thermal oxidation temperature of the source / drain region is as high as 1000 ° C. or higher, the source / drain region becomes large due to thermal diffusion, and is not a semiconductor nonvolatile memory suitable for high integration.
そこで、この発明は、従来のこのような欠点を解決す
るためゲート電極及びソース・ドレイン領域が変形しな
いような半導体不揮発性メモリを得ることを目的とし
た。Accordingly, an object of the present invention is to provide a semiconductor nonvolatile memory in which the gate electrode and the source / drain regions are not deformed in order to solve the conventional disadvantages.
上記問題点を解決するために、この発明は、制御ゲー
ト電極形成後、高品質な高温CVD膜を全面形状すること
により高集積化に適した信頼性の高い半導体不揮発性メ
モリを可能にした。In order to solve the above problems, the present invention enables a highly reliable semiconductor non-volatile memory suitable for high integration by forming a high-quality high-temperature CVD film over the entire surface after forming a control gate electrode.
上記のように構成された半導体不揮発性メモリの場
合、浮遊ゲート電極形成後、1000℃より低温で形成され
る高品質のCVD膜を全面に形成するために、浮遊ゲート
電極及びソース・ドレイン領域の変形を小さく形成で
き、その結果、高集積化に適した高品質な半導体不揮発
性メモリが実現できる。In the case of the semiconductor nonvolatile memory configured as described above, after forming the floating gate electrode, in order to form a high-quality CVD film formed at a temperature lower than 1000 ° C. over the entire surface, the floating gate electrode and the source / drain regions are formed. The deformation can be formed small, and as a result, a high-quality semiconductor nonvolatile memory suitable for high integration can be realized.
以下に、この発明の実施例を第１図に用いて説明す
る。第１図は、本発明の半導体不揮発性メモリの断面図
である。Ｐ型シリコン基板１の表面に互いに間隔をおい
てN+型のソース領域２及びドレイン領域３が形成され、
ゲート絶縁膜４を介して浮遊ゲート電極５が形成され、
浮遊ゲート電極５の上に制御ゲート絶縁膜６を介して浮
遊ゲート電極５の電位を制御する制御ゲート電極７が形
成されている。制御ゲート電極７を形成後、1000℃より
低い温度で形成された第１のCVD絶縁膜である高温CVD膜
を全面に形成し、さらに、900℃以下で形成する第２のC
VD絶縁膜である低温絶縁膜９が形成されている。高温CV
D膜は、800℃以上のジクロルシランと亜酸化チッソとの
反応、例えばSiH2Cl2＋2N2O→SiO2＋2HCl＋2N2の反応で
形成すると高品質な酸化膜を形成できる。また、低温絶
縁膜９は、PSG膜など低温で形成できる膜であり、熱酸
化で成長する膜ではない。特に、浮遊ゲート電極５のパ
ターニングを制御ゲート電極７をマスクにして行った構
造においては、浮遊ゲート電極５のエッヂ部の酸化膜が
エッチングされてしまうため、浮遊ゲート電極５の中の
電荷が基板１あるいは制御ゲート電極７へ揮発しやすく
なる。しかし、高温CVD膜を形成することにより、浮遊
ゲート電極５の側面をCVD膜で覆うことができる。この
ため、浮遊ゲート電極５から他の電極への揮発は防止で
きる。この高温CVD膜は、熱酸化膜と異なりCVD膜である
ために、その下の構造形状の変化をきわめて少なくする
ことができる。膜厚としては、200Å以上あれば充分な
信頼性が得られる。低温絶縁膜９も、この高品質な高温
CVD膜で形成することは技術的に可能であるが、形成す
る時間が長く実用的でない。An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a sectional view of a semiconductor nonvolatile memory according to the present invention. An N + -type source region 2 and a drain region 3 are formed on the surface of a P-type silicon substrate 1 at an interval from each other,
A floating gate electrode 5 is formed via the gate insulating film 4,
A control gate electrode 7 for controlling the potential of the floating gate electrode 5 is formed on the floating gate electrode 5 via a control gate insulating film 6. After forming the control gate electrode 7, a high-temperature CVD film as a first CVD insulating film formed at a temperature lower than 1000 ° C. is formed on the entire surface, and a second C film formed at 900 ° C. or lower is formed.
A low-temperature insulating film 9 as a VD insulating film is formed. High temperature CV
The D film can form a high-quality oxide film when formed by a reaction between dichlorosilane at 800 ° C. or higher and nitrogen suboxide, for example, a reaction of SiH 2 Cl 2 + 2N 2 O → SiO 2 + 2HCl + 2N 2 . The low-temperature insulating film 9 is a film that can be formed at a low temperature such as a PSG film, and is not a film grown by thermal oxidation. In particular, in a structure in which the floating gate electrode 5 is patterned using the control gate electrode 7 as a mask, the oxide film at the edge of the floating gate electrode 5 is etched, so that the charges in the floating gate electrode 5 are removed from the substrate. 1 or to the control gate electrode 7. However, by forming the high-temperature CVD film, the side surface of the floating gate electrode 5 can be covered with the CVD film. Therefore, volatilization from the floating gate electrode 5 to another electrode can be prevented. Since this high-temperature CVD film is a CVD film unlike a thermal oxide film, a change in the structural shape thereunder can be extremely reduced. If the film thickness is 200 mm or more, sufficient reliability can be obtained. The low-temperature insulating film 9 is also made of this high-quality high-temperature
Although it is technically possible to form a CVD film, it takes a long time to form the film and is not practical.
また、一般的には、浮遊ゲート電極５及び制御ゲート
電極７は多結晶シリコン膜が用いられているが、本発明
においては、モリブテン，タングステンなど熱酸化困難
な高融点金属電極にも適用できる。また、絶縁膜９はPS
Gなど従来用いられている層間絶縁膜を使用すればよ
い。In general, a polycrystalline silicon film is used for the floating gate electrode 5 and the control gate electrode 7, but the present invention can be applied to a high melting point metal electrode such as molybdenum and tungsten which is difficult to thermally oxidize. The insulating film 9 is made of PS
A conventionally used interlayer insulating film such as G may be used.
この発明は、以上説明したように、浮遊ゲート電極を
用いた半導体不揮発性メモリにおいて、浮遊ゲート電極
及び制御ゲート電極形成後、高温CVD膜により、浮遊ゲ
ート電極と他の領域との揮発電流を防止でき、また高温
CVD形成時の温度が低いため構造変化が少ない高集積化
に適した信頼性の高い半導体不揮発性メモリを可能にす
る効果がある。As described above, according to the present invention, in a semiconductor nonvolatile memory using a floating gate electrode, after a floating gate electrode and a control gate electrode are formed, a high-temperature CVD film prevents a volatile current between the floating gate electrode and another region. Can and also high temperature
Since the temperature at the time of CVD formation is low, there is an effect of enabling a highly reliable semiconductor non-volatile memory suitable for high integration with little structural change.
本発明は、二層電極構造の浮遊ゲート型半導体不揮発
性メモリに特に有効であるが、一層浮遊ゲート電極の半
導体不揮発性メモリへ適用できることは言うまでもな
い。The present invention is particularly effective for a floating gate type semiconductor nonvolatile memory having a two-layer electrode structure, but it is needless to say that the present invention is applicable to a semiconductor nonvolatile memory having a single layer floating gate electrode.
第１図は、この発明にかかる半導体不揮発性メモリの断
面図であり、第２図は、従来の半導体不揮発性メモリの
断面図である。 １……基板 ２……ソース領域 ３……ドレイン領域 ５……浮遊ゲート電極 ７……制御ゲート電極FIG. 1 is a sectional view of a semiconductor nonvolatile memory according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor nonvolatile memory. DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Source region 3 ... Drain region 5 ... Floating gate electrode 7 ... Control gate electrode
Claims (6)
て設けられた第２導電型のソース領域とドレイン領域
と、前記ソース・ドレイン領域間の前記半導体基板上に
ゲート絶縁膜を介して設けられた浮遊ゲート電極と、前
記浮遊ゲート電極と制御ゲート絶縁膜を介して設けられ
た制御ゲート電極と、少なくとも前記制御ゲート電極の
上と側部に順次形成された第１の絶縁膜及び第２の絶縁
膜とからなるとともに、前記第１の絶縁膜は、前記第２
の絶縁膜より高温で形成され、800℃以上で1000℃以下
の温度で形成されたCVD膜であることを特徴とする半導
体不揮発性メモリ。A source region and a drain region of a second conductivity type which are provided on a surface of a semiconductor substrate of a first conductivity type at an interval, and a gate insulating film is provided on the semiconductor substrate between the source and drain regions. A floating gate electrode provided, a control gate electrode provided with the floating gate electrode and a control gate insulating film interposed therebetween, and a first insulating film sequentially formed on at least the top and side portions of the control gate electrode; and A second insulating film, and the first insulating film is formed of the second insulating film.
A non-volatile semiconductor memory, wherein the non-volatile memory is a CVD film formed at a temperature higher than 800 ° C. and lower than 1000 ° C.
でいることを特徴とする特許請求の範囲第１項記載の半
導体不揮発性メモリ。2. The semiconductor nonvolatile memory according to claim 1, wherein said control gate electrode includes a refractory metal film.
00Åであることを特徴とする特許請求の範囲第１項記載
の半導体不揮発性メモリ。3. The method according to claim 1, wherein said first CVD insulating film has a thickness of at least two.
2. The non-volatile semiconductor memory according to claim 1, wherein the angle is 00 °.
て第２導電型のソース領域とドレイン領域を形成する工
程と、 前記半導体表面にゲート絶縁膜を形成する工程と、 前記ゲート絶縁膜の上に浮遊ゲート電極となる多結晶シ
リコン膜を形成する工程と、 前記の多結晶シリコン膜の上に制御ゲート絶縁膜を形成
する工程と、 前記制御ゲート絶縁膜上に制御ゲート電極となる導電膜
を形成する工程と、 前記多結晶シリコン膜、前記制御ゲート絶縁膜及び前記
導電膜を部分的にエッチングして前記浮遊ゲート電極と
前記制御ゲート電極を形成する工程と、 前記制御ゲート電極が形成された半導体基板の上に800
℃以上で1000℃以下の温度で第１の絶縁膜を少なくとも
前記制御ゲート電極の上と側部に堆積する工程と、 前記制御ゲート電極の上の前記第１の絶縁膜を介して第
１の絶縁膜の形成温度より低い温度で第２の絶縁膜を形
成する工程とからなる半導体不揮発性メモリの製造方
法。4. A step of forming a source region and a drain region of a second conductivity type at intervals on a surface of a semiconductor substrate of a first conductivity type; a step of forming a gate insulating film on the semiconductor surface; Forming a polycrystalline silicon film to be a floating gate electrode on the film; forming a control gate insulating film on the polycrystalline silicon film; forming a control gate electrode on the control gate insulating film A step of forming a conductive film; a step of partially etching the polycrystalline silicon film, the control gate insulating film and the conductive film to form the floating gate electrode and the control gate electrode; 800 on the formed semiconductor substrate
Depositing a first insulating film at least on the control gate electrode and at a side portion at a temperature of not less than 1000 ° C. and not more than 1000 ° C., and a first insulating film formed on the control gate electrode through the first insulating film. Forming a second insulating film at a temperature lower than the forming temperature of the insulating film.
点金属膜からなることを特徴とする特許請求の範囲第４
項記載の半導体不揮発性メモリの製造方法。5. The semiconductor device according to claim 4, wherein said conductor film is made of a polycrystalline silicon film or a high melting point metal film.
14. The method for manufacturing a semiconductor nonvolatile memory according to item 13.
ランガスと亜酸化チッソガスとの反応によりシリコン酸
化膜を形成する工程である特許請求の範囲第４項記載の
半導体不揮発性メモリの製造方法。6. The method according to claim 4, wherein the step of forming the first insulating film is a step of forming a silicon oxide film by a reaction between dichlorosilane gas and nitrogen dioxide gas. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61148649A JP2581542B2 (en) | 1986-06-25 | 1986-06-25 | Semiconductor nonvolatile memory and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61148649A JP2581542B2 (en) | 1986-06-25 | 1986-06-25 | Semiconductor nonvolatile memory and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS635570A JPS635570A (en) | 1988-01-11 |
| JP2581542B2 true JP2581542B2 (en) | 1997-02-12 |
Family
ID=15457524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61148649A Expired - Lifetime JP2581542B2 (en) | 1986-06-25 | 1986-06-25 | Semiconductor nonvolatile memory and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2581542B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6034021A (en) * | 1983-08-05 | 1985-02-21 | Hitachi Ltd | Protective film forming apparatus |
| JPS6066435A (en) * | 1983-09-22 | 1985-04-16 | Matsushita Electric Ind Co Ltd | Forming method of thin-film |
| JPS60242615A (en) * | 1984-05-17 | 1985-12-02 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0697695B2 (en) * | 1984-11-16 | 1994-11-30 | 株式会社日立製作所 | Method for manufacturing semiconductor integrated circuit device |
| JPS62235786A (en) * | 1986-04-04 | 1987-10-15 | Mitsubishi Electric Corp | Mos type semiconductor device and manufacture thereof |
-
1986
- 1986-06-25 JP JP61148649A patent/JP2581542B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS635570A (en) | 1988-01-11 |
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