JP2534967B2 - Method for forming shallow junction of semiconductor device by double implantation - Google Patents
Method for forming shallow junction of semiconductor device by double implantationInfo
- Publication number
- JP2534967B2 JP2534967B2 JP5147674A JP14767493A JP2534967B2 JP 2534967 B2 JP2534967 B2 JP 2534967B2 JP 5147674 A JP5147674 A JP 5147674A JP 14767493 A JP14767493 A JP 14767493A JP 2534967 B2 JP2534967 B2 JP 2534967B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon layer
- source
- implantation
- implanting
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 39
- 238000002513 implantation Methods 0.000 title claims description 24
- 239000004065 semiconductor Substances 0.000 title claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 43
- 229910052710 silicon Inorganic materials 0.000 claims description 43
- 239000010703 silicon Substances 0.000 claims description 43
- 239000012535 impurity Substances 0.000 claims description 22
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- 238000006073 displacement reaction Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、二重注入（Ｄｏｕｂｌ
ｅ Ｉｍｐｌａｎｔａｔｉｏｎ）による半導体素子の浅
い接合の形成方法に関するものであり、特に、半導体素
子で浅い接合を形成するためにシリコン層に１段階で４
９ＢＦ2 ソースを注入し、２段階で１１Ｂソースを注入
する、浅い接合の形成方法に関するものである。FIELD OF THE INVENTION The present invention relates to double injection (Double).
The present invention relates to a method for forming a shallow junction of a semiconductor device by means of an e-implantation method, and in particular, in order to form a shallow junction in a semiconductor device, the step of forming a shallow junction in a silicon layer is performed in four steps.
The present invention relates to a method for forming a shallow junction in which a 9BF 2 source is injected and an 11B source is injected in two steps.
【０００２】[0002]
【従来の技術】一般的に半導体素子の製造のとき、１つ
のタイプを持つシリコン層に他のタイプを持つ不純物ソ
ースを注入して接合を形成する。たとえば、ＰＭＯＳＦ
ＥＴを形成するためには、Ｎ型シリコン層の上部にゲー
ト酸化膜とゲート電極を形成し、Ｐタイプの不純物ソー
スをシリコン層に注入してソース／ドレインを形成す
る。2. Description of the Related Art Generally, in manufacturing a semiconductor device, a junction is formed by implanting an impurity source having another type into a silicon layer having one type. For example, PMOSF
To form ET, a gate oxide film and a gate electrode are formed on an N-type silicon layer, and a P-type impurity source is implanted into the silicon layer to form a source / drain.
【０００３】しかしながら、不純物ソースがかなり深く
シリコン層に注入されて深い接合（Ｄｅｅｐ Ｊｕｎｃ
ｔｉｏｎ）を形成する場合、サブミクロン（Ｓｕｂ−Ｍ
ｉｃｒｏｎ）級のＭＯＳＦＥＴでは、ショートチャンネ
ル効果（Ｓｈｏｒｔ Ｃｈａ１ｎｅｌ Ｅｆｆｅｃ
ｔ）、深いパンチスルー（Ｄｅｅｐ Ｐｕｎｃｈ−Ｔｈ
ｒｏｕｇｈ）によるリーク電流の増加、消費電力の増加
および耐圧（Ｂｒｅａｋ−Ｄｏｗｎ Ｖｏｌｔａｇｅ）
が低下する、といった短所が発生する。However, the impurity source is injected into the silicon layer considerably deeply and deep junction (Deep Junc) is performed.
sub-micron (Sub-M)
The short channel effect (Short Cha1nel Effec) is used in the (icron) class MOSFET.
t), deep punch-through (Deep Punch-Th)
increase in leak current, increase in power consumption and breakdown voltage (Break-Down Voltage)
However, there are disadvantages such as decrease in
【０００４】従来の技術によって、Ｎ型シリコン層にＰ
型不純物ソースを予定の条件で注入して接合を形成する
方法は次のとおりである。By the conventional technique, P is formed on the N-type silicon layer.
A method of implanting a type impurity source under predetermined conditions to form a junction is as follows.
【０００５】第１は、１１Ｂをたとえば３０〜３５Ｋｅ
Ｖエネルギーと、１×１０12ｃｍ-2のドース（ｄｏｓ
ｅ）量（不純物注入量）でＮ型シリコン層に注入する方
法がある。First, 11B is, for example, 30 to 35 Ke.
V energy and 1 × 10 12 cm -2 dose (dos)
e) There is a method of implanting an amount (impurity implant amount) into the N-type silicon layer.
【０００６】第２は、１段階で１１Ｂをたとえば３０〜
３５ＫｅＶエネルギーと、１×１０11ｃｍ-2の不純物注
入量でＮ型シリコン層に注入し、２段階で１１Ｂをたと
えば３０〜３５ＫｅＶエネルギーと、１×１０12ｃｍ-2
の不純物注入量でＮ型シリコン層に注入する方法があ
る。Second, 11B in one step, for example 30 ~.
35 KeV energy and 1 × 10 11 cm −2 impurity implantation amount are implanted into the N-type silicon layer, and 11B is provided in two steps, for example, 30 to 35 KeV energy and 1 × 10 12 cm −2.
There is a method of implanting into the N-type silicon layer with the impurity implantation amount of.
【０００７】第３は、４９ＢＦ2 をたとえば４５ＫｅＶ
エネルギーと、１×１０12ｃｍ-2の不純物注入量でＮ型
シリコン層に注入する方法等がある。[0007] Third, 49 BF 2 is, for example, 45 KeV
There is a method of implanting into the N-type silicon layer with energy and an impurity dose of 1 × 10 12 cm -2 .
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上記の
方法で接合を形成する場合、いろいろの問題点が発生す
る。However, when forming a bond by the above method, various problems occur.
【０００９】第１の方法は、一番簡単な接合を形成する
方法であるが、半導体素子の製造のとき、Ｐ−チャンネ
ルのしきい値（ｔｈｒｅｓｈｏｌｄ）電圧だけでなく、
Ｎ−チャンネルのしきい値電圧をも考慮すべきであるの
で、Ｎ−チャンネルのしきい値電圧を調節のための追加
的な工程が必要となる。The first method, which is the simplest method of forming a junction, is not limited to the threshold voltage of the P-channel in the manufacture of semiconductor devices.
Since the N-channel threshold voltage should also be considered, an additional step for adjusting the N-channel threshold voltage is required.
【００１０】第２の方法は、Ｎ−チャンネルのしきい値
電圧を調節する注入工程とＰ−チャンネルのしきい値電
圧を調節する注入工程のとき、注入される不純物注入量
を適当に調節し、上記の第１の方法の短所を補完した方
法である。この第２の方法は、上記の第１の方法と同様
に、１１Ｂソースがもたらす特性のため、深い接合（Ｄ
ｅｅｐ Ｊｕｎｃｔｉｏｎ）が形成される。The second method is to appropriately adjust the amount of impurities to be injected during the implantation process for adjusting the threshold voltage of the N-channel and the implantation process for adjusting the threshold voltage of the P-channel. This is a method that complements the disadvantages of the first method described above. This second method, like the first method above, has a deep junction (D
eeep Junction) is formed.
【００１１】第３の方法は、大きい質量値を持つ４９Ｂ
Ｆ2 ソースをシリコン層に注入することによって、シリ
コン層の表面に損傷（ｄａｍａｇｅ）を与えることにな
る。この損傷は、キャリアを捕獲（ｔｒａｐｐｉｎｇ）
する役割をすることになって、移動度が減少する現象が
発生する。また、４９ＢＦ2 ソースは飛程（ｐａｔｈｌ
ｅｎｇｔｈ）が短いので、全体的なドーパント（ｄｏｐ
ａｎｔ）の均一性の制御が難しい。The third method is 49B having a large mass value.
Implanting the F 2 source into the silicon layer will damage the surface of the silicon layer. This damage traps carriers.
As a result, the phenomenon that the mobility is reduced occurs. In addition, the 49BF 2 source has a range (pathl
Due to its short length, the overall dopant (dop)
It is difficult to control the uniformity of ant).
【００１２】上記の従来の技術でシリコン層に不純物ソ
ースを注入した後、シリコン層の損傷程度をテストした
ＴＷマップ（Ｔｈｅｒｍａｌ Ｗａｖｅ Ｍａｐ）によ
って測定した標準偏差と、シリコン層に不純物ソースを
注入させた後、９５０℃で３０分アニールした後、接合
の深さを測定したデータを表１に示す。After implanting the impurity source into the silicon layer by the conventional technique described above, the standard deviation measured by the TW map (Thermal Wave Map) in which the degree of damage to the silicon layer was tested, and the impurity source were implanted into the silicon layer. After that, after annealing at 950 ° C. for 30 minutes, data of measuring the junction depth are shown in Table 1.
【００１３】[0013]
【表１】 上記の表１で表したとおり、第２の方法はＴＷマップの
標準偏差が一番小さいが接合の深さが深く、第３の方法
は接合の深さは一番浅いがＴＷマップの標準偏差が一番
大きく表れることがわかる。[Table 1] As shown in Table 1 above, the second method has the smallest standard deviation of the TW map but the deepest junction depth, and the third method has the smallest junction depth but the standard deviation of the TW map. You can see that is the largest.
【００１４】本発明の目的は、上記の従来技術の接合深
さが深くなる問題点と、イオン注入されるドーパントの
均一性を表すＴＷマップの標準偏差が大きく表れる問題
点を解決することができる、二重注入による半導体素子
の浅い接合の形成方法を提供することにある。The object of the present invention is to solve the above-mentioned problems of deepening the junction depth and the problem that the standard deviation of the TW map showing the uniformity of the implanted dopant is large. A method of forming a shallow junction of a semiconductor device by double implantation is provided.
【００１５】[0015]
【課題を解決するための手段】この発明による二重注入
による半導体素子の浅い接合の形成方法は、注入工程に
より半導体素子の接合領域を形成する方法において、Ｎ
型シリコン層に１段階で４９ＢＦ2 ソースを４５ＫｅＶ
のエネルギと２．０×１０11ｃｍ-2の不純物注入量で注
入する工程と、２段階で１１Ｂソースを３５ＫｅＶのエ
ネルギと１．１５×１０12ｃｍ-2の不純物注入量で注入
する工程とを備え、１段階の４９ＢＦ2ソースのシリコ
ン層への注入により、シリコン層の表面でＢＦ2 ソース
が衝突してＢとＦ2 イオンに分離されてシリコン層内に
注入されながら、シリコン層の単結晶シリコン格子構造
に格子変位が発生して疑似アモルファス領域に変化する
ことを特徴としている。A method of forming a shallow junction of a semiconductor device by double implantation according to the present invention is a method of forming a junction region of a semiconductor device by an implantation process, wherein N
-Type silicon layer with one step of 49BF 2 source 45 KeV
Energy and an impurity implantation amount of 2.0 × 10 11 cm −2 , and a step of implanting an 11B source with energy of 35 KeV and an impurity implantation amount of 1.15 × 10 12 cm −2 in two steps. The single step implantation of the 49BF 2 source into the silicon layer allows the BF 2 source to collide with the surface of the silicon layer to be separated into B and F 2 ions and to be implanted into the silicon layer. It is characterized in that a lattice displacement occurs in the crystalline silicon lattice structure and changes into a pseudo-amorphous region.
【００１６】[0016]
【作用】本発明によれば、４９ＢＦ2 の短い飛程と大き
い質量によってシリコン層の一定の深さが格子変位（Ｌ
ａｔｔｉｃｅ Ｓｈｉｆｔ）される特性と、１１Ｂソー
スの注入されたドーパントの均一性の制御が容易である
という特性を利用している。According to the present invention, due to the short range of 49 BF 2 and the large mass, a constant depth of the silicon layer can cause a lattice displacement (L
The characteristic is that it is easily shifted and the uniformity of the implanted dopant of the 11B source is easily controlled.
【００１７】[0017]
【実施例】以下、本発明の一実施例を、添付した図面を
参照して説明すれば次のとおりである。DESCRIPTION OF THE PREFERRED EMBODIMENTS The following will describe one embodiment of the present invention with reference to the accompanying drawings.
【００１８】本発明は、Ｎ型シリコン層に１段階で４９
ＢＦ2 ソースを、４５ＫｅＶエネルギーにて２．０×１
０11ｃｍ-2の不純物注入量で注入した後、２段階で１１
Ｂソースを３５ＫｅＶエネルギーにて１．１５×１０12
ｃｍ-2の不純物注入量で注入する方法である。The present invention provides a 49-step N-type silicon layer in one step.
BF 2 source 2.0 × 1 at 45 KeV energy
After implantation with an impurity implantation amount of 0 11 cm -2 , 11 in 2 steps
B source at 35 KeV energy 1.15 × 10 12
This is a method of implanting with an impurity dose of cm −2 .
【００１９】図１は、本発明の一実施例によりＮ型シリ
コン層に１段階注入工程で４９ＢＦ2 ソースを注入する
ことにより、単結晶シリコン結晶構造に格子変位が発生
した状態を示す図である。FIG. 1 is a diagram showing a state where lattice displacement occurs in a single crystal silicon crystal structure by implanting a 49BF 2 source into an N-type silicon layer in a one-step implantation process according to an embodiment of the present invention. .
【００２０】図１を参照して、本発明によりＮ型シリコ
ン層に４９ＢＦ2 ソースを１段階に注入すれば、４９Ｂ
Ｆ2 ソースがシリコン層に衝突する場合１１Ｂ＋３８Ｆ
2 に分離され、シリコン層の単結晶シリコン格子構造の
うちに浸透されながら単結晶シリコン格子構造１が変位
して疑似（ｑｕａｓｉ）アモルファス領域２が形成され
る。Referring to FIG. 1, if a 49BF 2 source is injected in one step into an N-type silicon layer according to the present invention, 49B 2
When the F 2 source collides with the silicon layer 11B + 38F
The single crystal silicon lattice structure 1 is separated into two and is permeated into the single crystal silicon lattice structure of the silicon layer to displace the single crystal silicon lattice structure 1 to form a quasi amorphous region 2.
【００２１】ここで、シリコン層の上部面を完全にアモ
ルファス格子構造に作ることになれば、２段階での１１
Ｂ注入のときシリコン層の上部面に注入されたＢイオン
が止まる効果は大きくなるが、後継ぎ工程の熱処理工程
でも損傷されたシリコン層の表面が完全に補償されない
ので、移動度が落ちる要因となる。したがって、１段階
の注入工程のときは、シリコン層に損傷を与えないなが
ら、格子変位を起こすことのできる程度に制御すべきで
ある。Here, if the upper surface of the silicon layer is to be completely formed into an amorphous lattice structure, it will be 11 in two steps.
The effect of stopping the B ions implanted into the upper surface of the silicon layer at the time of the B implantation is large, but the surface of the damaged silicon layer is not completely compensated even in the heat treatment step of the subsequent step, which causes a decrease in mobility. . Therefore, during the one-step implantation process, the lattice displacement should be controlled so as not to damage the silicon layer.
【００２２】図２は、本発明の一実施例によりシリコン
層に１段階注入工程後、２段階注入工程で１１Ｂソース
をシリコン層に注入した状態を示す図である。FIG. 2 is a view showing a state in which the 11B source is implanted into the silicon layer by the two-stage implantation process after the one-stage implantation process into the silicon layer according to one embodiment of the present invention.
【００２３】図２を参照して、本発明により１１Ｂソー
スを２段階注入し、２段階注入されるＢイオンが疑似ア
モルファス領域２に多く捕獲され、その下部の単結晶シ
リコン格子構造１の一部分まで、一部のＢイオンが注入
された不純物が注入された領域３ができる。また、図２
より、不純物が注入されて形成される接合の深さは、疑
似アモルファス領域２の深さよりは大きく増大されない
ことがわかる。Referring to FIG. 2, according to the present invention, the 11B source is injected in two steps, and the B ions injected in two steps are mostly captured in the pseudo-amorphous region 2, and up to a part of the single crystal silicon lattice structure 1 thereunder. A region 3 in which some B ions are implanted and impurities are implanted is formed. FIG.
From this, it can be seen that the depth of the junction formed by implanting impurities is not increased to a greater extent than the depth of the pseudo-amorphous region 2.
【００２４】上記の本発明により、シリコン層に不純物
ソースを２段階注入した後、注入工程のときシリコン層
の損傷程度をテストしたＴＷマップ（Ｔｈｅｒｍａｌ
Ｗａｖｅ Ｍａｐ）により測定された標準偏差（δ）は
０．３８％であり、シリコン層に不純物ソースを２段階
注入した後、９５０℃で３０分間アニールした後、接合
の深さを測定してみると０．３８μｍであった。すなわ
ち、本発明は従来の技術と比較して、注入工程のときシ
リコン層の損傷程度をテストした標準偏差が一番小さ
い。これは、ドーパントの均一性が向上されることを意
味する。また、アニール工程の後の接合の深さは、従来
技術の第３の方法による接合の深さと同一に浅い接合を
実現することができる。According to the present invention described above, a TW map (Thermal) in which the degree of damage to the silicon layer is tested during the implantation process after implanting the impurity source into the silicon layer in two steps.
The standard deviation (δ) measured by Wave Map is 0.38%, and after implanting the impurity source into the silicon layer in two steps, annealing is performed at 950 ° C. for 30 minutes, and then the junction depth is measured. And was 0.38 μm. That is, the present invention has the smallest standard deviation in which the degree of damage to the silicon layer is tested during the implantation process, as compared with the prior art. This means that the uniformity of the dopant is improved. Also, the junction depth after the annealing step can be as shallow as the junction depth by the third method of the prior art.
【００２５】[0025]
【発明の効果】以上説明したように、本発明によれば、
従来の技術と比べてしきい値電圧を低下させて電力の消
費を減少させることができる。また、耐圧を向上させる
ことによって、パンチスルーによるリーク電流を減少さ
せることができる。As described above, according to the present invention,
The threshold voltage can be lowered to reduce power consumption as compared with the conventional technology. Further, by improving the breakdown voltage, it is possible to reduce the leak current due to punch through.
【図１】本発明の一実施例によりＮ型シリコン層に１段
階注入工程で４９ＢＦ2 ソースを注入することにより、
単結晶シリコン結晶構造に格子変位が発生した状態を示
す図である。FIG. 1 illustrates implanting a 49BF 2 source into an N-type silicon layer in a one-step implant process according to an embodiment of the present invention.
It is a figure which shows the state which the lattice displacement generate | occur | produced in the single crystal silicon crystal structure.
【図２】本発明の一実施例によりシリコン層に１段階注
入工程後、２段階注入工程で１１Ｂソースをシリコン層
に注入した状態を示す図である。FIG. 2 is a view showing a state where an 11B source is injected into a silicon layer by a two-step injection process after a one-step injection process into a silicon layer according to an embodiment of the present invention.
１ 単結晶シリコン結晶構造 ２ 疑似アモルファス領域 ３ 不純物が注入された領域 なお、各図中、同一符号は同一または相当部分を示す。 1 Single Crystal Silicon Crystal Structure 2 Pseudo Amorphous Region 3 Region Injected with Impurities In the drawings, the same reference numerals indicate the same or corresponding portions.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 高 在浣 大韓民国京畿道城南市壽井区太平４洞 3309−623番地 (72)発明者 玄 一善 大韓民国ソウル特別市江東区上一洞 住 公アパートメント301−405 (56)参考文献 特開 昭56−73470（ＪＰ，Ａ) 特開 平４−246823（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kozasui, 3309-623, Taeping 4-dong, Saui-gu, Seongnam-si, Gyeonggi-do, Republic of Korea (72) Inventor Gen Ichizen, Kami-dong, Koto-gu, Seoul, Republic of Korea 301 Apartment -405 (56) Reference JP-A-56-73470 (JP, A) JP-A-4-246823 (JP, A)
Claims (1)
形成する方法において、 Ｎ型シリコン層に１段階で４９ＢＦ2 ソースを４５Ｋｅ
Ｖのエネルギと２．０×１０11ｃｍ-2の不純物注入量で
注入する工程と、 ２段階で１１Ｂソースを３５ＫｅＶのエネルギと１．１
５×１０12ｃｍ-2の不純物注入量で注入する工程とを備
え、 前記１段階の４９ＢＦ2 ソースのシリコン層への注入に
より、シリコン層の表面でＢＦ2 ソースが衝突してＢと
Ｆ2 イオンに分離されてシリコン層内に注入されなが
ら、シリコン層の単結晶シリコン格子構造に格子変位が
発生して疑似アモルファス領域に変化することを特徴と
する、二重注入による半導体素子の浅い接合の形成方
法。1. A method for forming a junction region of a semiconductor device by an implantation process, wherein a 49BF 2 source of 45 Ke is formed in one step on an N-type silicon layer.
V energy and a step of implanting with an impurity implantation amount of 2.0 × 10 11 cm -2 , and 11B source with 35 KeV energy and 1.1 in two steps.
And a step of implanting the impurity of 5 × 10 12 cm −2. The one-step implantation of the 49BF 2 source into the silicon layer causes the BF 2 source to collide with B and F 2 at the surface of the silicon layer. While being separated into ions and injected into the silicon layer, a lattice displacement occurs in the single crystal silicon lattice structure of the silicon layer and changes into a pseudo-amorphous region. Forming method.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92P10739 | 1992-06-20 | ||
| KR1019920010739A KR960012577B1 (en) | 1992-06-20 | 1992-06-20 | Channel formation method of double implant process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0661170A JPH0661170A (en) | 1994-03-04 |
| JP2534967B2 true JP2534967B2 (en) | 1996-09-18 |
Family
ID=19334985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5147674A Expired - Fee Related JP2534967B2 (en) | 1992-06-20 | 1993-06-18 | Method for forming shallow junction of semiconductor device by double implantation |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2534967B2 (en) |
| KR (1) | KR960012577B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100460757B1 (en) * | 2003-04-30 | 2004-12-14 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device having ultra shallow super steep retrograge epi-channel formed by double channel doping |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5673470A (en) * | 1979-11-21 | 1981-06-18 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| US5155369A (en) * | 1990-09-28 | 1992-10-13 | Applied Materials, Inc. | Multiple angle implants for shallow implant |
-
1992
- 1992-06-20 KR KR1019920010739A patent/KR960012577B1/en not_active IP Right Cessation
-
1993
- 1993-06-18 JP JP5147674A patent/JP2534967B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0661170A (en) | 1994-03-04 |
| KR940001448A (en) | 1994-01-11 |
| KR960012577B1 (en) | 1996-09-23 |
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