CN112309853A - Preparation method of shielded gate trench structure - Google Patents

Preparation method of shielded gate trench structure Download PDF

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Publication number
CN112309853A
CN112309853A CN202011261890.3A CN202011261890A CN112309853A CN 112309853 A CN112309853 A CN 112309853A CN 202011261890 A CN202011261890 A CN 202011261890A CN 112309853 A CN112309853 A CN 112309853A
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oxide layer
substrate
groove
trench
shielded gate
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梁肖
张凌越
姜波
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention provides a preparation method of a shielded grid groove structure, which comprises the following steps: a substrate is provided, a groove is formed in the substrate, and an oxide layer is formed on the surfaces of the substrate and the groove. And carrying out ion implantation on the oxide layer. And removing part of the thickness of the oxide layer on the side wall of the groove. Therefore, the chemical property of the oxide layer is changed by performing ion implantation on the oxide layer, so that the etching rate of the oxide layer can be improved when the oxide layer with partial thickness on the side wall of the trench is removed. Therefore, under the condition of not changing the original process, the etching rate of the oxide layer is increased, and the problem of lateral etching in the original process can be solved.

Description

Preparation method of shielded gate trench structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a shielded gate trench structure.
Background
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), referred to as a MOSFET for short, is a Field-Effect Transistor that can be widely used in analog circuits and digital circuits. The mosfet may be classified into an N-channel type in which electrons are dominant and a P-channel type in which holes are dominant according to the polarity of its "channel", and is generally called an N-type mosfet (NMOSFET) and a P-type mosfet (PMOSFET). At present, the metal oxide semiconductor field effect transistor based on semiconductor material has very wide application in digital signal processing such as a microprocessor, a microcontroller and the like and integrated circuits for analog signal processing.
Because of the charge coupling effect of the Split-Gate-Trench (SGT) structure, horizontal depletion is introduced on the basis of vertical depletion (P-Body/N-Epi junction) of a mosfet with a conventional Trench, so that the electric field of the device is changed from triangular distribution to approximately rectangular distribution. The device can obtain higher breakdown voltage and can shield the trench gate and the drain under the condition of adopting the epitaxial specification with the same doping concentration. At present, the structure is widely applied to the field of medium and low voltage power devices.
However, in the process of preparing the shielded gate trench structure, especially when the trench oxide layer is etched, the substrate connected with the oxide layer is etched due to the influence of the lateral etching of the liquid medicine, i.e., the lateral etching problem occurs, so that the subsequent process is influenced, and the device performance is seriously influenced. Currently, the commonly used method for avoiding the lateral etching is to change the chemical property of the etching solution or to add a mask layer for preventing the lateral etching. However, in the actual process operation, these methods increase the process complexity and reduce the work efficiency.
Therefore, a new method for manufacturing a trench structure of a shielded gate is needed to solve the lateral etching problem, improve the working efficiency and ensure the device performance.
Disclosure of Invention
The invention aims to provide a preparation method of a shielded gate trench structure, which aims to solve the lateral etching problem in an etching process.
In order to solve the above technical problem, the present invention provides a method for manufacturing a trench structure of a shielded gate, including:
providing a substrate, wherein a groove is formed in the substrate, and an oxide layer is formed on the surfaces of the substrate and the groove;
performing ion implantation on the oxide layer;
and removing part of the thickness of the oxide layer on the side wall of the groove.
Optionally, in the preparation method of the shielded gate trench structure, ions used in ion implantation of the oxide layer include germanium ions and argon ions.
Optionally, in the preparation method of the shielded gate trench structure, the ion concentration in the ion implantation of the oxide layer is greater than 1 × 1015ions/cm3。
Optionally, in the preparation method of the shielded gate trench structure, the depth of the oxide layer subjected to ion implantation is equal to the thickness of the oxide layer removed on the sidewall of the trench.
Optionally, in the preparation method of the shielded gate trench structure, a wet etching process is used to remove a part of the oxide layer located on the sidewall of the trench, where the etching solution includes hydrofluoric acid.
Optionally, in the method for manufacturing the shielded gate trench structure, before removing a part of the oxide layer located on the sidewall of the trench, the method for manufacturing the shielded gate trench structure further includes: and removing the oxide layer on the surface of the substrate.
Optionally, in the preparation method of the shielded gate trench structure, a wet etching process is used to remove the oxide layer on the surface of the substrate, where the etching solution includes hydrofluoric acid.
Optionally, in the preparation method of the shielded gate trench structure, the oxide layer is formed on the surfaces of the substrate and the trench by using a thermal oxidation process.
Optionally, in the preparation method of the shielded gate trench structure, before the ion implantation is performed on the oxide layer, the preparation method of the shielded gate trench structure further includes: and forming a dielectric layer in the groove, wherein the dielectric layer fills the groove.
Optionally, in the preparation method of the shielded gate trench structure, the material of the dielectric layer includes polysilicon.
In summary, the present invention provides a method for manufacturing a trench structure of a shield gate, the method comprising: providing a substrate, wherein a groove is formed in the substrate, and an oxide layer is formed on the surfaces of the substrate and the groove; performing ion implantation on the oxide layer; and removing part of the thickness of the oxide layer on the side wall of the groove. Therefore, the chemical property of the oxide layer is changed by performing ion implantation on the oxide layer, so that the etching rate of the oxide layer can be improved when the oxide layer with partial thickness on the side wall of the trench is removed. Therefore, under the condition of not changing the original process, the etching rate of the oxide layer is increased, and the problem of lateral etching in the original process can be solved.
Drawings
FIG. 1 is a flow chart of an etching method in an embodiment of the present invention;
FIGS. 2-5 and 7 are schematic views of a semiconductor structure at various steps in a method of fabricating a shielded gate trench structure in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a lateral etch position in an embodiment of the invention;
wherein the reference numbers indicate:
100-a substrate; 101-an epitaxial layer; 102-a mask layer; 103-an oxide layer; 104-a dielectric layer; a P-groove; and M-lateral etching.
Detailed Description
Therefore, in the process of preparing the shielded gate trench structure, especially when the trench oxide layer is etched, lateral etching occurs, and the device performance is seriously affected. Currently, the commonly used method for avoiding the lateral etching is to change the chemical property of the etching solution or to add a mask layer for preventing the lateral etching. However, in the actual process operation, these methods increase the process complexity and reduce the work efficiency.
Therefore, a method for manufacturing a trench structure of a shielded gate is needed to solve the lateral etching problem, improve the working efficiency and ensure the device performance.
The method for fabricating the shielded gate trench structure according to the present invention is further described in detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
To solve the above technical problem, the present embodiment provides a method for manufacturing a shielded gate trench structure, referring to fig. 1, the method for manufacturing a shielded gate trench structure includes:
step one S10: providing a substrate, wherein a groove is formed in the substrate, and an oxide layer is formed on the surfaces of the substrate and the groove;
step two S20: performing ion implantation on the oxide layer;
step three S30: and removing part of the thickness of the oxide layer on the side wall of the groove.
The method for manufacturing the shielded gate trench structure provided in this embodiment is specifically described below with reference to fig. 2 to 5:
step one S10: referring to fig. 2-3, a substrate 100 is provided, a trench P is formed in the substrate 100, and an oxide layer 103 is formed on the surface of the substrate 100 and the trench P.
The substrate 100 includes, but is not limited to, a silicon substrate, a silicon germanium substrate, and the like. As shown in fig. 2, before forming the trench P, an epitaxial layer 101 is grown on the upper surface of the substrate 100. When an N-channel MOSFET is fabricated, the epitaxial layer 101 is a heavily doped N-type epitaxial layer 101. When a P-channel MOSFET is prepared, the epitaxial layer 101 is a heavily doped P-type epitaxial layer 101, and the thickness of the epitaxial layer 101 is determined according to the source-drain withstand voltage condition required by the device. A patterned mask layer 102 is further formed on the epitaxial layer 101, and the mask layer 102 may be an ONO film (silicon oxide-silicon nitride-silicon oxide film) or a hard mask made of silicon nitride. The trenches P are formed by the blocking action of the mask layer 102. The trench P penetrates the epitaxial layer 101 and a portion of the substrate 100. The number of the trenches P is not limited to one, and may be two, three, or four, and the like, and the specific number of the trenches P is determined according to the device design. The process for forming the trench P includes, but is not limited to, a dry etching process or a wet etching process.
As shown in fig. 3, after the trench P is formed, the mask layer 102 is removed, and then an oxide layer 103 is formed on the surface of the substrate 100 and the trench P by a thermal oxidation process. Optionally, the material of the oxide layer 103 includes silicon oxide, and the oxide layer 103 is used for protecting the substrate 100 and realizing electrical insulation. Optionally, the mask layer 102 is removed by a wet etching process, and the etching solution is hot phosphoric acid.
Step two S20: referring to fig. 4-5, the oxide layer 103 is ion implanted.
In an embodiment of the present application, before performing ion implantation on the oxide layer 103, referring to fig. 4, the method for preparing the shielded gate trench structure further includes: and forming a dielectric layer 104 in the groove P, wherein the dielectric layer 104 fills the groove P. That is, the surface of the dielectric layer 104 is flush with the oxide layer 103 on the surface of the epitaxial layer 101, or the surface of the dielectric layer 104 is slightly lower than the oxide layer 103 on the surface of the epitaxial layer 101. The material of the dielectric layer 104 includes polysilicon, and the process for forming the dielectric layer 104 includes, but is not limited to, a Low Pressure Chemical Vapor Deposition (LPCVD) process.
Please refer toIn fig. 5, the oxide layer 103 on which the ion implantation process is performed includes the oxide layer 103 on the surface of the epitaxial layer 101 and the oxide layer 103 on the sidewall of the trench P. The ions used include, but are not limited to, germanium ions and argon ions. The large-mass elements commonly used in the ion implantation process may be the ions implanted in step two S20. For optimum effect, the ion concentration during ion implantation is greater than 1 × 1015ions/cm3And the depth of the ion implantation performed on the oxide layer 103 is equal to the thickness of the oxide layer 103 removed on the sidewall of the trench P in the subsequent process.
In the existing manufacturing process of the shielded gate trench structure, in the step of etching the oxide layer 103, a wet etching process is usually adopted to ensure the etching effect. However, during the wet etching process, the used etching liquid flows to etch other structures in the device, which causes a serious lateral etching problem M (as shown in fig. 6). In order to avoid the influence of the lateral etching on the device, it is common to change the composition of the etching solution or to grow a barrier layer to protect other structures. However, these methods not only increase the cost but also decrease the production efficiency. Therefore, in the preparation method of the shielded gate trench structure provided by this embodiment, the chemical property of the oxide layer 103 is changed by injecting the large-mass ions into the oxide layer 103, so that the etching rate of the oxide layer 103 is increased on the premise of not changing the etching liquid, the problem of lateral etching can be alleviated, the time cost can be saved, and the preparation efficiency can be improved.
Step three S30: referring to fig. 7, a portion of the thickness of the oxide layer 103 on the sidewall of the trench P is removed.
And removing part of the oxide layer 103 on the side wall of the trench P by using a wet etching process, wherein the etching solution comprises hydrofluoric acid. In the preparation method of the shielded gate trench structure provided by this embodiment, after the ion implantation is performed on the oxide layer 103 in the second step S20 without changing the etching solution in the original process, the etching rate of the oxide layer 103 in the hydrofluoric acid solution is greatly increased, so that the process time of wet etching is shortened, and the problem of lateral etching is alleviated due to the shortened process time. Therefore, the preparation method of the shielded gate trench structure provided by the embodiment can reduce the degree of lateral etching, improve the performance of the device, shorten the process time and improve the preparation efficiency.
Further, before removing a portion of the oxide layer 103 on the sidewall of the trench P, the method for manufacturing the shielded gate trench structure further includes: and removing the oxide layer 103 on the surface of the substrate 100 by using a wet etching process, wherein the etching solution comprises hydrofluoric acid.
And further forming a grid structure, a source electrode, a drain electrode and the like in subsequent processes, and finally finishing the manufacture of the metal oxide semiconductor field effect transistor. Since the subsequent process is well known to those skilled in the art, it is not described herein.
In summary, the present embodiment provides a method for manufacturing a shielded gate trench structure, where the method for manufacturing the shielded gate trench structure includes: a substrate 100 is provided, a trench P is formed in the substrate 100, and an oxide layer 103 is formed on the surface of the substrate 100 and the trench P. And performing ion implantation on the oxide layer 103. Removing a part of the thickness of the oxide layer 103 on the sidewall of the trench P. Therefore, in the preparation method provided by this embodiment, the oxide layer 103 is subjected to ion implantation, so as to change the chemical property of the oxide layer 103, and further, when the oxide layer 103 with a partial thickness on the sidewall of the trench P is removed, the etching rate of the oxide layer 103 can be increased. Therefore, under the condition that the original process is not changed, the etching rate of the oxide layer 103 is increased, and the problem of lateral etching in the original process is solved, so that the preparation method provided by the embodiment not only saves the preparation time and cost and improves the efficiency, but also can achieve a better process effect and improve the device performance.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A preparation method of a shielded gate trench structure is characterized by comprising the following steps:
providing a substrate, wherein a groove is formed in the substrate, and an oxide layer is formed on the surfaces of the substrate and the groove;
performing ion implantation on the oxide layer;
and removing part of the thickness of the oxide layer on the side wall of the groove.
2. The method of claim 1, wherein ions used in the ion implantation of the oxide layer comprise germanium ions and argon ions.
3. The method of claim 1, wherein the oxide layer is ion implanted with an ion concentration greater than 1 x 1015ions/cm3。
4. The method of claim 1, wherein the oxide layer is ion implanted to a depth equal to a thickness of the oxide layer removed on the trench sidewalls.
5. The method of claim 1, wherein the oxide layer is partially removed on the sidewalls of the trench by a wet etching process, wherein the etching solution comprises hydrofluoric acid.
6. The method of claim 1, wherein prior to removing a portion of the oxide layer on the trench sidewalls, the method further comprises: and removing the oxide layer on the surface of the substrate.
7. The method of claim 6, wherein the oxide layer on the surface of the substrate is removed by a wet etching process, wherein the etching solution comprises hydrofluoric acid.
8. The method of claim 1, wherein a thermal oxidation process is used to form the oxide layer on the surface of the substrate and the trench.
9. The method of claim 1, wherein prior to ion implanting the oxide layer, the method further comprises: and forming a dielectric layer in the groove, wherein the dielectric layer fills the groove.
10. The method of claim 9, wherein the dielectric layer comprises polysilicon.
CN202011261890.3A 2020-11-12 2020-11-12 Preparation method of shielded gate trench structure Pending CN112309853A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635394A (en) * 2021-03-09 2021-04-09 晶芯成(北京)科技有限公司 Preparation method of trench isolation structure

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CN102129999A (en) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 Method for producing groove type dual-layer grid MOS (Metal Oxide Semiconductor) structure
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CN102983080A (en) * 2012-12-26 2013-03-20 上海宏力半导体制造有限公司 Method for improving erasure and programming performances of split gate memory
CN107710418A (en) * 2015-05-07 2018-02-16 德克萨斯仪器股份有限公司 Multi-shielding trench gate field effect transistor
CN108257869A (en) * 2016-12-28 2018-07-06 中航（重庆）微电子有限公司 The preparation method of shield grid groove MOSFET
CN110047759A (en) * 2019-04-28 2019-07-23 矽力杰半导体技术(杭州)有限公司 Trench MOSFET device manufacturing method

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JP2006165427A (en) * 2004-12-10 2006-06-22 Toko Inc Method of manufacturing semiconductor apparatus
US20060166419A1 (en) * 2005-01-21 2006-07-27 Kazuo Shimoyama Method for manufacturing semiconductor device
CN101383354A (en) * 2007-09-07 2009-03-11 东部高科股份有限公司 Flash memory and manufacturing method of the same
JP2009087603A (en) * 2007-09-28 2009-04-23 Toshiba Corp Ion implanting device, ion implanting method, and manufacturing method of semiconductor device
CN102129999A (en) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 Method for producing groove type dual-layer grid MOS (Metal Oxide Semiconductor) structure
CN102130006A (en) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 Method for preparing groove-type double-layer gate power metal oxide semiconductor (MOS) transistor
CN102983080A (en) * 2012-12-26 2013-03-20 上海宏力半导体制造有限公司 Method for improving erasure and programming performances of split gate memory
CN107710418A (en) * 2015-05-07 2018-02-16 德克萨斯仪器股份有限公司 Multi-shielding trench gate field effect transistor
CN108257869A (en) * 2016-12-28 2018-07-06 中航（重庆）微电子有限公司 The preparation method of shield grid groove MOSFET
CN110047759A (en) * 2019-04-28 2019-07-23 矽力杰半导体技术(杭州)有限公司 Trench MOSFET device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635394A (en) * 2021-03-09 2021-04-09 晶芯成(北京)科技有限公司 Preparation method of trench isolation structure

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