JP2527828B2 - 半導体パッケ―ジ - Google Patents

半導体パッケ―ジ

Info

Publication number
JP2527828B2
JP2527828B2 JP2044424A JP4442490A JP2527828B2 JP 2527828 B2 JP2527828 B2 JP 2527828B2 JP 2044424 A JP2044424 A JP 2044424A JP 4442490 A JP4442490 A JP 4442490A JP 2527828 B2 JP2527828 B2 JP 2527828B2
Authority
JP
Japan
Prior art keywords
solder flow
solder
ceramic member
wire bond
prevention wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2044424A
Other languages
English (en)
Other versions
JPH03248541A (ja
Inventor
敏一 尾形
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2044424A priority Critical patent/JP2527828B2/ja
Priority to US07/558,467 priority patent/US5055911A/en
Priority to GB9018550A priority patent/GB2241379B/en
Publication of JPH03248541A publication Critical patent/JPH03248541A/ja
Application granted granted Critical
Publication of JP2527828B2 publication Critical patent/JP2527828B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/151—Die mounting substrate
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  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体パッケージに係り、特に半導体組
み立て工程におけるダイボンド時の半田流れを防止する
ことのできるパッケージに関する。
〔従来の技術〕
第５図は従来の半導体装置を示す斜視図である。放熱
フィン（８）上にベースセラミック部材（１）が配置さ
れ、ベースセラミック部材（１）の上に開口部（5a）を
有するフレームセラミック部材（５）が配置されてい
る。フレームセラミック部材（５）の上にはメタライズ
層（12a）及び（12b）が形成され、これらメタライズ層
（12a）及び（12b）上にそれぞれリード（6a）及び（6
b）が設けられている。また、フレームセラミック部材
（５）の開口部（5a）内においてベースセラミック部材
（１）上にメタライズ層（２）及び（14）が形成されて
おり、半導体チップ（９）がメタライズ層（２）上に半
田（10）により搭載されている。尚、図中（11）は金属
細線を示している。
半導体チップ（９）の搭載部分を第６図に示す。ベー
スセラミック部材（１）上に位置するメタライズ層
（２）の上にNiメッキ層（３）を介してAuメッキ層
（４）が形成され、半導体チップ（９）がAuメッキ層
（４）上に半田（10）によって固着されている。
このような半導体装置は、次のようにして製造されて
いた。まず、ベリリア等のセラミックをメタライジング
して任意のパターンのメタライズ層（２）及び（14）を
形成した後、これを焼成することによりベースセラミッ
ク部材（１）を形成する。このとき、メタライズ層（1
4）はベースセラミック部材（１）の裏面にまで及ぶよ
うに形成される。次に、メタライズ層（２）及び（14）
の上に下地処理としてNiメッキ層（３）を形成した後、
Niメッキ層（３）上にフレームセラミック部材（５）及
び放熱フィン（８）をろう付けする。さらに、ダイパッ
ドエリア（13）及びワイヤボンドエリアに位置するNiメ
ッキ層（３）上にAuメッキ層（４）あるいはAgメッキ層
を形成することにより、パッケージが製造される。
このパッケージのダイパッドエリア（13）に半田（1
0）によって半導体チップ（９）を固着し、金属細線（1
1）を必要箇所にボンディングする。その後、パッケー
ジを封止して半導体装置の組み立てを完了する。
〔発明が解決しようとする課題〕
しかしながら、半導体チップ（９）を搭載するため
に、第６図に示すように、ダイパッドエリア（13）上に
は通常半田流れと呼ばれる半田（10）の広がりが生じて
しまう。このため、半導体チップ（９）の下面電極取り
出し用の金属細線（11）は半田流れの上にボンディング
せざるを得なかった。このような半田流れの上にボンデ
ィングされた金属細線（11）の付着力は極めて弱いこと
が知られており、使用中の熱ストレス等により金属細線
（11）が半田流れから剥離して接続不良になる恐れがあ
った。また、ボンディングが不可能となる場合もあっ
た。
このように、従来の半導体パッケージは、半田流れに
起因して信頼性が低下するという問題点があった。
この発明はこのような問題点を解消するためになされ
たもので、半田流れに起因する信頼性の低下を防止する
ことのできる半導体パッケージを提供することを目的と
する。
〔課題を解決するための手段〕
この発明に係る半導体パッケージは、セラミック基板
と、セラミック基板上に形成され且つダイパッドエリア
及びワイヤボンドエリアを有するメタライズ層と、メタ
ライズ層上で且つダイパッドエリアとワイヤボンドエリ
アとの間に形成されると共にダイパッドエリア上に半導
体チップを搭載する際の半田流れがワイヤボンドエリア
に流出することを防止するための半田流れ防止壁とを備
え、半田流れ防止壁はガラスから形成される、あるいは
接着剤により固められたセラミック粉末から形成された
ものである。
〔作用〕
この発明に係る半導体パッケージにおいては、メタラ
イズ層上に形成された半田流れ防止壁が、ダイパッドエ
リアへの半導体チップ搭載時に半田流れがワイヤボンド
エリアに流出することを防止する。
〔実施例〕
以下、この発明の実施例を添付図面に基づいて説明す
る。
第１図はこの発明の一実施例に係る半導体パッケージ
を用いて製造した半導体装置を示す斜視図である。Cu等
からなる放熱フィン（８）上に基板となるベースセラミ
ック部材（１）が配置され、ベースセラミック部材
（１）の上に開口部（5a）を有するフレームセラミック
部材（５）が配置されている。フレームセラミック部材
（５）の上にはメタライズ層（12a）及び（12b）が形成
され、これらメタライズ層（12a）及び（12b）上にそれ
ぞれ入出力用のリード（6a）及び（6b）が設けられてい
る。また、フレームセラミック部材（５）の開口部（5
a）を臨むベースセラミック部材（１）上にはメタライ
ズ層（２）及び（14）が形成され、メタライズ層（２）
上に半田流れ防止壁（７）が形成されている。この半田
流れ防止壁（７）を挟んでメタライズ層（２）はダイパ
ッドエリア（15）とワイヤボンドエリア（16）とに区画
され、ダイパッドエリア（15）上に半導体チップ（９）
が半田（10）により搭載されている。さらに、半導体チ
ップ（９）上の電極とメタライズ層（12b）及び（14）
との間、メタライズ層（２）のワイヤボンドエリア（1
6）とメタライズ層（12a）との間がそれぞれ金属細線
（11）により接続されている。
第２図に示されるように、メタライズ層（14）はベー
スセラミック部材（１）の裏面にまで及んでおり、ベー
スセラミック部材（１）を包むように形成されている。
また、各メタライズ層（２）、（12a）、（12b）及び
（14）上にはそれぞれ下地処理としてNiメッキ層（３）
が形成されている。フレームセラミック部材（５）の開
口部（5a）を臨むメタライズ層（２）、（14）及びフレ
ームセラミック部材（５）に形成されたメタライズ層
（12a）、（12b）においては、Niメッキ層（３）の上に
さらにAuメッキ層（４）が形成されている。
メタライズ層（２）上の半田流れ防止壁（７）はガラ
スから形成されており、Auメッキ層（４）の上に突出し
ている。この半田流れ防止壁（７）により区画されたダ
イパッドエリア（15）のAuメッキ層（４）上に半導体チ
ップ（９）が半田（10）によって固着されている。この
半田（10）は、ダイパッドエリア（15）のみに位置し、
ワイヤボンドエリア（16）には及んでいない。すなわ
ち、ワイヤボンドエリア（16）では、金属細線（11）が
Auメッキ層（４）上に直接ボンディングされている。
このような半導体装置は、次のようにして製造され
る。まず、ベリリア等のセラミックをメタライジングし
て任意のパターンのメタライズ層（２）及び（14）を形
成した後、これを焼成することによりベースセラミック
部材（１）を形成する。次に、メタライズ層（２）の上
にSiO2、Al2O3等を成分とするガラスを直線状に塗布
し、これを焼き付けることにより半田流れ防止壁（７）
を形成する。また、ベースセラミック部材（１）と同様
にして、メタライズ層（12a）及び（12b）を有するフレ
ームセラミック部材（５）を形成する。
次に、各メタライズ層（２）、（12a）、（12b）及び
（14）の上に下地処理としてNiメッキ層（３）を形成し
た後、ベースセラミック部材（１）のNiメッキ層（３）
上にフレームセラミック部材（５）及び放熱フィン
（８）をろう付けする一方、フレームセラミック部材
（５）のNiメッキ層（３）上にはリード（6a）及び（6
b）をろう付けする。
その後、フレームセラミック部材（５）の開口部（5
a）内に位置するメタライズ層（２）、（14）及びフレ
ームセラミック部材（５）上のメタライズ層（12a）、
（12b）において、Niメッキ層（３）の上にそれぞれAu
メッキ層（４）あるいはAgメッキ層を形成することによ
り、半導体パッケージが製造される。
この半導体パッケージのダイパッドエリア（15）上に
半導体チップ（９）が半田（10）によって搭載される
が、このとき半田流れ防止壁（７）が存在するために半
田（10）はワイヤボンドエリア（16）に流出することが
防止される。その後、半導体チップ（９）上の電極とメ
タライズ層（12b）及び（14）との間、メタライズ層
（２）のワイヤボンドエリア（16）とメタライズ層（12
a）との間がそれぞれ金属細線（11）により接続され
る。さらに、パッケージを封止して半導体装置の組み立
てを完了する。
以上のように、この実施例に係る半導体パッケージで
は、半田流れ防止壁（７）によりメタライズ層（２）上
のAuメッキ層（４）の表面がダイパッドエリア（15）と
ワイヤボンドエリア（16）とに分離・区画されているの
で、ワイヤボンドエリア（16）への半田流れの流出が防
止され、ワイヤボンドエリア（16）のAuメッキ層（４）
上に金属細線（11）を直接ボンディングすることが可能
となる。従って、ボンディングの信頼性は高いものとな
る。
半田流れ防止壁（７）は、ガラス質を焼成して形成さ
れるので、自由な形に形成しやすく、加熱しても変質し
ないという効果がある。また、半田流れ防止壁（７）
は、ガラス質の焼成による他、セラミックあるいはガラ
スの粉末を接着剤により固めることによっても形成する
ことができる。
さらに、半田流れ防止壁（７）は、ダイボンド時及び
ワイヤボンド時の位置合わせの指標としても活用するこ
とができ、半導体装置製造の自動化を図る上で有益なも
のとなる。
また上記実施例では、半田流れ防止壁（７）をメタラ
イズ層（２）の上に直接形成いたが、第３図に示すよう
に半田流れ防止壁（17）をNiメッキ層（３）上に形成し
てもよく、また第４図のように半田流れ防止壁（18）を
Auメッキ層（４）の上に形成してもよい。
〔発明の効果〕
以上説明したように、この発明に係る半導体パッケー
ジは、セラミック基板と、セラミック基板上に形成され
且つダイパッドエリア及びワイヤボンドエリアを有する
メタライズ層と、メタライズ層上で且つダイパッドエリ
アとワイヤボンドエリアとの間に形成されると共にダイ
パッドエリア上に半導体チップを搭載する際の半田流れ
がワイヤボンドエリアに流出することを防止するための
半田流れ防止壁とを備え、半田流れ防止壁はガラスから
形成される、あるいは接着剤により固められたセラミッ
ク粉末から形成されているので、半田流れに起因する信
頼性の低下を防止することができる。
【図面の簡単な説明】
第１図はこの発明の一実施例に係る半導体パッケージを
用いて製造した半導体装置を示す斜視図、第２図は第１
図のII−II線断面図、第３図及び第４図はそれぞれ他の
実施例を示す部分断面図、第５図は従来の半導体パッケ
ージを用いた半導体装置を示す斜視図、第６図は第５図
の装置の半導体チップ搭載部分を示す断面図である。 図において、（１）はベースセラミック部材、（２）は
メタライズ層、（７）、（17）及び（18）は半田流れ防
止壁、（９）は半導体チップ、（10）は半田、（15）は
ダイパッドエリア、（16）はワイヤボンドエリアであ
る。 なお、各図中同一符号は同一または相当部分を示す。

Claims (1)

    (57)【特許請求の範囲】
  1. 【請求項１】セラミック基板と、 前記セラミック基板上に形成され且つダイパッドエリア
    及びワイヤボンドエリアを有するメタライズ層と、 前記メタライズ層上で且つ前記ダイパッドエリアと前記
    ワイヤボンドエリアとの間に形成されると共に前記ダイ
    パッドエリア上に半導体チップを搭載する際の半田流れ
    が前記ワイヤボンドエリアに流出することを防止するた
    めの半田流れ防止壁と を備え、前記半田流れ防止壁はガラスから形成される、
    あるいは接着剤により固められたセラミック粉末から形
    成されることを特徴とする半導体パッケージ。
JP2044424A 1990-02-27 1990-02-27 半導体パッケ―ジ Expired - Lifetime JP2527828B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2044424A JP2527828B2 (ja) 1990-02-27 1990-02-27 半導体パッケ―ジ
US07/558,467 US5055911A (en) 1990-02-27 1990-07-27 Semiconductor device package utilizing a solder flow prevention wall
GB9018550A GB2241379B (en) 1990-02-27 1990-08-23 A semiconducter package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2044424A JP2527828B2 (ja) 1990-02-27 1990-02-27 半導体パッケ―ジ

Publications (2)

Publication Number Publication Date
JPH03248541A JPH03248541A (ja) 1991-11-06
JP2527828B2 true JP2527828B2 (ja) 1996-08-28

Family

ID=12691108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2044424A Expired - Lifetime JP2527828B2 (ja) 1990-02-27 1990-02-27 半導体パッケ―ジ

Country Status (3)

Country Link
US (1) US5055911A (ja)
JP (1) JP2527828B2 (ja)
GB (1) GB2241379B (ja)

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US5854511A (en) * 1995-11-17 1998-12-29 Anam Semiconductor, Inc. Semiconductor package including heat sink with layered conductive plate and non-conductive tape bonding to leads
US6060779A (en) * 1997-04-30 2000-05-09 Shinko Electric Industries, Co., Ltd. Resin sealed ceramic package and semiconductor device
EP0964446A3 (en) * 1998-06-04 2001-02-07 Ford Motor Company An electronic circuit assembly
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GB9018550D0 (en) 1990-10-10
JPH03248541A (ja) 1991-11-06
US5055911A (en) 1991-10-08
GB2241379A (en) 1991-08-28

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