JP2526252B2 - Reliability test method for semiconductor devices - Google Patents
Reliability test method for semiconductor devicesInfo
- Publication number
- JP2526252B2 JP2526252B2 JP62190808A JP19080887A JP2526252B2 JP 2526252 B2 JP2526252 B2 JP 2526252B2 JP 62190808 A JP62190808 A JP 62190808A JP 19080887 A JP19080887 A JP 19080887A JP 2526252 B2 JP2526252 B2 JP 2526252B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- reliability test
- semiconductor elements
- large number
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、半導体ウエハ上に形成された半導体素子の
信頼性試験を行う半導体素子の信頼性試験方法に関す
る。Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor element reliability test method for performing a reliability test of a semiconductor element formed on a semiconductor wafer.
（従来の技術） 一般に、半導体ウエハ上に形成された半導体素子の試
験測定は、従来プローバとテスタとを用いて行われてい
る。(Prior Art) In general, test measurement of a semiconductor element formed on a semiconductor wafer has been performed using a conventional prober and a tester.
すなわち、プローバによって半導体ウエハ上に形成さ
れた多数の半導体素子に順次探針を接触させ、この探針
を介してテスタから所定の検査信号を供給するととも
に、半導体素子からの信号を測定して順次半導体素子の
試験測定を行う。That is, a probe is sequentially brought into contact with a large number of semiconductor elements formed on a semiconductor wafer by a prober, a predetermined inspection signal is supplied from a tester through the probe, and signals from the semiconductor element are measured and sequentially measured. Test and measure semiconductor devices.
また、従来、半導体素子の信頼性試験を行う装置とし
ては、バーンイン装置等があり、多数のパッケージ済み
の完成品の半導体素子を所定の圧力、温度とされたチャ
ンバ内に収容し、これらの半導体素子に同時に所定のス
トレス信号を例えば数十ないし数百時間印加して、同時
に多数の半導体素子の信頼性試験を行う。Conventionally, as a device for performing a reliability test of a semiconductor element, there is a burn-in device or the like, and a large number of packaged finished semiconductor elements are housed in a chamber at a predetermined pressure and temperature, and A predetermined stress signal is applied to the devices at the same time, for example, for several tens to several hundreds of hours, and the reliability test of many semiconductor devices is performed at the same time.
（発明が解決しようとする問題点） 上記説明のように、従来は、半導体ウエハの状態で多
数の半導体素子の信頼性試験を同時に行うシステムはな
かった。しかしながら、例えば半導体ウエハ上の位置の
違い等によって、形成された半導体素子の信頼性の違い
等が生じる可能性もあり、半導体ウエハの状態で半導体
素子の信頼性試験を行うことは有用である。(Problems to be Solved by the Invention) As described above, conventionally, there is no system that simultaneously performs a reliability test on a large number of semiconductor elements in a semiconductor wafer state. However, there is a possibility that differences in the reliability of the formed semiconductor elements may occur due to, for example, differences in the position on the semiconductor wafer, and it is useful to perform the reliability test of the semiconductor elements in the state of the semiconductor wafer.
本発明は、かかる従来の事情に対処してなされたもの
で、半導体ウエハの状態で多数の半導体素子の信頼性試
験を同時に行うことのできる半導体素子の信頼性試験方
法を提供しようとするものである。The present invention has been made in consideration of such conventional circumstances, and is intended to provide a semiconductor element reliability test method capable of simultaneously performing a reliability test of a large number of semiconductor elements in a state of a semiconductor wafer. is there.
［発明の構成］ （問題点を解決するための手段） すなわち、本発明は、載置台に配置された半導体ウエ
ハに形成された多数の半導体素子と探針とを順次接触さ
せてこれらの半導体素子の試験測定を行うプローバを用
いて、前記半導体ウエハに形成された多数の前記半導体
素子の信頼性試験を行う信頼性試験方法であって、 前記プローバに、前記多数の半導体素子の電極パッド
に対応する多数の探針を備えたプローブカードを設ける
工程と、 前記載置台に前記半導体ウエハを配置する工程と、 前記載置台を移動させて、前記プローブカードの多数
の探針と、前記多数の半導体素子の電極パッドとを当接
させる工程と、 前記多数の探針を介して前記多数の半導体素子に所定
のパルス信号又は所定の交流成分よりなるストレス信号
を印加して、これらの半導体素子の信頼性試験を行う工
程と を具備したことを特徴とする半導体素子の信頼性試験方
法。[Structure of the Invention] (Means for Solving Problems) That is, according to the present invention, a large number of semiconductor elements formed on a semiconductor wafer arranged on a mounting table are sequentially brought into contact with a probe, and the semiconductor elements are formed. Is a reliability test method for performing a reliability test on a large number of the semiconductor elements formed on the semiconductor wafer by using a prober for performing the test measurement, wherein the prober corresponds to the electrode pads of the large number of semiconductor elements. A step of providing a probe card with a large number of probes, a step of arranging the semiconductor wafer on the mounting table, and a step of moving the mounting table to dispose a plurality of probes of the probe card and the semiconductors. A step of contacting the electrode pad of the element, applying a stress signal consisting of a predetermined pulse signal or a predetermined AC component to the plurality of semiconductor elements through the plurality of probes, Reliability test method for a semiconductor device characterized by comprising a step of performing a reliability test of these semiconductor devices.
（作用） 本発明の半導体素子の信頼性試験方法は、半導体ウエ
ハの状態で、同時に多数の半導体素子の信頼性試験を行
うことができる。(Operation) According to the semiconductor element reliability test method of the present invention, a large number of semiconductor element reliability tests can be simultaneously performed in a semiconductor wafer state.
したがって、１回の測定に長時間例えば数十ないし数
百時間を要する信頼性試験を、多数同時に行うことがで
き、例えば半導体ウエハ上の位置の違い等による半導体
素子の信頼性の違い等を短時間で試験することができ
る。Therefore, a large number of reliability tests that require a long time, for example, several tens to several hundreds of hours for one measurement, can be performed at the same time, and the difference in the reliability of semiconductor elements due to the difference in the position on the semiconductor wafer can be reduced. Can be tested in time.
（実施例） 以下本発明の半導体素子の信頼性試験方法を、第１図
を参照して一実施例について説明する。(Example) A semiconductor element reliability test method according to the present invention will be described below with reference to FIG.
プローバ１は、載置台1aを備えており、載置台1a上に
は、半導体ウエハ３が配置される。この載置台1aの上方
には、半導体ウエハ３に形成された多数の半導体素子の
電極パッドに対応する多数の探針4aを備えたプローブカ
ード４が配置されている。The prober 1 includes a mounting table 1a, and the semiconductor wafer 3 is placed on the mounting table 1a. A probe card 4 provided with a large number of probes 4a corresponding to electrode pads of a large number of semiconductor elements formed on the semiconductor wafer 3 is arranged above the mounting table 1a.
なお、上記探針4aは、半導体ウエハ３に形成された例
えば50〜100個の半導体素子の電極パッドに対応して植
設されており、例えばトランジスタの信頼性試験を行う
場合は、１つの半導体素子に対応して、３本の探針4aが
配置されており、この場合、探針4aの総数は、150〜300
本とされている。The probe 4a is implanted corresponding to the electrode pads of, for example, 50 to 100 semiconductor elements formed on the semiconductor wafer 3. For example, when conducting a reliability test of a transistor, one probe is used. Three probes 4a are arranged corresponding to the elements. In this case, the total number of the probes 4a is 150 to 300.
It is supposed to be a book.
また、テスタ２は、上記プローバ１に配置されたプロ
ーブカード４の探針4aと電気的に接続されている。The tester 2 is electrically connected to the probe 4a of the probe card 4 arranged on the prober 1.
上記構成のこの実施例の半導体素子の信頼性試験シス
テムでは、プローバ１により、載置台1a上に配置された
半導体ウエハ３に形成された例えば50〜100個の半導体
素子に、同時に探針4aを接触させる。In the semiconductor element reliability test system of this embodiment having the above-described configuration, the prober 1 simultaneously applies the probe 4a to, for example, 50 to 100 semiconductor elements formed on the semiconductor wafer 3 arranged on the mounting table 1a. Contact.
そして、テスタ２からこれらの探針4aを介して、それ
ぞれの半導体素子に所定のストレス信号例えば所定電圧
のパルス信号、所定の交流成分等を、例えば数十ないし
数百時間印加して、これらの半導体素子の信頼性試験を
行う。Then, a predetermined stress signal, for example, a pulse signal of a predetermined voltage, a predetermined AC component, or the like is applied to each semiconductor element from the tester 2 through these probes 4a, for example, for several tens to several hundreds of hours, and these Conduct a reliability test of semiconductor devices.
すなわち、上記説明のこの実施例の半導体素子の信頼
性試験システムでは、半導体ウエハ３の状態で、同時に
多数の半導体素子の信頼性試験を行うことができる。That is, in the semiconductor element reliability test system of this embodiment described above, a large number of semiconductor element reliability tests can be performed simultaneously in the state of the semiconductor wafer 3.
したがって、例えば半導体ウエハ３上の位置の違い等
による半導体素子の信頼性の違い等を、短時間で試験す
ることができる。Therefore, for example, a difference in reliability of semiconductor elements due to a difference in position on the semiconductor wafer 3 or the like can be tested in a short time.
［発明の効果］ 上述のように、本発明の半導体素子の信頼性試験方法
では、半導体ウエハの状態で多数の半導体素子の信頼性
試験を同時に行うことができる。[Effects of the Invention] As described above, according to the semiconductor element reliability test method of the present invention, it is possible to simultaneously perform reliability tests on a large number of semiconductor elements in a semiconductor wafer state.
第１図は本発明の一実施例の半導体素子の信頼性試験シ
ステムを示す構成図である。 １……プローバ、1a……載置台、２……テスタ、３……
半導体ウエハ、４……プローブカード、4a……探針。FIG. 1 is a configuration diagram showing a semiconductor element reliability test system according to an embodiment of the present invention. 1 ... Prober, 1a ... Mounting table, 2 ... Tester, 3 ...
Semiconductor wafer, 4 ... probe card, 4a ... probe.
Claims (1)
れた多数の半導体素子と探針とを順次接触させてこれら
の半導体素子の試験測定を行うプローバを用いて、前記
半導体ウエハに形成された多数の前記半導体素子の信頼
性試験を行う信頼性試験方法であって、 前記プローバに、前記多数の半導体素子の電極パッドに
対応する多数の探針を備えたプローブカードを設ける工
程と、 前記載置台に前記半導体ウエハを配置する工程と、 前記載置台を移動させて、前記プローブカードの多数の
探針と、前記多数の半導体素子の電極パッドとを当接さ
せる工程と、 前記多数の探針を介して前記多数の半導体素子に所定の
パルス信号又は所定の交流成分よりなるストレス信号を
印加して、これらの半導体素子の信頼性試験を行う工程
と を具備したことを特徴とする半導体素子の信頼性試験方
法。1. A semiconductor wafer formed on a semiconductor wafer arranged on a mounting table using a prober for sequentially contacting a large number of semiconductor elements formed on the semiconductor wafer with a probe to test-measure these semiconductor elements. A reliability test method for performing a reliability test of a large number of the semiconductor elements, wherein the prober is provided with a probe card having a large number of probes corresponding to the electrode pads of the large number of semiconductor elements; Arranging the semiconductor wafer on the mounting table, moving the mounting table to bring the probe tips of the probe card into contact with the electrode pads of the semiconductor elements, and Applying a predetermined pulse signal or a stress signal consisting of a predetermined AC component to the plurality of semiconductor elements via a needle to perform a reliability test of these semiconductor elements. Reliability test method for a semiconductor device characterized and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62190808A JP2526252B2 (en) | 1987-07-30 | 1987-07-30 | Reliability test method for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62190808A JP2526252B2 (en) | 1987-07-30 | 1987-07-30 | Reliability test method for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6435926A JPS6435926A (en) | 1989-02-07 |
| JP2526252B2 true JP2526252B2 (en) | 1996-08-21 |
Family
ID=16264090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62190808A Expired - Lifetime JP2526252B2 (en) | 1987-07-30 | 1987-07-30 | Reliability test method for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2526252B2 (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5322033B2 (en) * | 1974-03-08 | 1978-07-06 | ||
| JPS59134845A (en) * | 1983-01-21 | 1984-08-02 | Hitachi Ltd | Probe card |
| JPS6059745A (en) * | 1983-09-13 | 1985-04-06 | Nec Corp | Probe substrate for measuring semiconductor integrated circuit |
| JPS6113932A (en) * | 1984-06-29 | 1986-01-22 | 松下電器産業株式会社 | Power controller of cleaner |
| JPS6170734A (en) * | 1984-09-13 | 1986-04-11 | Fujitsu Ltd | Probe card |
| JPS62149150A (en) * | 1985-09-24 | 1987-07-03 | Nec Corp | Accelerated-life testing method of semiconductor device |
| JPS62293629A (en) * | 1986-06-12 | 1987-12-21 | Nec Corp | Accelerated life test of semiconductor device |
-
1987
- 1987-07-30 JP JP62190808A patent/JP2526252B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6435926A (en) | 1989-02-07 |
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