JP2022070198A - 隣接するメモリセルの干渉緩和 - Google Patents
隣接するメモリセルの干渉緩和 Download PDFInfo
- Publication number
- JP2022070198A JP2022070198A JP2021097435A JP2021097435A JP2022070198A JP 2022070198 A JP2022070198 A JP 2022070198A JP 2021097435 A JP2021097435 A JP 2021097435A JP 2021097435 A JP2021097435 A JP 2021097435A JP 2022070198 A JP2022070198 A JP 2022070198A
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- Prior art keywords
- memory cell
- memory
- sensing
- data state
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
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Abstract
Description
本出願は、参照によりその全体が本明細書に組み込まれる、2020年10月26日に出願されたBazarskyらによる「ADJACENT MEMORY CELL INTERFERENCE MITIGATION」という名称の米国仮特許出願第63/105,696号の優先権を主張する。
Claims (20)
- 装置であって、
記憶装置と、
前記記憶装置に接続された制御回路と、を備え、前記制御回路は、ブロック内の第1のワード線に接続された第1の不揮発性メモリセルと、前記第1のワード線に隣接する前記ブロック内の第2のワード線に接続された第2の不揮発性メモリセルと、を含む、メモリダイに接続するように構成され、前記制御回路は、
前記第1のメモリセルを感知し、
前記第1のメモリセルを感知することに基づいて、前記第1のメモリセルの各々に関するデータ状態情報を前記記憶装置に記憶し、前記記憶は、前記ブロック内のワード線の読み出しの組において前記第2のメモリセルを感知する前に行われ、
前記記憶されたデータ状態情報に基づいて、前記第2の不揮発性メモリセルの条件を判定する、ように構成される、装置。 - 前記制御回路は、
前記記憶されたデータ状態情報を使用して、前記第2のメモリセルの各々に関するハードビットを判定し、
前記記憶されたデータ状態情報を使用して、前記第2のメモリセルの前記ハードビットに対する復号エラーに応じて、前記第2のメモリセルの各々に関するソフトビットを判定する、ように更に構成される、請求項1に記載の装置。 - 前記記憶装置はデータラッチを備え、前記制御回路は、
前記第1のメモリセルを感知することによる第1の感知情報を前記データラッチに記憶し、
前記第2のメモリセルを感知することによる第2の感知情報を前記データラッチに記憶し、それによって前記第1の感知情報を上書きし、
前記第1のメモリセルに関する前記記憶されたデータ状態情報を使用して、前記第1の感知情報を上書きした後の前記第2の不揮発性メモリセルの前記条件を判定する、ように更に構成される、請求項1に記載の装置。 - 前記制御回路及び前記記憶装置は、前記メモリダイに接合された制御ダイ上に存在し、
前記メモリダイは、前記第1のメモリセル及び前記第2のメモリセルに関連付けられたビット線を含み、
前記制御回路は、前記ビット線を感知することによって前記第1のメモリセル及び前記第2のメモリセルを感知するように更に構成される、請求項3に記載の装置。 - 前記制御回路は、
前記第2のワード線に接続された選択されたメモリセルに印加された基準電圧に基づいて、前記選択されたメモリセルの前記条件を判定し、前記基準電圧は、前記選択されたメモリセルに隣接するメモリセルの前記記憶されたデータ状態情報に対応する、前記選択されたメモリセルに対する干渉の補償を行う、ように構成される、請求項1に記載の装置。 - 前記制御回路及び前記記憶装置は、前記メモリダイに固着された制御ダイ上に存在し、前記制御回路は、
前記第2のワード線に接続された前記第2のメモリセルを感知し、
前記第2のメモリセルを前記メモリダイから感知することによる感知情報を前記記憶装置に転送し、
前記記憶されたデータ状態情報を使用して前記記憶装置内の前記感知情報の等化を実行し、前記等化は、前記第2のメモリセルに対する前記第1のメモリセルの干渉を補償し、
前記等化に基づいて、前記第2のメモリセルのデータ状態を判定する、ように更に構成される、請求項1に記載の装置。 - 前記制御回路は、
前記記憶されたデータ状態情報に基づいて、前記第2のメモリセルの各々に関するハードビットを判定し、
各第2のメモリセルに関する前記ハードビットをメモリコントローラに転送し、
前記メモリコントローラからのソフトビットの要求に応じて、前記ソフトビットを前記メモリコントローラに提供し、これは、
ソフトビット読み出し基準電圧を前記第2のワード線に印加し、
前記ソフトビット読み出し基準電圧の印加に応じて、各第2の不揮発性メモリセルを感知し、前記ソフトビット読み出し基準電圧の各々について、各第2のメモリセルに関するソフトビット感知データが生成され、
それぞれの第2のメモリセルに隣接する第1のメモリセルに関する前記記憶されたデータ状態情報を使用して、各それぞれの第2のメモリセルに使用するためのソフトビット感知データを選択し、
各それぞれの第2のメモリセルの前記選択されたソフトビット感知データに基づいて、前記第2のメモリセルの各々に関する前記ソフトビットを判定する、ことを含む、ように更に構成される、請求項1に記載の装置。 - 前記制御回路は、
前記第2のメモリセルに記憶されたコードワードの復号の失敗前に、前記第1のメモリセルの各々に関する前記データ状態情報を前記記憶装置に記憶し、
前記第2のメモリセルに記憶された前記コードワードの復号の前記失敗に応じて、前記記憶されたデータ状態情報に基づいて、前記第2の不揮発性メモリセルの前記条件を判定する、ように構成される、請求項1に記載の装置。 - 前記制御回路は、前記ブロック内の前記ワード線の前記読み出しにおいて前記第2のワード線を読み出す直前に前記第1のワード線を読み出すように構成される、請求項1に記載の装置。
- 方法であって、
第1のワード線に接続された第1の不揮発性メモリセルを感知することであって、前記第1の不揮発性メモリセル及び前記第1のワード線は、制御ダイに固着されたメモリダイ上に存在し、前記感知することは、前記制御ダイ上の制御回路によって制御される、感知することと、
前記第1のメモリセルを感知することに基づいて、各それぞれの第1のメモリセルに関する第1の感知情報を前記制御ダイ上のデータラッチに記憶することと、
前記第1及び第2のワード線の逐次読み出しにおいて前記第1のワード線に隣接する第2のワード線に接続された第2の不揮発性メモリセルを感知する前に、前記データラッチ内の前記第1の感知情報に基づいて、前記制御ダイ上に、各それぞれの第1のメモリセルに関するデータ状態情報を記憶することであって、各それぞれの第1のメモリセルに関する前記データ状態情報は、前記それぞれの第1のメモリセルが存在する1つ以上のデータ状態の組を指定する、記憶することと、
前記記憶されたデータ状態情報に基づいて、前記第2のメモリセルに対する前記第1のメモリセルの干渉を補償することと、
前記補償の結果として前記第2のメモリセルのデータ状態を判定することと、を含む、方法。 - 前記記憶されたデータ状態情報に基づいて、前記第2のメモリセルに対する前記第1のメモリセルの干渉を補償することは、
前記データラッチに前記第1の感知情報を、前記第2のメモリセルの第2の感知情報で上書きした後で、前記記憶されたデータ状態情報に基づいて、前記第2のメモリセルに対する前記第1のメモリセルの干渉を補償することを含む、請求項10に記載の方法。 - 前記記憶されたデータ状態情報に基づいて、前記第2のメモリセルに対する前記第1のメモリセルの干渉を補償することは、
異なるハードビット読み出し基準電圧を前記第2のワード線に印加して、それぞれの第2のメモリセルがハードビット基準レベルを上回る閾値電圧を有するか、又はハードビット基準レベルを下回る閾値電圧を有するかを試験することであって、前記異なるハードビット読み出し基準電圧の各々が異なる補償量を適用する、試験することと、
前記記憶されたデータ状態情報に基づく前記異なるハードビット読み出し基準電圧のうちの1つの各それぞれの第2のメモリセルを感知することと、
前記第2のメモリセルを感知することに基づいて、各それぞれの第2のメモリセルに関する第2の感知情報を前記制御ダイ上の前記データラッチに記憶することであって、前記第2の感知情報は前記第1の感知情報を上書きし、前記記憶された第2の感知情報は、隣接する第1のメモリセルによって引き起こされる前記それぞれの第2のメモリセルへの前記干渉に対応する補償量を提供する、ハードビット読み出し基準電圧に対応する、記憶することと、を含む、請求項10に記載の方法。 - 前記記憶されたデータ状態情報に基づいて、前記第2のメモリセルに対する前記第1のメモリセルの干渉を補償することは、
異なるソフトビット読み出し基準電圧を前記第2のワード線に印加して、それぞれの第2のメモリセルがソフトビット基準レベルを上回る閾値電圧を有するか、又はソフトビット基準レベルを下回る閾値電圧を有するかを試験することであって、前記異なるソフトビット読み出し基準電圧の各々が異なる補償量を適用する、試験することと、
前記記憶されたデータ状態情報に基づく前記異なるソフトビット読み出し基準電圧のサブセットの各それぞれの第2のメモリセルを感知することと、
前記第2のメモリセルを感知することに基づいて、各それぞれの第2のメモリセルの第3の感知情報を前記制御ダイ上の前記データラッチに記憶することであって、前記第3の感知情報は前記第2の感知情報を上書きし、前記記憶された第3の感知情報は、前記隣接する第1のメモリセルによって引き起こされる前記それぞれの第2のメモリセルへの前記干渉に対応する補償量を提供する、ソフトビット読み出し基準電圧のサブセットに対応する、記憶することと、を含む、請求項12に記載の方法。 - 前記記憶されたデータ状態情報に基づいて、第2のメモリセルに対する前記第1のメモリセルの干渉を補償することは、
前記データラッチ内の前記第1の感知情報を、前記第2のメモリセルの第2の感知情報で上書きすることと、
前記記憶されたデータ状態情報に基づいて、隣接する第1のメモリセルによって引き起こされる前記それぞれの第2のメモリセルに対する前記干渉に対応する各それぞれの第2のメモリセルに対する補償量を提供する前記第2の感知情報に対して、等化を実行することと、を含む、請求項10に記載の方法。 - 不揮発性記憶システムであって、
不揮発性メモリセルと、前記メモリセルに接続された複数のワード線と、前記メモリセルに関連付けられたビット線と、を含む、メモリダイと、
ボンドパッドによって前記メモリダイに接合された制御ダイであって、前記制御ダイは、
前記ボンドパッドによってビット線を感知するための感知手段であって、前記ビット線は、前記複数のワード線のうちの第1のワード線に接続された第1の不揮発性メモリセルと関連付けられる、感知手段と、
前記第1のワード線に隣接する第2のワード線に接続された第2のメモリセルに記憶されたコードワードの復号の失敗前に、前記第1のメモリセルの各々に関するデータ状態情報を記憶するデータ状態記憶手段であって、前記データ状態情報は、前記感知することに基づき、前記それぞれの第1のメモリセルが存在する1つ以上のデータ状態の範囲を指定する、データ状態記憶手段と、
前記記憶されたデータ状態情報に基づいて、データ状態依存補償を前記第2のメモリセルに適用する補償手段と、を備える、不揮発性記憶システム。 - 前記補償手段は、
前記記憶されたデータ状態情報を使用して、前記第2のメモリセルの各々のハードビットを判定し、前記第2のメモリセルに関する前記ハードビットは、前記コードワードを形成し、
前記記憶されたデータ状態情報を使用して、前記コードワードの正常な復号の失敗に応じて、前記第2のメモリセルの各々に関するソフトビットを判定する、ように構成される、請求項15に記載の不揮発性記憶システム。 - 前記データ状態記憶手段は、
前記第1のメモリセルの第1のデータ状態を前記制御ダイ上のデータラッチに記憶し、
前記記憶されたデータ状態情報を使用して、前記第2のメモリセルの各々に関するハードビットを判定するときに、前記データラッチ内の前記第1のメモリセルの前記第1のデータ状態を、前記第2のメモリセルの第2のデータ状態で上書きする、ように構成される、請求項16に記載の不揮発性記憶システム。 - 前記補償手段は、異なるハードビット読み出し基準電圧を前記第2のメモリセルに印加するように構成され、前記異なるハードビット読み出し基準電圧の各々は、異なる量のデータ状態依存補償を適用し、
前記感知手段は、隣接する第1のメモリセルから前記それぞれの第2のメモリセルへの干渉の補償を提供する、少なくとも1つのハードビット読み出し基準電圧について、各それぞれの第2のメモリセルに関する感知情報を提供するように構成され、
前記補償手段は、前記隣接する第1のメモリセルから前記それぞれの第2のメモリセルへの干渉の補償を提供する、前記感知情報を使用して、前記それぞれの第2のメモリセルの条件を判定する、ように構成される、請求項16に記載の不揮発性記憶システム。 - 前記補償手段は、異なるソフトビット基準電圧を前記第2のメモリセルに印加するように更に構成され、
前記感知手段は、隣接する第1のメモリセルから前記それぞれの第2のメモリセルへの干渉の補償を提供する、少なくとも1つの前記ソフトビット基準電圧の組について、各それぞれの第2のメモリセルに関する感知情報を生成するように構成され、
前記補償手段は、前記隣接する第1のメモリセルから前記それぞれの第2のメモリセルへの干渉の補償を提供する、前記ソフトビット基準電圧の前記組に関する前記感知情報を使用して、前記それぞれの第2のメモリセルの条件を判定する、ように構成される、請求項15に記載の不揮発性記憶システム。 - 前記データ状態記憶手段は、前記第1のメモリセルの第1のデータ状態を前記制御ダイ上のデータラッチに記憶し、前記データラッチ内の前記第1のメモリセルの前記第1のデータ状態を、前記第2のメモリセルの第2のデータ状態で上書きするように構成され、
状態依存補償を前記第1のメモリセルに適用する前記補償手段は、前記データラッチ内の前記第1のメモリセルの前記第1のデータ状態を、前記第2のメモリセルの第2のデータ状態で上書きした後、前記それぞれの第2のメモリセルに隣接する第1のメモリセルのデータ状態に対応する各それぞれの第2のメモリセルの状態依存補償の量を提供する前記第2のデータ状態に対して、等化を実行するように構成される、請求項15に記載の不揮発性記憶システム。
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