JP2020510312A - メモリデバイスおよび方法 - Google Patents
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Abstract
Description
Claims (31)
- メモリデバイスであって、
メモリアレイ構造であって、
メモリアレイスタックと、
前記メモリアレイスタックの少なくとも一部を通って垂直に延びる貫通アレイ接点(TAC)と、
1つまたは複数のメモリアレイ接点と
を含む、メモリアレイ構造と、
前記メモリアレイ構造の前面の第1の誘電体層と、
前記第1の誘電体層内の複数の第1の接点と、
前記メモリアレイ構造の裏面の複数の導電性パッドと、
相補型金属酸化膜半導体(CMOS)構造と、
前記CMOS構造の前面の金属層であって、複数の金属パターンを含む、金属層と、
前記金属層上の第2の誘電体層と、
前記第2の誘電体層内の複数の第2の接点と
を含み、
前記第1の誘電体層および前記第2の誘電体層は向かい合わせて接合され、それにより、前記メモリアレイ構造が前記CMOS構造の上側にあり、少なくとも前記複数の導電性パッド、前記TAC、前記複数の第1の接点、前記複数の第2の接点、前記金属層内の前記複数の金属パターン、および前記1つまたは複数のメモリアレイ接点の少なくとも1つによって、1つまたは複数の電気接続が形成される、
メモリデバイス。 - 前記複数の第1の接点の少なくとも1つおよび前記複数の第2の接点の少なくとも1つが、接点信号経路を形成する、
請求項1に記載のメモリデバイス。 - 前記1つまたは複数のメモリアレイ接点が、ワード線接点およびビット線接点の少なくとも一方を含む、
請求項2に記載のメモリデバイス。 - 前記複数の導電性パッド、前記TAC、前記複数の第1の接点、前記複数の第2の接点、前記金属層内の前記複数の金属パターン、および前記ワード線が、電気的に接続されて、第1の前記1つまたは複数の電気接続を形成して複数の接点信号経路を試験する、
請求項3に記載のメモリデバイス。 - 前記複数の導電性パッド、前記TAC、前記複数の第1の接点、前記複数の第2の接点、前記金属層内の前記複数の金属パターン、および前記ビット線接点が、電気的に接続されて、第2の前記1つまたは複数の電気接続を形成して複数の接点信号経路を試験する、
請求項3に記載のメモリデバイス。 - 前記複数の接点信号経路が、直列に接続される、
請求項4または5に記載のメモリデバイス。 - 前記複数の接点信号経路の少なくともいくつかが、並列に接続される、
請求項4または5に記載のメモリデバイス。 - 前記複数の接点信号経路の少なくとも半分が、並列に接続される、
請求項7に記載のメモリデバイス。 - 前記CMOS構造が、前記金属層に電気的に接続された試験回路を含む、
請求項1から8のいずれか一項に記載のメモリデバイス。 - 前記試験回路が、メモリアレイ構造試験回路および接点信号経路試験回路の少なくとも一方を含む、
請求項9に記載のメモリデバイス。 - 前記メモリアレイ構造試験回路が、メモリプレーン試験回路、メモリブロック試験回路、ビット線試験回路、およびワード線試験回路の少なくとも1つを含む、
請求項10に記載のメモリデバイス。 - 前記メモリアレイ構造が、第3の接点をさらに含み、前記複数の導電性パッドの少なくとも1つが、前記第3の接点によって前記TACに電気的に接続される、
請求項1から11のいずれか一項に記載のメモリデバイス。 - メモリデバイスを形成するための方法であって、
メモリアレイスタックおよび1つまたは複数のメモリアレイ接点を含むメモリアレイ構造を形成することと、
前記メモリアレイ構造の前記メモリアレイスタックの少なくとも一部を通って垂直に延びる貫通アレイ接点(TAC)を形成することと、
前記メモリアレイ構造の前面に第1の誘電体層を形成することと、
前記第1の誘電体層内に複数の第1の接点を形成することと、
前記メモリアレイ構造の裏面に複数の導電性パッドを形成することと、
相補型金属酸化膜半導体(CMOS)構造を形成することと、
前記CMOS構造の前面に金属層であって、複数の金属パターンを含む金属層を形成することと、
前記金属層上に第2の誘電体層を形成することと、
前記第2の誘電体層内に複数の第2の接点を形成することと、
前記第1の誘電体層および前記第2の誘電体層を向かい合わせて接合することを含み、、それにより、前記メモリアレイ構造が前記CMOS構造の上側にあり、少なくとも前記複数の導電性パッド、前記TAC、前記複数の第1の接点、前記複数の第2の接点、前記金属層内の前記複数の金属パターン、および前記1つまたは複数のメモリアレイ接点の少なくとも1つによって、1つまたは複数の電気接続が形成される、
方法。 - 前記CMOS構造の前面に金属層を形成する前に、試験回路を形成することをさらに含み、前記金属層が、前記試験回路に電気的に接続される、
請求項13に記載の方法。 - 前記メモリアレイ構造の裏面に複数の導電性パッドを形成する前に、前記メモリアレイ構造の前記裏面から第3の接点を形成することをさらに含み、
前記複数の導電性パッドの少なくとも1つが、前記第3の接点によって前記TACに電気的に接続され、
前記複数の導電性パッドの前記少なくとも1つが、前記第3の接点の上側に形成される、
請求項13または14に記載の方法。 - メモリデバイスを試験するための方法であって、前記メモリデバイスが、
メモリアレイ構造であって、前記メモリアレイ構造の少なくとも一部を通ってそれぞれが垂直に延びる複数の貫通アレイ接点(TAC)と、1つまたは複数のメモリアレイ接点とを含む、メモリアレイ構造と、
前記メモリアレイ構造の前面の第1誘電体層と、
前記第1の誘電体層内の複数の第1の接点と、
前記メモリアレイ構造の裏面の複数の導電性パッドと、
相補型金属酸化物半導体(CMOS)構造と、
前記CMOS構造の前面の金属層であって、複数の金属パターンを含む、金属層と、
前記金属層上の第2の誘電体層と、
前記第2の誘電体層内の複数の第2の接点と
を含み、前記方法が、
前記メモリデバイス内の試験構造を試験するための入力信号を受信することと、
第1のプローブおよび第1の電気接続であって、前記第1の電気接続が、前記複数の導電性パッドの1つと、前記複数のTACの1つと、前記複数の第1の接点の1つと、前記複数の第2の接点の1つと、前記金属層内の前記複数の金属パターンの1つと、前記1つまたは複数のメモリアレイ接点の少なくとも1つとを含む第1の電気接続を介して前記試験構造に前記入力信号を送信することと、
第2のプローブおよび第2の電気接続であって、前記第2の電気接続が、前記複数の導電性パッドの1つと、前記複数のTACの1つと、前記複数の第1の接点の1つと、前記複数の第2の接点の1つと、前記金属層内の前記複数の金属パターンの1つと、前記1つまたは複数のメモリアレイ接点の少なくとも1つとを含む第2の電気接続を介して前記試験構造から出力信号を受信することと、
前記入力信号、前記出力信号、および前記試験構造に基づいて、前記メモリデバイス内の前記試験構造における構造の特性を決定することと
を含む、方法。 - 前記試験構造が、(i)前記複数の第1の接点の少なくとも1つおよび前記複数の第2の接点の少なくとも1つを含む接点信号経路、および(ii)前記メモリアレイ構造の少なくとも一方を含む、
請求項16に記載の方法。 - 三次元(3D)メモリデバイスであって、
メモリアレイ構造であって、
メモリアレイスタックと、
前記メモリアレイスタックの少なくとも一部を通って垂直に延びる第1の貫通アレイ接点(TAC)と、
メモリアレイ接点と
を含む、メモレイアレイ構造と、
試験回路を備える周辺デバイス構造と、
前記メモリアレイ構造の前面および前記周辺デバイス構造の前面に接触する相互接続層であって、相互接続構造を含む、相互接続層と、
前記メモリアレイ構造の裏面にあり、前記メモリアレイ構造に重なる第1の導電性パッドと
を含み、前記第1の導電性パッド、前記第1のTAC、前記相互接続構造、ならびに前記試験回路および前記メモリアレイ接点の少なくとも一方が、電気的に接続される、
三次元(3D)メモリデバイス。 - 前記メモリアレイ構造の前記裏面にあり、前記メモリアレイ構造に重なる第2の導電性パッドと、
前記メモリアレイスタックの少なくとも一部を通って垂直に延びる第2のTACと
をさらに含み、前記第1の導電性パッドおよび前記第2の導電性パッドが、前記第1のTAC、前記第2のTAC、前記相互接続構造、ならびに前記試験回路および前記メモリアレイ接点の前記少なくとも一方によって電気的に接続される、
請求項18に記載のメモリデバイス。 - 前記第1の導電性パッドおよび前記第2の導電性パッドが、前記第1のTAC、前記第2のTAC、前記相互接続構造、および前記メモリアレイ接点によって電気的に接続される、
請求項19に記載のメモリデバイス。 - 前記第1の導電性パッドおよび前記第2の導電性パッドが、前記第1のTAC、前記第2のTAC、前記相互接続構造、および前記試験回路によって電気的に接続される、
請求項19に記載のメモリデバイス。 - 前記第1の導電性パッドおよび前記第2の導電性パッドが、前記第1のTAC、前記第2のTAC、前記相互接続構造、前記メモリアレイ接点、および前記試験回路によって電気的に接続される、
請求項19に記載のメモリデバイス。 - 前記第1の導電性パッドと前記メモリアレイスタックとの間の距離が、垂直方向に少なくとも約3μmである、
請求項18から22のいずれか一項に記載のメモリデバイス。 - 前記相互接続層が、ハイブリッド結合インターフェースを含む、
請求項18から23のいずれか一項に記載のメモリデバイス。 - 前記第1の導電性パッドおよび前記第2の導電性パッドが、名目上同じサイズおよび名目上同じ形状を有する、
請求項18から24のいずれか一項に記載のメモリデバイス。 - 前記メモリアレイ接点が、ワード線接点、ビット線接点、および選択ゲート接点の少なくとも1つを含む、
請求項18から25のいずれか一項に記載のメモリデバイス。 - 三次元(3D)メモリデバイスを試験するための方法であって、
プローブカードの第1のプローブによって前記メモリデバイスの第1の導電性パッドであって、前記第1の導電性パッドの少なくとも一部が、前記メモリデバイスの上面上にある第1の導電性パッドに入力信号を印加することと、
少なくとも前記第1の導電性パッド、前記メモリデバイスの第1の貫通アレイ接点(TAC)、前記メモリデバイスの結合インターフェースを通過する第1の相互接続構造、ならびにメモリアレイ接点および試験回路の少なくとも一方を介して、前記入力信号を前記メモリデバイスの試験構造に送信することと、
少なくとも前記結合インターフェースを通過する第2の相互接続構造、前記メモリデバイスの第2のTAC、ならびに前記メモリアレイ接点および前記試験回路の前記少なくとも一方を介して、前記試験構造から出力信号を受信することと、
前記プローブカードの第2のプローブによって前記メモリデバイスの第2の導電性パッドであって、前記第2の導電性パッドの少なくとも一部が、前記メモリデバイスの前記上面上にある第2の導電性パッドからの前記出力信号を測定することと、
前記入力信号および前記出力信号に基づいて、前記試験構造の特性を決定することと
を含む、方法。 - 前記試験構造の前記特性が、相互接続構造の抵抗を含む、
請求項27に記載の方法。 - 前記試験構造の前記特性が、相互接続構造の静電容量を含む、
請求項27に記載の方法。 - 前記試験構造の前記特性が、前記試験回路に電気的に接続された周辺デバイスの特性を含む、
請求項27に記載の方法。 - 前記試験構造の前記特性が、前記メモリアレイ接点に電気的に接続されたメモリ構造の特性を含む、
請求項27に記載の方法。
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CN111554690A (zh) | 2020-08-18 |
KR20190122794A (ko) | 2019-10-30 |
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CN106920797A (zh) | 2017-07-04 |
CN110088899B (zh) | 2020-06-26 |
US20190057756A1 (en) | 2019-02-21 |
CN106920797B (zh) | 2018-10-12 |
TWI644379B (zh) | 2018-12-11 |
US10998079B2 (en) | 2021-05-04 |
KR102286338B1 (ko) | 2021-08-05 |
JP6918959B2 (ja) | 2021-08-11 |
CN111554690B (zh) | 2021-03-30 |
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US10679721B2 (en) | 2020-06-09 |
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