JP2020035993A - ファン−アウト半導体パッケージ - Google Patents
ファン−アウト半導体パッケージ Download PDFInfo
- Publication number
- JP2020035993A JP2020035993A JP2018236620A JP2018236620A JP2020035993A JP 2020035993 A JP2020035993 A JP 2020035993A JP 2018236620 A JP2018236620 A JP 2018236620A JP 2018236620 A JP2018236620 A JP 2018236620A JP 2020035993 A JP2020035993 A JP 2020035993A
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- Prior art keywords
- layer
- fan
- wiring
- semiconductor package
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910052782 aluminium Inorganic materials 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
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Classifications
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Abstract
Description
図1は電子機器システムの例を概略的に示すブロック図である。
一般に、半導体チップには、数多くの微細電気回路が集積されているが、それ自体が半導体完成品としての役割を果たすことはできず、外部からの物理的又は化学的衝撃により損傷する可能性がある。したがって、半導体チップ自体をそのまま用いるのではなく、半導体チップをパッケージングして、パッケージ状態で電子機器などに用いている。
図3a及び図3bはファン−イン半導体パッケージのパッケージング前後を概略的に示す断面図である。
図7はファン−アウト半導体パッケージの概略的な形態を示す断面図である。
Claims (16)
- 接続パッドが配置された活性面、及び前記活性面の反対側である非活性面を有する半導体チップと、
前記半導体チップの非活性面を覆う封止材と、
前記半導体チップの非活性面上において前記封止材の少なくとも一部を貫通し、且つ前記半導体チップの非活性面と物理的に離隔する熱導電性ビアと、
前記半導体チップの活性面上に配置され、前記接続パッドと電気的に連結される再配線層を含む連結構造体と、を含む、ファン−アウト半導体パッケージ。 - 前記封止材は、前記半導体チップの非活性面と前記熱導電性ビアの間の前記物理的に離隔する領域の少なくとも一部を満たす、請求項1に記載のファン−アウト半導体パッケージ。
- 前記半導体チップの非活性面と前記熱導電性ビアの間の前記物理的に離隔する距離は1μm〜5μmである、請求項1または2に記載のファン−アウト半導体パッケージ。
- 前記熱導電性ビアは、前記半導体チップの非活性面に近くなるほど断面の幅が狭くなるテーパー形状を有する、請求項1から3のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記熱導電性ビアは金属のみからなる層を含む、請求項1から4のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記封止材上に突出して配置され、前記熱導電性ビアと接続された熱導電性パターン層をさらに含む、請求項1から5のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記封止材上に配置され、前記熱導電性パターン層の少なくとも一部をオープンさせる開口部を有するカバー層をさらに含む、請求項6に記載のファン−アウト半導体パッケージ。
- 前記熱導電性ビアと前記熱導電性パターン層は境界なく一体化している、請求項6または7に記載のファン−アウト半導体パッケージ。
- 前記封止材内に一面が露出するように埋め込まれ、前記熱導電性ビアと接続された熱導電性パターン層をさらに含む、請求項1から5のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記封止材上に配置され、前記熱導電性パターン層の少なくとも一部をオープンさせる開口部を有するカバー層をさらに含む、請求項9に記載のファン−アウト半導体パッケージ。
- 前記熱導電性ビアは前記熱導電性パターン層を貫通する、請求項9または10に記載のファン−アウト半導体パッケージ。
- 貫通孔を有するフレームをさらに含み、
前記半導体チップは前記貫通孔内に配置され、
前記封止材は前記フレームの少なくとも一部を覆い、
前記封止材は前記貫通孔の少なくとも一部を満たす、請求項1から11のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記フレームは複数の配線層を含み、
前記複数の配線層は前記接続パッドと電気的に連結され、
前記封止材上に、又は前記封止材内には配線パターン層が配置され、
前記配線パターン層は前記封止材の少なくとも一部を貫通する配線ビアを介して前記複数の配線層のうち最上側の配線層と電気的に連結される、請求項12に記載のファン−アウト半導体パッケージ。 - 前記フレームは、前記連結構造体と接する第1絶縁層と、前記第1絶縁層に埋め込まれ、前記連結構造体と接する第1配線層と、前記第1絶縁層の前記第1配線層が埋め込まれた側の反対側上に配置された第2配線層と、前記第1絶縁層上に配置され、前記第2配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3配線層と、を含み、
前記第1配線層から前記第3配線層は前記接続パッドと電気的に連結される、請求項12に記載のファン−アウト半導体パッケージ。 - 前記フレームは、前記第2絶縁層上に配置され、前記第3配線層を覆う第3絶縁層と、前記第3絶縁層上に配置された第4配線層と、をさらに含み、
前記第1配線層から前記第4配線層は前記接続パッドと電気的に連結される、請求項14に記載のファン−アウト半導体パッケージ。 - 前記フレームは、第1絶縁層と、前記第1絶縁層の一面上に配置された第1配線層と、前記第1絶縁層の他面上に配置された第2配線層と、前記第1絶縁層の一面上に配置され、前記第1配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3配線層と、前記第1絶縁層の他面上に配置され、前記第2配線層を覆う第3絶縁層と、前記第3絶縁層上に配置された第4配線層と、を含み、
前記第1配線層から前記第4配線層は前記接続パッドと電気的に連結される、請求項12に記載のファン−アウト半導体パッケージ。
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