JP2019512715A - Ltps半導体薄膜トランジスタによるgoa回路 - Google Patents
Ltps半導体薄膜トランジスタによるgoa回路 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 199
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000003990 capacitor Substances 0.000 claims description 23
- 235000008694 Humulus lupulus Nutrition 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 14
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Abstract
Description
Claims (7)
- LTPS半導体薄膜トランジスタによるGOA回路であって、
縦続接続される複数のGOAユニットを備え、各段のGOAユニットはいずれも走査制御モジュール、出力モジュール、プルダウンモジュール及び出力調整モジュールを含み、
nを正の整数とすると、1段目及び最終段のGOAユニットを除き、n段目のGOAユニットにおいて、
前記走査制御モジュールは第1薄膜トランジスタ、第3薄膜トランジスタ及び第5薄膜トランジスタを備え、前記第1薄膜トランジスタのゲート電極が第1クロック信号に電気的に接続され、ソース電極が前段である第n−1段のGOAユニットの出力端子G(n−1)に電気的に接続され、ドレイン電極が第3ノードに電気的に接続され、前記第3薄膜トランジスタのゲート電極が第3クロック信号に電気的に接続され、ソース電極が次段である第n+1段のGOAユニットの出力端子G(n+1)に電気的に接続され、ドレイン電極が前記第3ノードに電気的に接続され、前記第5薄膜トランジスタのゲート電極が定電圧ハイレベルに電気的に接続され、ソース電極が前記第3ノードに電気的に接続され、ドレイン電極が第1ノードに電気的に接続され、
前記出力モジュールは第2薄膜トランジスタ及び第1ブートストラップコンデンサを備え、前記第2薄膜トランジスタのゲート電極が前記第1ノードに電気的に接続され、ソース電極が第2クロック信号に電気的に接続され、ドレイン電極が出力端子G(n)に電気的に接続され、前記第1ブートストラップコンデンサの一端が前記第1ノードに電気的に接続され、他端が前記出力端子G(n)に電気的に接続され、
前記プルダウンモジュールは第4薄膜トランジスタ、第6薄膜トランジスタ、第7薄膜トランジスタ、第8薄膜トランジスタ及び第2ブートストラップコンデンサを備え、前記第4薄膜トランジスタのゲート電極が第2ノードに電気的に接続され、ソース電極が定電圧ローレベルに電気的に接続され、ドレイン電極が前記出力端子G(n)に電気的に接続され、前記第6薄膜トランジスタのゲート電極が前記第3ノードに電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記第2ノードに電気的に接続され、前記第7薄膜トランジスタのゲート電極が前記第2ノードに電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記第1ノードに電気的に接続され、前記第8薄膜トランジスタのゲート電極が第4クロック信号に電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記出力端子G(n)に電気的に接続され、前記第2ブートストラップコンデンサの一端が前記第2ノードに電気的に接続され、他端が前記第2クロック信号に電気的に接続され、
前記出力調整モジュールは第9薄膜トランジスタ、第10薄膜トランジスタ、第11薄膜トランジスタ及び第12薄膜トランジスタを備え、前記第9薄膜トランジスタのゲート電極が前記第2クロック信号に電気的に接続され、ソース電極が前記定電圧ハイレベルに電気的に接続され、ドレイン電極が第4ノードに電気的に接続され、前記第10薄膜トランジスタのゲート電極が前記第1ノードに電気的に接続され、ソース電極が前記第4ノードに電気的に接続され、ドレイン電極が前記出力端子G(n)に電気的に接続され、前記第11薄膜トランジスタのゲート電極が前記出力端子G(n−1)に電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記第4ノードに電気的に接続され、前記第12薄膜トランジスタのゲート電極が前記出力端子G(n+1)に電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記第4ノードに電気的に接続され、かつ、
すべての薄膜トランジスタがいずれも低温ポリシリコン半導体薄膜トランジスタであり、前記第1クロック信号、前記第2クロック信号、前記第3クロック信号及び前記第4クロック信号のパルスが順次に出力されて、互いに重ならず、前記第4ノードのレベルは、前記第2クロック信号がハイ、ローレベルの間をホッピングすると共に、同様にハイ、ローレベルをホッピングするLTPS半導体薄膜トランジスタによるGOA回路。 - 順方向に走査する時、前記第1薄膜トランジスタに電気的に接続される前記第1クロック信号及び前記出力端子G(n−1)がハイレベルを同時に提供し、逆方向に走査する時、前記第3薄膜トランジスタに電気的に接続される前記第3クロック信号及び前記出力端子G(n+1)がハイレベルを同時に提供する請求項1に記載のGOA回路。
- LTPS半導体薄膜トランジスタによるGOA回路であって、
縦続接続される複数のGOAユニットを備え、各段のGOAユニットはいずれも走査制御モジュール、出力モジュール、プルダウンモジュール及び出力調整モジュールを含み、
nを正の整数とすると、1段目及び最終段のGOAユニットを除き、n段目のGOAユニットにおいて、
前記走査制御モジュールは第1薄膜トランジスタ、第3薄膜トランジスタ及び第5薄膜トランジスタを備え、前記第1薄膜トランジスタのゲート電極が第1クロック信号に電気的に接続され、ソース電極が前段である第n−1段のGOAユニットの出力端子G(n−1)に電気的に接続され、ドレイン電極が第3ノードに電気的に接続され、前記第3薄膜トランジスタのゲート電極が第3クロック信号に電気的に接続され、ソース電極が次段である第n+1段のGOAユニットの出力端子G(n+1)に電気的に接続され、ドレイン電極が前記第3ノードに電気的に接続され、前記第5薄膜トランジスタのゲート電極が定電圧ハイレベルに電気的に接続され、ソース電極が前記第3ノードに電気的に接続され、ドレイン電極が第1ノードに電気的に接続され、
前記出力モジュールは第2薄膜トランジスタ及び第1ブートストラップコンデンサを備え、前記第2薄膜トランジスタのゲート電極が前記第1ノードに電気的に接続され、ソース電極が第2クロック信号に電気的に接続され、ドレイン電極が出力端子G(n)に電気的に接続され、前記第1ブートストラップコンデンサの一端が前記第1ノードに電気的に接続され、他端が前記出力端子G(n)に電気的に接続され、
前記プルダウンモジュールは第4薄膜トランジスタ、第6薄膜トランジスタ、第7薄膜トランジスタ、第8薄膜トランジスタ及び第2ブートストラップコンデンサを備え、前記第4薄膜トランジスタのゲート電極が第2ノードに電気的に接続され、ソース電極が定電圧ローレベルに電気的に接続され、ドレイン電極が前記出力端子G(n)に電気的に接続され、前記第6薄膜トランジスタのゲート電極が前記第3ノードに電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記第2ノードに電気的に接続され、前記第7薄膜トランジスタのゲート電極が前記第2ノードに電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記第1ノードに電気的に接続され、前記第8薄膜トランジスタのゲート電極が第4クロック信号に電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記出力端子G(n)に電気的に接続され、前記第2ブートストラップコンデンサの一端が前記第2ノードに電気的に接続され、他端が前記第2クロック信号に電気的に接続され、かつ、
前記出力調整モジュールは第9薄膜トランジスタ、第10薄膜トランジスタ、第11薄膜トランジスタ及び第12薄膜トランジスタを備え、前記第9薄膜トランジスタのゲート電極が前記第2クロック信号に電気的に接続され、ソース電極が前記定電圧ハイレベルに電気的に接続され、ドレイン電極が第4ノードに電気的に接続され、前記第10薄膜トランジスタのゲート電極が前記第1ノードに電気的に接続され、ソース電極が前記第4ノードに電気的に接続され、ドレイン電極が前記出力端子G(n)に電気的に接続され、前記第11薄膜トランジスタのゲート電極が前記出力端子G(n−1)に電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記第4ノードに電気的に接続され、前記第12薄膜トランジスタのゲート電極が前記出力端子G(n+1)に電気的に接続され、ソース電極が前記定電圧ローレベルに電気的に接続され、ドレイン電極が前記第4ノードに電気的に接続されるLTPS半導体薄膜トランジスタによるGOA回路。 - 前記第4ノードのレベルは、前記第2クロック信号がハイ、ローレベルの間をホッピングすると共に、同様にハイ、ローレベルをホッピングする請求項3に記載のGOA回路。
- 前記第1クロック信号、前記第2クロック信号、前記第3クロック信号及び前記第4クロック信号のパルスが順次に出力されて、互いに重ならない請求項3に記載のGOA回路。
- 順方向に走査する時、前記第1薄膜トランジスタに電気的に接続される前記第1クロック信号及び前記出力端子G(n−1)がハイレベルを同時に提供し、逆方向に走査する時、前記第3薄膜トランジスタに電気的に接続される前記第3クロック信号及び前記出力端子G(n+1)がハイレベルを同時に提供する請求項3に記載のGOA回路。
- すべての薄膜トランジスタがいずれも低温ポリシリコン半導体薄膜トランジスタである請求項3に記載のGOA回路。
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