JP2019207743A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2019207743A JP2019207743A JP2018103157A JP2018103157A JP2019207743A JP 2019207743 A JP2019207743 A JP 2019207743A JP 2018103157 A JP2018103157 A JP 2018103157A JP 2018103157 A JP2018103157 A JP 2018103157A JP 2019207743 A JP2019207743 A JP 2019207743A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000001514 detection method Methods 0.000 claims description 17
- 238000003860 storage Methods 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 2
- 239000000872 buffer Substances 0.000 abstract description 31
- 230000006870 function Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/44—Program or device authentication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Mathematical Physics (AREA)
- Read Only Memory (AREA)
Abstract
Description
120:入出力バッファ 130:アドレスレジスタ
140:コントローラ 150:ワード線選択回路
160:ページバッファ/センス回路 170:列選択回路
180:内部電圧発生正回路 200:ビット線選択回路
300:固有データ生成回路 310:差動センスアンプ
Claims (12)
- NAND型ストリングを含むメモリセルアレイと、
前記メモリアレイの特定の領域を選択する選択手段と、
前記選択手段により選択された特定の領域を読み出す読出し手段と、
前記読出し手段により読み出された特定の領域のビット線対の電位差を検出する検出手段と、
前記検出手段の検出結果に基づき半導体装置の固有データを生成する生成手段と、
を有する半導体装置。 - 前記特定の領域は、前記読出し手段から物理的に最遠端のブロックである、請求項1に記載の半導体装置。
- 前記特定の領域は、前記読出し手段から物理的に最遠端のブロックに含まれるページである、請求項1に記載の半導体装置。
- 前記特定の領域は、ユーザーによってアクセスすることができない領域である、請求項1に記載の半導体装置。
- 前記特定の領域は、NAND型ストリングに接続されたMOSトランジスタである、請求項1に記載の半導体装置。
- 前記選択手段は、メモリセルの記憶状態にかかわらずメモリセルが導通する電圧を選択されたブロック内の全ワード線に印加する、請求項2または3に記載の半導体装置。
- 前記検出手段は、前記読出し手段のセンスノードに電気的に接続され、前記検出手段は、前記センスノードの電位差を検出するための差動センスアンプを含む、請求項1ないし6いずれか1つに記載の半導体装置。
- 前記ビット線対は、読出し動作時に隣接するビット線である、請求項1ないし7いずれか1つに記載の半導体装置。
- 前記読出し手段が偶数ビット線または奇数ビット線の読出しを行う場合、前記ビット線対は、隣接する偶数ビット線または奇数ビット線である、請求項1ないし7いずれか1つに記載の半導体装置。
- 前記ビット線対は、予め決められた規則に従い選択されたビット線である、請求項1ないし7いずれか1つに記載の半導体装置。
- 前記生成手段は、前記検出手段の検出結果を表すデータを演算する演算回路を含み、前記生成手段は、当該演算回路の演算結果を固有データとして出力する、請求項1ないし10いずれか1つに記載の半導体装置。
- 半導体装置はさらに、固有データの生成を制御する制御手段を含み、
前記制御手段は、パワーオンシーケンス時あるいは外部からの要求に応答して前記選択手段、前記読出し手段、前記検出手段および前記生成手段を制御し、前記固有データを生成させる、請求項1ないし11いずれか1つに記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2018103157A JP6646103B2 (ja) | 2018-05-30 | 2018-05-30 | 半導体装置 |
US16/406,263 US10971236B2 (en) | 2018-05-30 | 2019-05-08 | Semiconductor device with a function of generating inherent information |
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JP2018103157A JP6646103B2 (ja) | 2018-05-30 | 2018-05-30 | 半導体装置 |
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JP2019207743A true JP2019207743A (ja) | 2019-12-05 |
JP6646103B2 JP6646103B2 (ja) | 2020-02-14 |
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JP2018103157A Active JP6646103B2 (ja) | 2018-05-30 | 2018-05-30 | 半導体装置 |
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Cited By (1)
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JP2021163987A (ja) * | 2020-03-30 | 2021-10-11 | キオクシア株式会社 | メモリシステム、メモリデバイス、及びメモリシステムの制御方法 |
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EP3640945B1 (en) * | 2018-10-15 | 2021-03-17 | Nxp B.V. | Non-volatile memory with physical unclonable function |
KR102535827B1 (ko) * | 2019-04-04 | 2023-05-23 | 삼성전자주식회사 | 내부 전압을 안정화시키기 위한 메모리 장치 및 그것의 내부 전압 안정화 방법 |
US10923185B2 (en) | 2019-06-04 | 2021-02-16 | Qualcomm Incorporated | SRAM with burst mode operation |
US11437091B2 (en) * | 2020-08-31 | 2022-09-06 | Qualcomm Incorporated | SRAM with robust charge-transfer sense amplification |
US11894065B2 (en) * | 2022-01-05 | 2024-02-06 | Macronix International Co., Ltd. | Three-dimensional memory device |
US12007912B2 (en) * | 2022-06-01 | 2024-06-11 | Micron Technology, Inc. | NAND page buffer based security operations |
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Cited By (2)
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JP2021163987A (ja) * | 2020-03-30 | 2021-10-11 | キオクシア株式会社 | メモリシステム、メモリデバイス、及びメモリシステムの制御方法 |
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US20190371413A1 (en) | 2019-12-05 |
US10971236B2 (en) | 2021-04-06 |
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