JP2019067890A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 552
- 238000004519 manufacturing process Methods 0.000 title claims description 85
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 239000002019 doping agent Substances 0.000 claims description 96
- 238000000034 method Methods 0.000 claims description 48
- 230000002093 peripheral effect Effects 0.000 claims description 18
- 230000007423 decrease Effects 0.000 claims description 16
- 230000001133 acceleration Effects 0.000 claims description 11
- 229910052785 arsenic Inorganic materials 0.000 claims description 10
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 239000000969 carrier Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 324
- 230000008569 process Effects 0.000 description 42
- 230000005684 electric field Effects 0.000 description 41
- 230000000052 comparative effect Effects 0.000 description 38
- 238000009826 distribution Methods 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Abstract
Description
図1及び図2を参照して、実施の形態1に係る半導体装置1を説明する。
本実施の形態の半導体装置1,1aは、半導体素子3が設けられたセル領域2を含む半導体基板7を備える。半導体基板7は、おもて面8と裏面9とを有する。半導体素子3は、n型ドリフト領域10と、p型ベース領域11と、n型エミッタ領域12と、ゲート絶縁膜15と、ゲート電極16と、裏面9に設けられているp型コレクタ層26とを含む。ゲート絶縁膜15は、n型エミッタ領域12とn型ドリフト領域10とに挟まれるp型ベース領域11の部分11a上に設けられている。ゲート電極16は、ゲート絶縁膜15を挟んでp型ベース領域11の部分11aに対向している。
図27を参照して、実施の形態2に係る半導体装置1bを説明する。本実施の形態の半導体装置1bは、実施の形態1の半導体装置1と同様の構成を備えるが、主に以下の点で異なる。
図32及び図33を参照して、実施の形態3に係る半導体装置1cを説明する。本実施の形態の半導体装置1cは、実施の形態1の半導体装置1と同様の構成を備えるが、主に以下の点で異なる。
Claims (17)
- 半導体素子が設けられたセル領域を含む半導体基板を備え、前記半導体基板は、おもて面と裏面とを有し、
前記半導体素子は、n型ドリフト領域と、p型ベース領域と、n型エミッタ領域と、前記n型エミッタ領域と前記n型ドリフト領域とに挟まれる前記p型ベース領域の部分上に設けられているゲート絶縁膜と、前記ゲート絶縁膜を挟んで前記p型ベース領域の前記部分に対向するゲート電極と、前記裏面に設けられているp型コレクタ層と、第1のn型バッファ層と、第2のn型バッファ層と、第1のp型半導体領域とを含み、
前記第1のn型バッファ層は、前記n型ドリフト領域に接し、かつ、前記n型ドリフト領域に対して前記裏面側に設けられており、
前記第2のn型バッファ層は、前記第1のn型バッファ層に接し、かつ、前記第1のn型バッファ層に対して前記裏面側に設けられており、前記第1のn型バッファ層における第1のn型キャリアの第1の最大ピーク濃度は、前記第2のn型バッファ層における第2のn型キャリアの第2の最大ピーク濃度よりも小さく、前記第1のn型バッファ層は、前記第2のn型バッファ層よりも厚く、
前記第1のp型半導体領域は、前記第1のn型バッファ層の中に形成されており、
前記n型エミッタ領域と前記ゲート電極とが配列されている方向において、前記第1のp型半導体領域は、前記第1のn型バッファ層よりも狭い幅を有し、
前記第1のp型半導体領域は、前記p型コレクタ層及び前記p型ベース領域から離間されている、半導体装置。 - 前記おもて面の平面視において、前記第1のp型半導体領域は、前記ゲート電極に重なっている、請求項1に記載の半導体装置。
- 前記半導体素子は、n型半導体領域をさらに含み、
前記n型半導体領域は、前記裏面に設けられており、
前記n型半導体領域は、前記p型コレクタ層に隣接して設けられており、かつ、前記平面視において、前記ゲート電極に重なっていない、請求項2に記載の半導体装置。 - 前記第1のp型半導体領域における第1のp型キャリアの第3の最大ピーク濃度は、前記第2のn型バッファ層における前記第2のn型キャリアの前記第2の最大ピーク濃度よりも大きい、請求項1から請求項3のいずれか1項に記載の半導体装置。
- 前記第1のp型半導体領域は、前記p型コレクタ層よりも厚い、請求項1から請求項4のいずれか1項に記載の半導体装置。
- 前記第1のn型バッファ層は、前記第1のn型キャリアの複数のピーク濃度を有しており、前記複数のピーク濃度は前記裏面から離れるにつれて減少する、請求項1から請求項5のいずれか1項に記載の半導体装置。
- 前記第1のn型バッファ層は、プロトンを含み、
前記第2のn型バッファ層は、リンまたはヒ素を含む、請求項1から請求項6のいずれか1項に記載の半導体装置。 - 前記半導体基板は、前記セル領域を取り囲む外周領域をさらに含み、
前記外周領域は、前記おもて面に設けられたガードリングを含み、前記ガードリングは前記セル領域を取り囲んでいる、請求項1から請求項7のいずれか1項に記載の半導体装置。 - 前記第1のp型半導体領域は前記外周領域に形成されていない、請求項8に記載の半導体装置。
- 半導体基板を準備することを備え、前記半導体基板はおもて面と裏面とを有し、前記半導体基板は、前記半導体基板のセル領域に、n型ドリフト領域と、p型ベース領域と、n型エミッタ領域と、前記n型エミッタ領域と前記n型ドリフト領域とに挟まれる前記p型ベース領域の部分上に設けられているゲート絶縁膜と、前記ゲート絶縁膜を挟んで前記p型ベース領域の前記部分に対向するゲート電極とを含み、さらに、
前記裏面から第1のn型ドーパントをドープすることによって、第1のn型バッファ層を形成することを備え、前記第1のn型バッファ層は、前記n型ドリフト領域に接し、かつ、前記n型ドリフト領域に対して前記裏面側に設けられており、さらに、
前記裏面から第1のp型ドーパントをドープすることによって、前記第1のn型バッファ層の中に第1のp型半導体領域を形成することを備え、前記n型エミッタ領域と前記ゲート電極とが配列されている方向において、前記第1のp型半導体領域は、前記第1のn型バッファ層よりも狭い幅を有し、さらに、
前記裏面から第2のn型ドーパントをドープすることによって、第2のn型バッファ層を形成することを備え、前記第2のn型バッファ層は、前記第1のn型バッファ層に接し、かつ、前記第1のn型バッファ層に対して前記裏面側に設けられており、前記第1のn型バッファ層における第1のn型キャリアの第1の最大ピーク濃度は、前記第2のn型バッファ層における第2のn型キャリアの第2の最大ピーク濃度よりも小さく、前記第1のn型バッファ層は、前記第2のn型バッファ層よりも厚く、さらに、
前記裏面から第2のp型ドーパントをドープすることによって、前記裏面にp型コレクタ層を形成することを備え、
前記第1のp型半導体領域は、前記p型コレクタ層及び前記p型ベース領域から離間されている、半導体装置の製造方法。 - 前記おもて面の平面視において、前記第1のp型半導体領域は、前記ゲート電極に重なっている、請求項10に記載の半導体装置の製造方法。
- 前記裏面から第3のn型ドーパントをドープすることによって、前記裏面にn型半導体領域を形成することをさらに備え、
前記p型コレクタ層を形成することは、前記n型半導体領域に前記第2のp型ドーパントをドープすることを含み、
前記n型半導体領域は、前記p型コレクタ層に隣接して設けられており、かつ、前記平面視において、前記ゲート電極に重なっていない、請求項11に記載の半導体装置の製造方法。 - 前記第1のp型半導体領域と前記p型コレクタ層とは、同一のマスクを用いて形成される、請求項12に記載の半導体装置の製造方法。
- 前記第1のn型ドーパントをドープすることは、互いに異なる加速電圧で複数回前記第1のn型ドーパントを前記半導体基板に注入することを含み、
前記第1のn型バッファ層は、前記第1のn型キャリアの複数のピーク濃度を有しており、前記複数のピーク濃度は前記裏面から離れるにつれて減少する、請求項10から請求項13のいずれか1項に記載の半導体装置の製造方法。 - 前記第1のn型バッファ層を350℃以上450℃以下の温度でファーネスアニール処理して、前記第1のn型ドーパントを活性化することをさらに備える、請求項10から請求項14のいずれか1項に記載の半導体装置の製造方法。
- 前記第1のn型ドーパントと前記第2のn型ドーパントと前記第1のp型ドーパントと前記第2のp型ドーパントとを一括してアニールして、前記第1のn型ドーパントと前記第2のn型ドーパントと前記第1のp型ドーパントと前記第2のp型ドーパントとを活性化することをさらに備える、請求項10から請求項14のいずれか1項に記載の半導体装置の製造方法。
- 前記第1のn型ドーパントは、プロトンを含み、
前記第2のn型ドーパントは、リンまたはヒ素を含む、請求項10から請求項16のいずれか1項に記載の半導体装置の製造方法。
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