JP2018160707A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
Description
2a アイランド部
2b 電極部
4 樹脂層
6 レジストパターン層
11 実装用金属薄膜
12 リード層
13 ボンディング用金属膜
S 半導体素子
Claims (4)
- 半導体素子Sが搭載されるアイランド部2aと、該アイランド部2aの周りに所定の間隔をおいて配置される1以上の電極部2bとを有し、上記アイランド部2a上に搭載した半導体素子Sと上記電極部2bとの間を電気的に接続した後樹脂封止して、アイランド部2aと電極部2bのそれぞれ裏面が樹脂層4の底面と同一平面で露出して構成される半導体装置において、
上記アイランド部2aおよび電極部2bはそれぞれ電鋳により、裏面側の実装用金属薄膜11とこの上面に一体に積層されるリード層12の少なくとも二層構造からあらかじめ形成されていることを特徴とする半導体装置。 - 少なくとも電極部2bのリード層12上面にボンディング用金属膜13を形成したことを特徴とする請求項1に記載の半導体装置。
- 導電性基板1の一面側に、半導体素子S搭載用のアイランド部2aおよび半導体素子Sの電極Lと接続される電極部2bを形成するための所定パターンから成るレジストパターン層6を形成する工程と、
上記基板1の露出面に、実装用金属薄膜11をメッキ成長させるとともに該金属薄膜11上に電鋳工程によりリード層12を積層して成長させ一体化して、金属薄膜11とこの上面に一体に積層されるリード層12の少なくとも二層構造から成るアイランド部2aおよび電極部2bを独立して形成する工程と、
基板1よりレジストパターン層6を除去する工程と、
上記アイランド部2aに半導体素子Sを搭載した後、半導体素子Sと電極部2bとを電気的に接続する工程と、
上記基板1を除去して、アイランド部2aおよび電極部2bの金属薄膜11の各裏面が、樹脂層4の底面と同一平面で露出した状態で形成される工程
とを有する半導体装置の製造方法。 - 少なくとも電極部2bのリード層12上面に、メッキ工程によってボンディング用金属膜13を一体に成長形成し、半導体素子Sと電気的に接続させるようにしたことを特徴とする請求項3に記載の半導体装置の製造方法。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60234380A (ja) * | 1984-05-07 | 1985-11-21 | Nippon Mining Co Ltd | 太陽電池用基板 |
JPS6142796B2 (ja) * | 1983-02-09 | 1986-09-24 | Furukawa Electric Co Ltd | |
JPS61243193A (ja) * | 1985-04-18 | 1986-10-29 | Nisshin Steel Co Ltd | ステンレス鋼に純金めつきする方法 |
JP2002009196A (ja) * | 2000-06-20 | 2002-01-11 | Kyushu Hitachi Maxell Ltd | 半導体装置の製造方法 |
JP2002016181A (ja) * | 2000-04-25 | 2002-01-18 | Torex Semiconductor Ltd | 半導体装置、その製造方法、及び電着フレーム |
JP2002289739A (ja) * | 2001-03-23 | 2002-10-04 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法 |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6142796B2 (ja) * | 1983-02-09 | 1986-09-24 | Furukawa Electric Co Ltd | |
JPS60234380A (ja) * | 1984-05-07 | 1985-11-21 | Nippon Mining Co Ltd | 太陽電池用基板 |
JPS61243193A (ja) * | 1985-04-18 | 1986-10-29 | Nisshin Steel Co Ltd | ステンレス鋼に純金めつきする方法 |
JP2002016181A (ja) * | 2000-04-25 | 2002-01-18 | Torex Semiconductor Ltd | 半導体装置、その製造方法、及び電着フレーム |
JP2002009196A (ja) * | 2000-06-20 | 2002-01-11 | Kyushu Hitachi Maxell Ltd | 半導体装置の製造方法 |
JP2002289739A (ja) * | 2001-03-23 | 2002-10-04 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法 |
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