JP2014022582A - 半導体装置の製造方法、及び半導体装置 - Google Patents
半導体装置の製造方法、及び半導体装置 Download PDFInfo
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
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- H01L2224/732—Location after the connecting process
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
【解決手段】基板20の一面側にリード3の形成箇所を除く部分に対応するレジスト体25aを有するレジストパターン層25を形成する。次いで、レジストパターン層25から露出する基板20の表面にリード部13を形成した後、レジストパターン層25及びリード部13上に表面層12の形成箇所を除く部分に対応するレジスト体36aを有するレジストパターン層36を形成し、レジストパターン層36から露出するリード部13の表面の一部分に表面層12を積層形成してリード3を形成する。次いで、基板20よりレジストパターン層25及びレジストパターン層36を除去する。次いで、半導体素子2とリード3の表面層12とを電気的に接続する。次いで、半導体素子2とリード3とを封止樹脂38でモールドして樹脂封止体7を形成する。次いで、基板20を除去する。
【選択図】図1
Description
2 半導体素子
3 リード
4 ダイパッド
5 電極
6 ワイヤ
7 樹脂封止体
11 裏面層
12 表面層
13 リード部
14 ダイパッド部
20 基板
25 レジストパターン層
31 第1金属層
32 第2金属層
33 第3金属層
36 レジストパターン層
Claims (7)
- 半導体素子(2)と、前記半導体素子(2)と電気的に接続されるリード(3)とが樹脂封止体(7)により封止されている半導体装置の製造方法であって、
基板(20)の一面側に前記リード(3)の形成箇所を除く部分に対応するレジスト体(25a)を有するレジストパターン層(25)を形成する工程と、
前記レジストパターン層(25)から露出する前記基板(20)の表面にリード部(13)を形成した後、前記レジストパターン層(25)及び前記リード部(13)上に表面層(12)の形成箇所を除く部分に対応するレジスト体(36a)を有するレジストパターン層(36)を形成し、前記レジストパターン層(36)から露出する前記リード部(13)の表面の一部分に前記表面層(12)を積層形成して前記リード(3)を形成する工程と、
前記基板(20)より前記レジストパターン層(25)及び前記レジストパターン層(36)を除去する工程と、
前記半導体素子(2)と前記リード(3)の前記表面層(12)とを電気的に接続する工程と、
前記半導体素子(2)と前記リード(3)とを封止樹脂(38)でモールドして樹脂封止体(7)を形成する工程と、
前記基板(20)を除去する工程とを有することを特徴とする半導体装置の製造方法。 - 前記レジストパターン層(25)から露出する前記基板(20)の表面に前記リード部(13)を形成する前に、裏面層(11)を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記レジストパターン層(25)から露出する前記基板(20)の表面に前記リード部(13)を形成した後、前記レジストパターン層(25)及び前記リード部(13)上に直描装置(35)を用いてレジストパターン層(36)を形成し、前記レジストパターン層(36)から露出する前記リード部(13)の表面に前記表面層(12)を形成することを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記樹脂封止体(7)には前記半導体素子(2)及び前記リード(3)を複数封止し、前記基板(20)を除去した後、前記樹脂封止体(7)を切断線(X)に沿って個々の半導体装置に切断してあって、隣接する半導体装置の前記リード(3)を連接形成し、前記切断線(X)が連接形成した前記リード(3)の中央部分に沿っていることを特徴とする請求項1ないし3のいずれかに記載の半導体装置の製造方法。
- 前記リード(3)の前記表面層(12)が前記切断線(X)上を避けた位置に形成することを特徴とする請求項1ないし4のいずれかに記載の半導体装置の製造方法。
- 前記請求項1ないし5のいずれに記載の半導体装置の製造方法によって得られる半導体装置であって、隅部に位置する前記リード(3)が前記樹脂封止体(7)の正面、背面、側面、及び裏面から露出していることを特徴とする半導体装置。
- 前記リード(3)の前記表面層(12)が前記樹脂封止体(7)から露出されないように前記樹脂封止体(7)の内部に位置することを特徴とする請求項6に記載の半導体装置。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465418A (zh) * | 2014-12-24 | 2015-03-25 | 南通富士通微电子股份有限公司 | 一种扇出晶圆级封装方法 |
JP2016136573A (ja) * | 2015-01-23 | 2016-07-28 | 新日本無線株式会社 | リード内蔵型回路パッケージの製造方法 |
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WO2009060745A1 (ja) * | 2007-11-06 | 2009-05-14 | Nikon Corporation | 制御装置、露光方法、及び露光装置 |
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JPH09266267A (ja) * | 1996-03-28 | 1997-10-07 | Hitachi Chem Co Ltd | 転写配線支持部材及びそれを使用した半導体パッケージの製造法 |
JP2000268722A (ja) * | 1999-03-18 | 2000-09-29 | Fujitsu Ltd | 繰返しパターン形成方法および装置 |
JP2001326316A (ja) * | 2000-05-12 | 2001-11-22 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置用フレーム |
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