JP2018157035A - 半導体装置、およびその製造方法 - Google Patents
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Abstract
Description
図1は、第1実施形態に係る半導体装置の要部の断面図である。図1に示す半導体装置1は、絶縁膜に電荷を蓄積する、いわゆるチャージトラップ型の三次元半導体メモリに適用することができる。
図8は、第2実施形態に係る半導体装置2の製造工程の一部を示す断面図である。以下、第1実施形態と異なる点を中心に説明する。第1実施形態では、ブロック絶縁膜20の形成時に、欠陥終端元素90を含んだ改質ガス202を導入している。
図9は、第3実施形態に係る半導体装置3の製造工程の一部を示す断面図である。ここでは、第2実施形態と異なる点を中心に説明する。第2実施形態では、絶縁層12aを導電層12に置換する際に、ブロック絶縁膜20の露出部分へ改質ガス202を導入する。
図10は、第4実施形態に係る半導体装置の要部の断面図である。本実施形態では、第1実施形態に係る半導体装置1と同様の構成要素には同じ符号を付し、詳細な説明を省略する。本実施形態に係る半導体装置4は、電気的に浮遊している導電体に電荷を蓄積する、いわゆるフローティングゲート型の三次元半導体メモリに適用することができる。
図14は、第5実施形態に係る半導体装置5の製造工程の一部を示す断面図である。本実施形態は、第2実施形態の製法をフローティングゲート型の三次元半導体メモリに適用したものである。
Claims (5)
- 絶縁層と導電層とが交互に積層された積層体と、
前記絶縁層表面および前記導電層表面に設けられたブロック絶縁膜と、
前記ブロック絶縁膜表面に設けられた電荷蓄積膜と、
前記電荷蓄積膜表面に設けられた第1絶縁膜と、前記第1絶縁膜表面に設けられた第2絶縁膜と、前記第2絶縁膜表面に設けられた第3絶縁膜と、を有するトンネル絶縁膜と、
前記第3絶縁膜表面に設けられたチャネル膜と、を備え、
欠陥終端元素が少なくとも前記第1絶縁膜または前記第3絶縁膜に含まれ、前記第1の絶縁膜、前記第2の絶縁膜、および前記第3の絶縁膜の欠陥終端元素含有濃度がそれぞれ異なる、ことを特徴とする半導体装置。 - 前記第2絶縁膜は、前記第1絶縁膜および前記第2絶縁膜よりも、前記欠陥終端元素含有濃度が高い、ことを特徴とする請求項1に記載の半導体装置。
- 前記第1絶縁膜は、前記第3絶縁膜および前記第2絶縁膜よりも、前記欠陥終端元素含有濃度が高い、ことを特徴とする請求項1に記載の半導体装置。
- 前記欠陥終端元素が重水素である、ことを特徴とする請求項1から3のいずれかに記載の半導体装置。
- 第1の層と第2の層とが交互に積層された積層体を形成し、前記積層体を貫通するホールを形成し、前記ホール内にブロック絶縁膜を形成し、前記ブロック絶縁膜表面に電荷蓄積膜を形成し、前記電荷蓄積膜表面に第1絶縁膜を形成し、前記第1絶縁膜表面に第2絶縁膜を形成し、前記第2絶縁膜表面に第3絶縁膜を形成し、前記第3絶縁膜表面にチャネル膜を形成する半導体装置の製造方法において、
前記第1絶縁膜、前記第2絶縁膜、または前記第3絶縁膜は、重水素を含むガスを用いてALD法により形成する、ことを特徴とする半導体装置の製造方法。
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JP2017051693A JP2018157035A (ja) | 2017-03-16 | 2017-03-16 | 半導体装置、およびその製造方法 |
TW106123436A TWI670834B (zh) | 2017-03-16 | 2017-07-13 | 半導體裝置及其製造方法 |
CN201710662161.0A CN108630762A (zh) | 2017-03-16 | 2017-08-04 | 半导体装置及其制造方法 |
US15/699,609 US10153262B2 (en) | 2017-03-16 | 2017-09-08 | Semiconductor device and manufacturing method thereof |
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US10910401B2 (en) | 2019-03-15 | 2021-02-02 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
JP2021044486A (ja) * | 2019-09-13 | 2021-03-18 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2021106216A (ja) * | 2019-12-26 | 2021-07-26 | 東京エレクトロン株式会社 | 膜形成方法及びシステム |
JP7513547B2 (ja) | 2021-02-25 | 2024-07-09 | キオクシア株式会社 | 半導体製造装置および半導体装置の製造方法 |
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CN105226027B (zh) * | 2015-09-06 | 2019-03-15 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
JP2019054068A (ja) * | 2017-09-13 | 2019-04-04 | 東芝メモリ株式会社 | 半導体記憶装置及びその製造方法 |
JP2019207950A (ja) * | 2018-05-29 | 2019-12-05 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
JP2021048172A (ja) | 2019-09-17 | 2021-03-25 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2021125594A (ja) | 2020-02-06 | 2021-08-30 | キオクシア株式会社 | 半導体記憶装置及びその製造方法 |
JP2021129042A (ja) * | 2020-02-14 | 2021-09-02 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2021136410A (ja) | 2020-02-28 | 2021-09-13 | キオクシア株式会社 | 半導体装置の製造方法 |
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US20180269196A1 (en) | 2018-09-20 |
CN108630762A (zh) | 2018-10-09 |
TWI670834B (zh) | 2019-09-01 |
US10153262B2 (en) | 2018-12-11 |
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