CN105226027B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN105226027B CN105226027B CN201510560954.2A CN201510560954A CN105226027B CN 105226027 B CN105226027 B CN 105226027B CN 201510560954 A CN201510560954 A CN 201510560954A CN 105226027 B CN105226027 B CN 105226027B
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- H10B—ELECTRONIC MEMORY DEVICES
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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Abstract
一种半导体器件,包括衬底、源漏区、沟道区、栅极介质层和栅极导电层,其中,栅极介质层包括阻挡层、存储层、第一界面层、隧穿层、第二界面层。依照本发明的半导体器件及其制造方法,调整工艺步骤在栅极介质层中存储层与隧穿层之间增加界面层并灵活调整隧穿层氮峰值浓度和位置,能够有效提高栅极介质层中存储层与隧穿层之间的界面质量,增加工艺灵活性,改善器件可靠性和电流特性。
Description
技术领域
本发明涉及一种半导体器件及其制造方法,特别是涉及一种三维存储器栅介质层及其制造方法。
背景技术
为了改善存储器件的密度,业界已经广泛致力于研发减小二维布置的存储器单元的尺寸的方法。随着二维(2D)存储器件的存储器单元尺寸持续缩减,信号冲突和干扰会显著增大,以至于难以执行多电平单元(MLC)操作。为了克服2D存储器件的限制,业界已经研发了具有三维(3D)结构的存储器件,通过将存储器单元三维地布置在衬底之上来提高集成密度。
三维存储器由于其特殊的三维结构和复杂的工艺继承,无法使用单晶(硅)材料而只能用多晶(硅)材料作为沟道。其中,多晶(硅)材料的晶粒大小、晶粒边界的陷阱多少成为制约沟道导通能力的关键。高的界面态使得沟道的漏电较大,同时特性随温度的变化影响很大。
附图1示出了现有技术中一种典型的三维存储器。具体的,在衬底1上沉积不同介质材料2A/2B构成的堆叠以用作伪栅极,在多个伪栅极堆叠之间刻蚀开口填充绝缘材料形成存储器单元之间的绝缘隔离层3。隔离层3包围了多个有源区,刻蚀有源区内的伪栅极堆叠形成沟道沟槽,在沟槽中沉积栅介质4。在栅介质4上共形沉积非晶沟道层5,例如非晶硅,并且在后续过程中通过退火工艺转变为多晶的沟道层。
做为一种电荷捕获存储器,栅介质的特性是所有材料中最重要的部分,基本要求包括快的编程擦除速度以及良好的可靠性特性。因此,上述图1所示的栅介质层4通常至少包括三个子层,紧贴沟道层的隧穿层、隧穿层上用于存储捕获电荷的存储层、以及存储层与栅极/伪栅极之间的阻挡层。与以往其中隧穿层、存储层、阻挡层依次沉积在单晶硅沟道层表面上的平面电荷捕获存储器的栅介质制备方法不同,如图1所示的三维存储器由于其复杂的结构,淀积顺序的改变(沟道/隧穿层/存储层/阻挡层变为阻挡层/存储层/隧穿层/沟道)和沟道材料的变化(单晶硅变为多晶硅)使得我们迫切需要寻求一种满足以上三个基本要求的新的栅介质制备方法。
另一方面,由于擦除操作时空穴遇到的价带势垒高度大于电子导带势垒高度,电荷存储器一般采用ONO三明治结构作为隧穿层。中间的氮氧化硅可以有效的降低擦除时空穴隧穿遇到的势垒,极大的增强空穴隧穿几率,加快擦除速度。
因此,依照图1结构的一种现有技术的栅极介质层4的制备方法具体如图2A至图2E所示(对应于图1中虚线框所示,为对栅介质层4附近结构的局部放大)。如图2A所示,在栅极/伪栅极结构2A/2B中形成沟道沟槽,在沟道沟槽的侧面和底部、伪栅极结构的侧面(以及衬底1露出沟槽的顶表面)上共形地依次沉积阻挡层4A和存储层4B。随后如图2B所示,在存储层4B(图中侧面)上沉积氧化物的第一隧穿层4C1,例如氧化硅。接着如图2C所示,在第一隧穿层4C1上共形地沉积氮氧化物的第二隧穿层4C2,例如氮氧化硅。然后如图2D所示,在第二隧穿层4C2上共形地沉积氧化物例如氧化硅的第三隧穿层4C3并任选地退火处理。最后如图2E所示,在第三隧穿层4C3上共形地沉积非晶材料层并退火使其部分结晶化成为多晶材料的沟道层5,其材质例如为多晶硅。由此,形成了可加快擦除速度的ONO结构的隧穿层结构。
然而,现有方法存在以下问题。存储层4B和第一层隧穿层4C1之间的界面很差,容易引起额外的电荷泄漏通路。第二层隧穿层4C2的氮浓度虽然可调,但是浓度峰值的位置不能调整。第三层隧穿层4C3和多晶硅5之间的界面很差,容易引起较大的阈值分布和较差的温度特性。
发明内容
由上所述,本发明的目的在于克服上述技术困难,提出一种三维存储器及其制造方法,能够有效提高栅极介质层中存储层与隧穿层之间的界面质量,增加工艺灵活性,改善器件可靠性和电流特性。
为此,本发明一方面提供了一种半导体器件制造方法,包括步骤:在伪栅极结构侧面形成阻挡层和存储层;执行氧化和沉积工艺,在存储层上形成第一界面层;在第一界面层上形成连续的隧穿层;执行退火,在隧穿层表面形成第二界面层;在第二界面层上形成多晶材料的沟道。
其中,阻挡层为选自氧化硅、氧化铝、氧化铪或其组合的单层结构或多层堆叠结构;任选地,存储层为选自SiN、HfOx、ZrOx、YOx或其组合的单层结构或多层堆叠结构。
其中,所述氧化和沉积工艺至少包括多个交替进行的氧化子工序和沉积子工序;任选地,调节前驱体、还原性气体、氧化性气体的浓度和时序,控制进行氧化子工序和沉积子工序。
其中,形成隧穿层的步骤中,改变气体组分浓度和比例调整各个元素之间的比例。
其中,形成多晶材料的沟道的步骤进一步包括,在第二界面层上形成非晶材料层,执行第二退火将非晶材料层转变为多晶材料的沟道。
其中,隧穿层为高k材料并优选氮氧化物;任选地,第一界面层和/或第二界面层为氧化物。
本发明另一方面提供了一种半导体器件,包括衬底、源漏区、沟道区、栅极介质层和栅极导电层,其中,栅极介质层包括阻挡层、存储层、第一界面层、隧穿层、第二界面层。
其中,阻挡层为选自氧化硅、氧化铝、氧化铪或其组合的单层结构或多层堆叠结构;任选地,存储层为选自SiN、HfOx、ZrOx、YOx或其组合的单层结构或多层堆叠结构;任选地,隧穿层为高k材料并优选氮氧化物;任选地,第一界面层和/或第二界面层为氧化物。
其中,存储层厚度为2~15nm;任选地,第一界面层和/或第二界面层厚度为1nm;任选地,隧穿层厚度为2~8nm。
其中,隧穿层中各元素相对比例连续可调。
依照本发明的半导体器件及其制造方法,调整工艺步骤在栅极介质层中存储层与隧穿层之间增加界面层并灵活调整隧穿层氮峰值浓度和位置,能够有效提高栅极介质层中存储层与隧穿层之间的界面质量,增加工艺灵活性,改善器件可靠性和电流特性。
附图说明
以下参照附图来详细说明本发明的技术方案,其中:
图1为现有技术的三维存储器件的剖视图;
图2A至图2E为图1所示器件的栅介质层制造方法的各步骤剖视图;
图3A至图3E为本发明的栅介质层制造方法的各步骤剖视图;以及
图4为本发明的三维存储器件制造方法的示意性流程图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果,公开了能有效地提高栅介质子层之间界面质量的三维存储器制造方法。需要指出的是,类似的附图标记表示类似的结构,本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
首先,如图1所示,形成基础结构。
在衬底1上交替形成第一材料层2A与第二材料层2B的堆叠结构2。衬底1材质可以包括体硅(bulk Si)、体锗(bulk Ge)、绝缘体上硅(SOI)、绝缘体上锗(GeOI)或者是其他化合物半导体衬底,例如SiGe、SiC、GaN、GaAs、InP等等,以及这些物质的组合。为了与现有的IC制造工艺兼容,衬底1优选地为含硅材质的衬底,例如Si、SOI、SiGe、Si:C等。堆叠结构2的选自以下材料的组合并且至少包括一种绝缘介质:如氧化硅、氮化硅、非晶碳、类金刚石无定形碳(DLC)、氧化锗、氧化铝、等及其组合。第一材料层2A具有第一刻蚀选择性,第二材料层2B具有第二刻蚀选择性并且不同于第一刻蚀选择性(例如两种材料之间的刻蚀选择比大于5:1并优选大于10:1)。在本发明一个优选实施例中,叠层结构2A/2B均为非导电材料,层2A/层2B的组合例如氧化硅与氮化硅的组合、氧化硅与(未掺杂)多晶硅或非晶硅的组合、氧化硅或氮化硅与非晶碳的组合等等。在本发明另一优选实施例中,层2A与层2B在湿法腐蚀条件或者在氧等离子干法刻蚀条件下具有较大的刻蚀选择比(例如大于5:1)。层2A、层2B的沉积方法包括PECVD、LPCVD、HDPCVD、MOCVD、MBE、ALD、热氧化、蒸发、溅射等各种工艺。在本发明一个最优实施例中,层2A为二氧化硅,层2B为氮化硅。
在阵列区域刻蚀(伪栅极)堆叠结构2直至暴露衬底1,形成伪栅极开孔(或称第一开孔)并在其中形成填充层3(填充层3下方的衬底将形成未来的共源区)。优选地,采用RIE或等离子干法刻蚀各向异性刻蚀层2A/层2B的堆叠结构2,形成露出衬底1以及衬底1上交替堆叠的层2A/层2B的侧壁的开孔(未示出)。刻蚀气体例如针对二氧化硅和氮化硅等材质的碳氟基刻蚀气体,并且通过增加碳氟比而在侧壁形成由含C聚合物形成的临时保护侧壁,最终获得较好的垂直侧壁。在本发明一个优选实施例中刻蚀气体优选C3F6、C4F8等含C量比较高的气体并进一步优选通过增加氧化性气体如O2、CO等控制侧壁形貌。平行于衬底1表面切得的孔槽的截面形状可以为矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形等等各种几何形状。填充层3沉积方法包括PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等,材质优选为与堆叠结构2的层2A、层2B均具有高选择性的材料,例如层3、层2A、层2B三者之间每两个之间的刻蚀选择比均大于等于5:1。在本发明一个优选实施例中,层2A为氧化硅,层2B为氮化硅,填充层3为非晶锗、非晶碳、DLC氮氧化硅等,反之亦然。
接着,与刻蚀形成第一开孔的工艺类似,RIE或等离子干法刻蚀各向异性刻蚀层2A/层2B的堆叠结构2,在第一开孔的周围形成多个露出衬底1以及衬底1上交替堆叠的层2A/层2B的侧壁的第二开孔。刻蚀气体例如针对二氧化硅和氮化硅等材质的碳氟基刻蚀气体,并且通过增加碳氟比而在侧壁形成由含C聚合物形成的临时保护侧壁,最终获得较好的垂直侧壁。在本发明一个优选实施例中刻蚀气体优选C3F6、C4F8等含C量比较高的气体并进一步优选通过增加氧化性气体如O2、CO等控制侧壁形貌。在本发明一个优选实施例中,用于暴露共源区的第一开孔的尺寸(例如直径)要大于或等于用于形成沟道区的第二开孔尺寸,例如两者尺寸(直径或者多边形的最大跨距的比值)比大于1.5并优选大于等于2。在本发明一个实施例中,每一个第一开孔周围具有六个第二开孔,以便于提高稍后侧向刻蚀层2B的效率以及均匀性。
接着,如图4和图3A所示,在第二开孔中、伪栅极结构2A/2B的侧壁以及衬底1暴露的顶部上依次共形地形成阻挡层4A和存储层4B。沉积方法包括PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等。阻挡层4A可以是氧化硅、氧化铝、氧化铪等介质材料的单层结构或多层堆叠结构。存储层4B是具有电荷俘获能力的介质材料,例如SiN、HfOx、ZrOx、YOx等及其组合,同样可以是上述材料的单层结构或多层堆叠结构。存储层4B的厚度为2~15nm。
如图4和图3B所示,在存储层4B上共形地形成第一界面层4IF1,位于第二开孔中侧壁以及底部上。与之前图2A~图2E所示现有技术中单纯沉积形成第一隧穿层4C1不同,本申请采用氧化和沉积同时进行的工艺形成高质量的界面层。沉积方法包括PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等。具体的,控制沉积工艺中反应气体(例如包括,前驱体(例如硅烷、锗烷、TEOS等)、还原性气体(例如氢气、氨气、CO)、氧化性气体(例如氧气、臭氧、CO2、N2O)等气体的浓度和时序,对存储层4B界面进行氧化+淀积同时进行的工艺过程,由此比如形成1nm左右的界面层4IF1,来制备存储层4B和隧穿层4C之间的高质量界面层。特别地,在本发明一个实施例中,界面层4IF1的制备包括多个沉积子工序与氧化子工序的交替循环,例如先在沉积子工序中提高前驱体与氧化性气体的比例以增强例如氧化硅的沉积速度,然后任选地降低或去除氧化性气体比例并增加还原性气体比例以消除硅、锗等半导体材料的悬挂键,接着在氧化子工序中降低前驱体比例并增加氧化性气体比例以重新链接Si等半导体材料与O之间的键连接,由此可以在埃米量级的逐层氧化沉积过程中及时调整界面层的质量,获得纳米量级的高质量界面层4IF1,其厚度例如为1nm。此外,在本发明另一实施例中,也可以采用先提高还原性气体比例以减少悬挂键、接着提高前驱体比例以增大沉积速度、再提高氧化性气体比例以提高氧化薄膜致密性的三个子工艺循环交替的顺序,以及可以采取另外其他的工艺顺序。
如图4和图3C所示,在第一界面层4IF1上连续地、共形地形成隧穿层4C。沉积方法优选ALD。通过改变ALD沉积工艺中气体组份浓度和比例来连续沉积高K材料做为隧穿层,其中隧穿层4C中非氧元素的含量连续可调。高k材料包括但不限于氮化物(例如SiN、SiON、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物,例如MgO、Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、氮氧化物(如HfSiON)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))等,隧穿层可以是上述材料的单层结构或多层堆叠结构。在本发明一个优选实施例中,隧穿层4C为氮氧化物,例如氮氧化硅,通过连续调整气体组份的浓度和比例来调整氮氧化硅中氮元素的峰值浓度和位置,增加了工艺优化的灵活性。在本发明其他实施例中,调整气体组分浓度和比例以调整金属元素、N元素相对于O元素的比例,例如调整其峰值浓度和位置。隧穿层4C厚度例如2~8nm。
如图4和图3D所示,执行退火,使得隧穿层4C的表面元素重新分布,在隧穿层4C的表面形成氧化物的第二界面层4IF2。退火温度例如为500~1000℃,退火时间例如1分钟至10小时。在该过程中,退火等热处理施加的热量打破了隧穿层4C表面的化学键(例如Si-O、Si-N键),使得各个元素依照各自的键能重新结合,通过控制退火温度和时间使得隧穿层4C表面上某些键例如Si-O键占据优势从而重新组合形成例如氧化硅的第二界面层。界面层4IF2的厚度例如仅为1nm。
如图4和图3E所示,在第二界面层上沉积非晶材料并退火形成多晶材料的沟道层5,其厚度例如5~100nm。非晶材料例如为非晶硅、非晶锗,沉积工艺包括LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD等。在本发明一个实施例中,非晶沟道层的沉积方式为局部填充第二开孔(图1中左右两侧的开孔)的侧壁而形成为具有空气隙的中空柱形。在本发明其他实施例中,选择非晶沟道层的沉积方式以完全或者局部填充第二开孔,形成实心柱、空心环、或者空心环内填充绝缘层(未示出)的核心-外壳结构。非晶沟道层的水平截面的形状与第二开孔类似并且优选地共形,可以为实心的矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形等等各种几何形状,或者为上述几何形状演化得到的空心的环状、桶状结构(并且其内部可以填充绝缘层)。退火温度例如为300~850℃,通过低温工艺控制沟道的晶粒大小,减小漏电流。退火时间例如1分钟至10小时。最终,形成的栅极介质层4在从伪栅极结构2A/2B至沟道层5的方向上依次包括阻挡层4A、存储层4B、第一界面层4IF1、隧穿层4C、第二界面层4IF2,各个子层均为共形沉积分布,也即分布在第二开孔的侧壁以及底部上。
此后可以进一步执行后续工艺,完成器件制造。
例如,在沟道层5内侧填充绝缘隔离层(未示出),例如通过LPCVD、PECVD、HDPCVD等工艺形成氧化硅层,用于支撑、绝缘并隔离沟道层5。此后,在沟道层5顶部沉积漏区接触。优选地,采用与沟道层5材质相同或者相近(例如与Si相近的材质SiGe、SiC等,以便微调晶格常数而提高载流子迁移率,从而控制单元器件的驱动性能)的材质沉积在第二开口的顶部而形成存储器件单元晶体管的漏区,并且可以进一步形成硅化物(未示出)以降低接触电阻。
选择性刻蚀去除填充层3,重新露出第一开孔,利用第一开孔侧向刻蚀去除堆叠结构中的第二材料层(伪栅极层)2B。随后,采用各向同性干法刻蚀工艺,横向刻蚀去除层2B,在层2A之间留下了侧向凹槽。例如减小碳氟比以横向刻蚀氮化硅的层2B、或者采用热磷酸腐蚀氮化硅的层2B。备选地,当层2A为氮化硅、层2B为氧化硅时,可以采用HF基腐蚀液腐蚀层2B。
在第一开孔底部形成共源区,在凹槽中形成栅极导电层(未示出)。可以通过离子注入掺杂、以及优选地进一步在表面形成金属硅化物(未示出)而形成源区。金属硅化物例如NiSi2-y、Ni1-xPtxSi2-y、CoSi2-y或Ni1-xCoxSi2-y,其中x均大于0小于1,y均大于等于0小于1。栅极导电层可以是多晶硅、多晶锗硅、或金属,其中金属可包括Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的氮化物,栅极导电层中还可掺杂有C、F、N、O、B、P、As等元素以调节功函数。栅极绝缘层4与栅极导电层之间还优选通过PVD、CVD、ALD等常规方法形成氮化物的阻挡层(未示出),阻挡层材质为MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz,其中M为Ta、Ti、Hf、Zr、Mo、W或其它元素。同样地,栅极导电层可以是单层结构也可以是多层堆叠结构。此后形成源漏接触和层间介质层,完全器件的接触互联。
依照本发明的半导体器件及其制造方法,调整工艺步骤在栅极介质层中存储层与隧穿层之间增加界面层并灵活调整隧穿层氮峰值浓度和位置,能够有效提高栅极介质层中存储层与隧穿层之间的界面质量,增加工艺灵活性,改善器件可靠性和电流特性。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需脱离本发明范围而对器件结构或方法流程做出各种合适的改变和等价方式。此外,由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此,本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (20)
1.一种半导体器件制造方法,由以下步骤构成:
在伪栅极结构侧面形成阻挡层和存储层;
执行氧化和沉积工艺,在存储层上形成第一界面层;
在第一界面层上形成连续的隧穿层;
执行退火,打破隧穿层表面的化学键使得各个元素依照各自的键能重新结合而在隧穿层表面形成第二界面层;
在第二界面层上形成多晶材料的沟道。
2.如权利要求1的方法,其中,阻挡层为选自氧化硅、氧化铝、氧化铪或其组合的单层结构或多层堆叠结构。
3.如权利要求1的方法,其中,存储层为选自SiN、HfOx、ZrOx、YOx或其组合的单层结构或多层堆叠结构。
4.如权利要求1的方法,其中,所述氧化和沉积工艺至少包括多个交替进行的氧化子工序和沉积子工序。
5.如权利要求4的方法,其中,调节前驱体、还原性气体、氧化性气体的浓度和时序,控制进行氧化子工序和沉积子工序。
6.如权利要求1的方法,其中,形成隧穿层的步骤中,改变气体组分浓度和比例调整各个元素之间的比例。
7.如权利要求1的方法,其中,形成多晶材料的沟道的步骤进一步包括,在第二界面层上形成非晶材料层,执行第二退火将非晶材料层转变为多晶材料的沟道。
8.如权利要求1的方法,其中,隧穿层为高k材料。
9.如权利要求8的方法,其中,隧穿层为氮氧化物。
10.如权利要求1的方法,其中,第一界面层和/或第二界面层为氧化物。
11.一种半导体器件,包括衬底、源漏区、沟道区、栅极介质层和栅极导电层,其中,栅极介质层由阻挡层、存储层、第一界面层、隧穿层、第二界面层构成,其中第二界面层为退火打破隧穿层表面的化学键使得各个元素依照各自的键能重新结合而形成。
12.如权利要求11的半导体器件,其中,阻挡层为选自氧化硅、氧化铝、氧化铪或其组合的单层结构或多层堆叠结构。
13.如权利要求11的半导体器件,其中,存储层为选自SiN、HfOx、ZrOx、YOx或其组合的单层结构或多层堆叠结构。
14.如权利要求11的半导体器件,其中,隧穿层为高k材料。
15.如权利要求14的半导体器件,其中,隧穿层为氮氧化物。
16.如权利要求11的半导体器件,其中,第一界面层和/或第二界面层为氧化物。
17.如权利要求11的半导体器件,其中,存储层厚度为2~15nm。
18.如权利要求11的半导体器件,其中,第一界面层和/或第二界面层厚度为1nm。
19.如权利要求11的半导体器件,其中,隧穿层厚度为2~8nm。
20.如权利要求11的半导体器件,其中,隧穿层中各元素相对比例连续可调。
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