JP2013058592A - 不揮発性半導体記憶装置 - Google Patents
不揮発性半導体記憶装置 Download PDFInfo
- Publication number
- JP2013058592A JP2013058592A JP2011195846A JP2011195846A JP2013058592A JP 2013058592 A JP2013058592 A JP 2013058592A JP 2011195846 A JP2011195846 A JP 2011195846A JP 2011195846 A JP2011195846 A JP 2011195846A JP 2013058592 A JP2013058592 A JP 2013058592A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- charge storage
- hole
- tunnel insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000003860 storage Methods 0.000 title claims abstract description 105
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 55
- 239000013081 microcrystal Substances 0.000 claims description 17
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 abstract description 66
- 230000007423 decrease Effects 0.000 abstract description 15
- 230000006872 improvement Effects 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 6
- 239000010408 film Substances 0.000 description 465
- 229910052710 silicon Inorganic materials 0.000 description 90
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 85
- 239000010703 silicon Substances 0.000 description 85
- 229910052814 silicon oxide Inorganic materials 0.000 description 34
- 238000000034 method Methods 0.000 description 24
- 230000005684 electric field Effects 0.000 description 22
- 238000000231 atomic layer deposition Methods 0.000 description 21
- 239000010410 layer Substances 0.000 description 20
- 230000014759 maintenance of location Effects 0.000 description 17
- 230000000694 effects Effects 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 11
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 8
- 230000008859 change Effects 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000009826 distribution Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- -1 that is Inorganic materials 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910017121 AlSiO Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- YKTSYUJCYHOUJP-UHFFFAOYSA-N [O--].[Al+3].[Al+3].[O-][Si]([O-])([O-])[O-] Chemical compound [O--].[Al+3].[Al+3].[O-][Si]([O-])([O-])[O-] YKTSYUJCYHOUJP-UHFFFAOYSA-N 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】不揮発性半導体記憶装置は、半導体基板と、前記半導体基板上に形成され、上面から下面まで達する円筒状の貫通ホールを有するコントロールゲートCGと、前記貫通ホール内における前記コントロールゲートの側面上に形成されたブロック絶縁膜150と、前記貫通ホール内における前記ブロック絶縁膜の側面上に形成された電荷蓄積膜151と、前記貫通ホール内における前記電荷蓄積膜の側面上に形成されたトンネル絶縁膜152と、前記貫通ホール内における前記トンネル絶縁膜の側面上に形成された半導体層SPと、を具備し、前記トンネル絶縁膜は、SiO2を母材とし、添加することで前記母材のバンドギャップを低下させる元素を含む第1絶縁膜を含み、前記元素の濃度および濃度勾配は、前記半導体層側から前記電荷蓄積膜側に向かって単調に増加する。
【選択図】 図6
Description
図1乃至図3を用いて、各実施形態に係る不揮発性半導体記憶装置の構成例について説明する。
図4乃至図8を用いて、第1の実施形態に係る不揮発性半導体記憶装置について説明する。
まず、第1の実施形態に係るMONOSメモリセルの構造について説明する。
次に、第1の実施形態に係るMONOSメモリセルの製造方法について説明する。
上記第1の実施形態によれば、MONOSメモリセルにおけるトンネル絶縁膜152は、シリコンピラーSP側の界面においてSiO2、電荷蓄積膜151側の界面においてSiONで構成され、その間においてシリコンピラーSP側から電荷蓄積膜151側に向かってN濃度、およびN濃度の勾配が大きくなる(単調増加する)SiONで構成されている。これにより、トンネル絶縁膜152のバンドギャップ(もしくはバンドオフセット)をシリコンピラーSP側から電荷蓄積膜151側に向かって小さくなるように構成できる。その結果、電荷保持特性の向上を図ることができる。以下に、電荷保持によるバンド変調の原理について説明する。
図9および図10を用いて、第2の実施形態に係る不揮発性半導体記憶装置について説明する。
まず、第2の実施形態に係るMONOSメモリセルの構造について説明する。
次に、第2の実施形態に係るMONOSメモリセルの製造方法について説明する。
上記第2の実施形態によれば、第1の実施形態と同様の効果を得ることができる。すなわち、電荷保持特性の向上、および書き込み/消去特性の向上を図ることができる。
図11および図12を用いて、第3の実施形態に係る不揮発性半導体記憶装置について説明する。
まず、第3の実施形態に係るMONOSメモリセルの構造について説明する。
次に、第3の実施形態に係るMONOSメモリセルの製造方法について説明する。
上記第3の実施形態によれば、第1の実施形態と同様の効果を得ることができる。すなわち、電荷保持特性の向上、および書き込み/消去特性の向上を図ることができる。
図13および図15を用いて、第4の実施形態に係る不揮発性半導体記憶装置について説明する。
まず、第4の実施形態に係るMONOSメモリセルの構造について説明する。
次に、第4の実施形態に係るMONOSメモリセルの製造方法について説明する。
上記第4の実施形態によれば、第3の実施形態と同様の効果を得ることができる。すなわち、電荷保持特性の向上、および書き込み/消去特性の向上を図ることができ、また、チャネルにおける電荷の移動度を大きくすることができる。
図16および図17を用いて、第5の実施形態に係る不揮発性半導体記憶装置について説明する。
まず、第5の実施形態に係るMONOSメモリセルの構造について説明する。
次に、第5の実施形態に係るMONOSメモリセルの製造方法について説明する。
上記第5の実施形態によれば、第3の実施形態と同様の効果を得ることができる。すなわち、電荷保持特性の向上、および書き込み/消去特性の向上を図ることができ、また、チャネル近傍の絶縁膜がSiO2で構成されているため、チャネルにおける電荷の移動度を大きくすることができる。
Claims (6)
- 半導体基板と、
前記半導体基板上に形成され、上面から下面まで達する円筒状の貫通ホールを有するコントロールゲートと、
前記貫通ホール内における前記コントロールゲートの側面上に形成されたブロック絶縁膜と、
前記貫通ホール内における前記ブロック絶縁膜の側面上に形成された電荷蓄積膜と、
前記貫通ホール内における前記電荷蓄積膜の側面上に形成されたトンネル絶縁膜と、
前記貫通ホール内における前記トンネル絶縁膜の側面上に形成された半導体層と、
を具備し、
前記トンネル絶縁膜は、SiO2を母材とし、添加することで前記母材のバンドギャップを低下させる元素を含む第1絶縁膜を含み、
前記元素の濃度および濃度勾配は、前記半導体層側から前記電荷蓄積膜側に向かって単調に増加することを特徴とする不揮発性半導体記憶装置。 - 前記元素は、Nであることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記元素は、AlまたはHfであることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記トンネル絶縁膜は、前記第1絶縁膜と前記半導体層との間に、SiO2で構成される第2絶縁膜をさらに含むことを特徴とする請求項1または請求項2に記載の不揮発性半導体記憶装置。
- 前記トンネル絶縁膜は、前記第1絶縁膜と前記第2絶縁膜との界面に、Si微結晶をさらに含むことを特徴とする請求項4に記載の不揮発性半導体記憶装置。
- 半導体基板と、
前記半導体基板上に形成され、上面から下面まで達する円筒状の貫通ホールを有するコントロールゲートと、
前記貫通ホール内における前記コントロールゲートの側面上に形成されたブロック絶縁膜と、
前記貫通ホール内における前記ブロック絶縁膜の側面上に形成された電荷蓄積膜と、
前記貫通ホール内における前記電荷蓄積膜の側面上に形成されたトンネル絶縁膜と、
前記貫通ホール内における前記トンネル絶縁膜の側面上に形成された半導体層と、
を具備し、
前記トンネル絶縁膜は、前記電荷蓄積膜側から順に積層された、SiO2を母材とし、添加することで前記母材のバンドギャップを低下させる元素を含む複数の絶縁膜を含み、
前記電荷蓄積膜側から順に積層された前記複数の絶縁膜における前記元素の濃度をそれぞれ、n1,n2,・・・,およびni(iは整数、かつi≧3)とし、膜厚をそれぞれ、r1,r2,・・・,およびriとした場合、n1>n2>・・・>ni、かつ(n1−n2)/(r1+r2)>(n2−n3)/(r2+r3)>・・・>(ni−1−ni)/(ri−1+ri)の関係を満たすことを特徴とする不揮発性半導体記憶装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011195846A JP2013058592A (ja) | 2011-09-08 | 2011-09-08 | 不揮発性半導体記憶装置 |
US13/428,111 US8674430B2 (en) | 2011-09-08 | 2012-03-23 | Nonvolatile semiconductor storage device |
US14/157,162 US8963232B2 (en) | 2011-09-08 | 2014-01-16 | Nonvolatile semiconductor storage device |
US14/606,267 US9224875B2 (en) | 2011-09-08 | 2015-01-27 | Nonvolatile semiconductor storage device |
US14/944,483 US9496278B2 (en) | 2011-09-08 | 2015-11-18 | Nonvolatile semiconductor storage device |
US15/334,828 US9917095B2 (en) | 2011-09-08 | 2016-10-26 | Nonvolatile semiconductor storage device |
US15/883,730 US10347648B2 (en) | 2011-09-08 | 2018-01-30 | Nonvolatile semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011195846A JP2013058592A (ja) | 2011-09-08 | 2011-09-08 | 不揮発性半導体記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2013058592A true JP2013058592A (ja) | 2013-03-28 |
Family
ID=47829071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011195846A Withdrawn JP2013058592A (ja) | 2011-09-08 | 2011-09-08 | 不揮発性半導体記憶装置 |
Country Status (2)
Country | Link |
---|---|
US (6) | US8674430B2 (ja) |
JP (1) | JP2013058592A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018157035A (ja) * | 2017-03-16 | 2018-10-04 | 東芝メモリ株式会社 | 半導体装置、およびその製造方法 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013058592A (ja) * | 2011-09-08 | 2013-03-28 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2014007392A (ja) * | 2012-05-31 | 2014-01-16 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR102015578B1 (ko) * | 2012-09-11 | 2019-08-28 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그 형성방법 |
JP2015002195A (ja) * | 2013-06-13 | 2015-01-05 | 株式会社東芝 | 半導体記憶装置 |
US9099385B2 (en) * | 2013-11-08 | 2015-08-04 | Sandisk 3D Llc | Vertical 1T-1R memory cells, memory arrays and methods of forming the same |
US9263461B2 (en) * | 2014-03-07 | 2016-02-16 | Micron Technology, Inc. | Apparatuses including memory arrays with source contacts adjacent edges of sources |
US9508739B2 (en) | 2014-09-11 | 2016-11-29 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing the same |
KR102247914B1 (ko) * | 2014-10-24 | 2021-05-06 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
US9876029B2 (en) * | 2016-03-22 | 2018-01-23 | Toshiba Memory Corporation | Semiconductor memory device |
US11631465B2 (en) * | 2018-07-03 | 2023-04-18 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
US10593730B1 (en) | 2018-10-10 | 2020-03-17 | Micron Technology, Inc. | Three-dimensional memory array |
CN109300900B (zh) * | 2018-10-16 | 2020-07-07 | 长江存储科技有限责任公司 | 三维存储器以及形成三维存储器的方法 |
KR20200074304A (ko) * | 2018-12-14 | 2020-06-25 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
JP2020150171A (ja) | 2019-03-14 | 2020-09-17 | キオクシア株式会社 | 半導体装置 |
US20230164990A1 (en) * | 2021-11-24 | 2023-05-25 | Sandisk Technologies Llc | Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof |
US12016179B2 (en) | 2021-11-24 | 2024-06-18 | Sandisk Technologies Llc | Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4358252B2 (ja) | 2007-03-27 | 2009-11-04 | 株式会社東芝 | 不揮発性半導体メモリのメモリセル |
JP5047765B2 (ja) | 2007-12-11 | 2012-10-10 | 株式会社テクノ菱和 | 断熱膨張によるイオン核凝縮を用いた荷電粒子搬送式イオナイザー |
JP5142692B2 (ja) | 2007-12-11 | 2013-02-13 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2009231373A (ja) | 2008-03-19 | 2009-10-08 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2010021204A (ja) * | 2008-07-08 | 2010-01-28 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5361294B2 (ja) | 2008-09-04 | 2013-12-04 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP5355063B2 (ja) | 2008-12-16 | 2013-11-27 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2010231373A (ja) | 2009-03-26 | 2010-10-14 | Toshiba Corp | 料金収受システム |
JP5433462B2 (ja) * | 2010-03-03 | 2014-03-05 | 株式会社東芝 | 半導体装置の製造方法 |
JP5514004B2 (ja) * | 2010-06-15 | 2014-06-04 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
KR20120007838A (ko) * | 2010-07-15 | 2012-01-25 | 삼성전자주식회사 | 수직형 비휘발성 메모리 소자 및 그 제조방법 |
JP2013058592A (ja) * | 2011-09-08 | 2013-03-28 | Toshiba Corp | 不揮発性半導体記憶装置 |
-
2011
- 2011-09-08 JP JP2011195846A patent/JP2013058592A/ja not_active Withdrawn
-
2012
- 2012-03-23 US US13/428,111 patent/US8674430B2/en active Active
-
2014
- 2014-01-16 US US14/157,162 patent/US8963232B2/en active Active
-
2015
- 2015-01-27 US US14/606,267 patent/US9224875B2/en active Active
- 2015-11-18 US US14/944,483 patent/US9496278B2/en active Active
-
2016
- 2016-10-26 US US15/334,828 patent/US9917095B2/en active Active
-
2018
- 2018-01-30 US US15/883,730 patent/US10347648B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018157035A (ja) * | 2017-03-16 | 2018-10-04 | 東芝メモリ株式会社 | 半導体装置、およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US9496278B2 (en) | 2016-11-15 |
US9917095B2 (en) | 2018-03-13 |
US8674430B2 (en) | 2014-03-18 |
US20130062685A1 (en) | 2013-03-14 |
US20150137213A1 (en) | 2015-05-21 |
US8963232B2 (en) | 2015-02-24 |
US20170053924A1 (en) | 2017-02-23 |
US9224875B2 (en) | 2015-12-29 |
US20160079271A1 (en) | 2016-03-17 |
US10347648B2 (en) | 2019-07-09 |
US20140131789A1 (en) | 2014-05-15 |
US20180175048A1 (en) | 2018-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10347648B2 (en) | Nonvolatile semiconductor storage device | |
US9613981B2 (en) | Vertical channel-type 3D semiconductor memory device and method for manufacturing the same | |
US8426976B2 (en) | Non-volatile semiconductor storage device and method of manufacturing the same | |
CN110943088B (zh) | 半导体存储装置及其制造方法 | |
US8030700B2 (en) | Semiconductor memory device | |
US8598643B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
US8120961B2 (en) | Nonvolatile semiconductor memory device | |
US8907397B2 (en) | Nonvolatile semiconductor memory device containing a material having an oxygen dissociation catalytic action | |
US8829593B2 (en) | Semiconductor memory device having three-dimensionally arranged memory cells, and manufacturing method thereof | |
TWI704682B (zh) | 低電阻垂直通道立體記憶體元件 | |
JP2013222785A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
JP2009004510A (ja) | 不揮発性半導体記憶装置 | |
JP2018046059A (ja) | 半導体装置 | |
JP2011023586A (ja) | 半導体記憶装置およびその製造方法 | |
JPWO2011055433A1 (ja) | 不揮発性半導体記憶装置 | |
JP2013201270A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
JP2015079802A (ja) | 不揮発性半導体記憶装置 | |
US9502513B2 (en) | Non-volatile memory device and manufacture of the same | |
JP2013069751A (ja) | 不揮発性半導体記憶装置、及びその製造方法 | |
KR20120094818A (ko) | 비휘발성 메모리 소자 및 그 동작 방법 | |
US20130228841A1 (en) | Method for manufacturing nonvolatile semiconductor memory device and nonvolatile semiconductor memory device | |
JP2010123600A (ja) | 不揮発性半導体記憶装置 | |
JP2013062325A (ja) | 半導体記憶装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131205 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131212 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131219 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131226 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20140109 |
|
A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20141202 |