JP2018078274A - イメージセンサー装置及びそれを含むイメージセンサーモジュール - Google Patents
イメージセンサー装置及びそれを含むイメージセンサーモジュール Download PDFInfo
- Publication number
- JP2018078274A JP2018078274A JP2017157302A JP2017157302A JP2018078274A JP 2018078274 A JP2018078274 A JP 2018078274A JP 2017157302 A JP2017157302 A JP 2017157302A JP 2017157302 A JP2017157302 A JP 2017157302A JP 2018078274 A JP2018078274 A JP 2018078274A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- image sensor
- disposed
- sensor device
- connecting member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 253
- 238000007789 sealing Methods 0.000 claims abstract description 8
- 230000015654 memory Effects 0.000 claims description 14
- 230000003014 reinforcing effect Effects 0.000 claims description 13
- 239000003566 sealing material Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 description 26
- 239000000758 substrate Substances 0.000 description 16
- 235000012431 wafers Nutrition 0.000 description 16
- 238000002161 passivation Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 230000003287 optical effect Effects 0.000 description 13
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 230000006870 function Effects 0.000 description 10
- 239000011810 insulating material Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 7
- 239000011256 inorganic filler Substances 0.000 description 7
- 229910003475 inorganic filler Inorganic materials 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000033001 locomotion Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000003365 glass fiber Substances 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 239000003973 paint Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 208000032365 Electromagnetic interference Diseases 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011162 core material Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000859 α-Fe Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000000740 bleeding effect Effects 0.000 description 1
- 238000010344 co-firing Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/214—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
図1は電子機器システムの例を概略的に示すブロック図である。
一般に、半導体チップには、数多くの微細電気回路が集積されているが、それ自体が半導体完成品としての役割をすることはできず、外部からの物理的または化学的衝撃により損傷する可能性がある。したがって、半導体チップ自体をそのまま用いるのではなく、半導体チップをパッケージングして、パッケージ状態で電子機器などに用いている。
図3はファン‐イン半導体パッケージのパッケージング前後を概略的に示した断面図である。
図7はファン‐アウト半導体パッケージの概略的な形態を示した断面図である。
図9は一例によるイメージセンサー装置を概略的に示した断面図である。
図14は一例によるイメージセンサーモジュールを概略的に示した断面図である。
図15は一例によるカメラモジュールを概略的に示した断面図である。
Claims (17)
- 接続パッドが配置された活性面を有する第1半導体チップと、前記第1半導体チップの活性面上に配置され、前記第1半導体チップの接続パッドと電気的に連結された再配線層を含む第1連結部材と、前記第1連結部材上に配置され、前記第1半導体チップの少なくとも一部を封止する封止材と、を含むファン‐アウト半導体パッケージと、
前記第1連結部材上に配置され、前記第1連結部材と電気的に連結された第2半導体チップと、
前記第2半導体チップ上に配置され、前記第2半導体チップと電気的に連結された第3半導体チップと、を含み、
前記第2半導体チップ及び第3半導体チップの少なくとも1つはイメージセンサーである、イメージセンサー装置。 - 前記第1半導体チップはメモリー(Memory)であり、
前記第2半導体チップはロジック(Logic)であり、
前記第3半導体チップはイメージセンサー(Image sensor)である、請求項1に記載のイメージセンサー装置。 - 前記第1半導体チップの水平断面積が、前記第2及び第3半導体チップの水平断面積より小さい、請求項1または2に記載のイメージセンサー装置。
- 前記第1連結部材と前記第2半導体チップは、前記第1連結部材と前記第2半導体チップとの間に配置された接続部材を介して互いに電気的に連結され、
前記第2半導体チップと前記第3半導体チップは、前記第2半導体チップの少なくとも一部を貫通する貫通電極を介して互いに電気的に連結される、請求項1から3の何れか1項に記載のイメージセンサー装置。 - 前記第2半導体チップ及び前記第3半導体チップはそれぞれ、接続パッドが配置された活性面及び前記活性面の反対側に配置された非活性面を有し、
前記第2半導体チップ及び前記第3半導体チップのそれぞれの非活性面が互いに接する、請求項4に記載のイメージセンサー装置。 - 前記第2半導体チップ及び前記第3半導体チップは一体化している、請求項4または5に記載のイメージセンサー装置。
- 前記ファン‐アウト半導体パッケージは、前記第1連結部材上に配置され、貫通孔を有する第2連結部材をさらに含み、
前記第1半導体チップが前記貫通孔に配置されている、請求項1に記載のイメージセンサー装置。 - 前記第2連結部材は、前記第1半導体チップの接続パッドと電気的に連結された再配線層を含む、請求項7に記載のイメージセンサー装置。
- 前記第2連結部材は、第1絶縁層と、前記第1連結部材と接して前記第1絶縁層に埋め込まれた第1再配線層と、前記第1絶縁層の前記第1再配線層が埋め込まれた側の反対側上に配置された第2再配線層と、を含む、請求項7または8に記載のイメージセンサー装置。
- 前記第2連結部材は、前記第1絶縁層上に配置されて前記第2再配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3再配線層と、をさらに含む、請求項9に記載のイメージセンサー装置。
- 前記第1絶縁層の下面は前記第1再配線層の下面と段差を有する、請求項9または10に記載のイメージセンサー装置。
- 前記第2連結部材は、第1絶縁層と、前記第1絶縁層の両面に配置された第1再配線層及び第2再配線層と、前記第1絶縁層上に配置されて前記第1再配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3再配線層と、を含む、請求項7に記載のイメージセンサー装置。
- 前記第2連結部材は、前記第1絶縁層上に配置されて前記第2再配線層を覆う第3絶縁層と、前記第3絶縁層上に配置された第4再配線層と、をさらに含む、請求項12に記載のイメージセンサー装置。
- 前記第1絶縁層の厚さが前記第2絶縁層の厚さより厚い、請求項12または13に記載のイメージセンサー装置。
- 貫通孔を有し、回路パターンが形成された回路基板と、
前記回路基板の貫通孔に配置され、前記回路基板の回路パターンと電気的に連結されたイメージセンサー装置と、を含むイメージセンサーモジュールであって、
前記イメージセンサー装置は、
接続パッドが配置された活性面を有する第1半導体チップと、前記第1半導体チップの活性面上に配置され、前記第1半導体チップの接続パッドと電気的に連結された再配線層を含む第1連結部材と、前記第1連結部材上に配置され、前記第1半導体チップの少なくとも一部を封止する封止材と、を含むファン‐アウト半導体パッケージと、
前記第1連結部材上に配置され、前記第1連結部材と電気的に連結された第2半導体チップと、
前記第2半導体チップ上に配置され、前記第2半導体チップと電気的に連結された第3半導体チップと、を含み、
前記第2半導体チップ及び第3半導体チップの少なくとも1つはイメージセンサーである、イメージセンサーモジュール。 - 前記回路基板の下側に配置された補強板をさらに含み、
前記イメージセンサー装置が前記貫通孔内で前記補強板上に付着されている、請求項15に記載のイメージセンサーモジュール。 - 前記第2及び第3半導体チップはそれぞれ、接続パッドが配置された活性面及び前記活性面の反対側に配置された非活性面を有し、
前記第2半導体チップ及び前記第3半導体チップのそれぞれの非活性面が互いに接しており、
前記第3半導体チップの接続パッドは、ワイヤボンディングにより前記回路基板の回路パターンと電気的に連結されている、請求項15または16に記載のイメージセンサーモジュール。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2016-0149833 | 2016-11-10 | ||
KR20160149833 | 2016-11-10 | ||
KR1020160178488A KR102041663B1 (ko) | 2016-11-10 | 2016-12-23 | 이미지 센서 장치 및 이를 포함하는 이미지 센서 모듈 |
KR10-2016-0178488 | 2016-12-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2018078274A true JP2018078274A (ja) | 2018-05-17 |
Family
ID=62064029
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017157302A Pending JP2018078274A (ja) | 2016-11-10 | 2017-08-17 | イメージセンサー装置及びそれを含むイメージセンサーモジュール |
Country Status (2)
Country | Link |
---|---|
US (1) | US10153235B2 (ja) |
JP (1) | JP2018078274A (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019230243A1 (ja) * | 2018-05-28 | 2019-12-05 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置 |
WO2021111715A1 (ja) | 2019-12-04 | 2021-06-10 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置および撮像装置の製造方法 |
WO2023166843A1 (ja) * | 2022-03-01 | 2023-09-07 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置及び電子機器 |
JP7500876B2 (ja) | 2020-11-13 | 2024-06-17 | エイエムエス-オスラム アーゲー | X線放射の検出のためのモジュールアセンブリ |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10790328B2 (en) * | 2017-11-28 | 2020-09-29 | Asahi Kasei Microdevices Corporation | Semiconductor package and camera module |
US10991774B2 (en) * | 2018-02-12 | 2021-04-27 | Samsung Display Co., Ltd. | Display device and method for fabricating the same |
TWI704658B (zh) * | 2019-06-04 | 2020-09-11 | 恆勁科技股份有限公司 | 封裝基板 |
CN110418040B (zh) * | 2019-07-11 | 2020-11-06 | 北京中盛国华工程技术有限公司 | 一种智能安防监控装置 |
US12010416B1 (en) * | 2019-09-27 | 2024-06-11 | Apple Inc. | Camera module including embedded ceramic substrate package |
KR20210101440A (ko) * | 2020-02-10 | 2021-08-19 | 삼성전자주식회사 | Pcb 구조 및 이를 포함하는 전자 장치 |
Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001339057A (ja) * | 2000-05-30 | 2001-12-07 | Mitsumasa Koyanagi | 3次元画像処理装置の製造方法 |
JP2003264280A (ja) * | 2002-03-08 | 2003-09-19 | Hamamatsu Photonics Kk | 検出器 |
JP2003309243A (ja) * | 2002-04-15 | 2003-10-31 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
JP2003309213A (ja) * | 2002-04-15 | 2003-10-31 | Ngk Spark Plug Co Ltd | 配線基板 |
JP2005075784A (ja) * | 2003-09-01 | 2005-03-24 | Nagase & Co Ltd | カルボニル化合物の製造方法 |
JP2006059992A (ja) * | 2004-08-19 | 2006-03-02 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
JP2007123524A (ja) * | 2005-10-27 | 2007-05-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板 |
JP2008042899A (ja) * | 2006-07-19 | 2008-02-21 | Advanced Chip Engineering Technology Inc | イメージセンサ・モジュールの構造及びウェハーレベル・パッケージの製造方法 |
JP2008048313A (ja) * | 2006-08-21 | 2008-02-28 | Sony Corp | 物理量検出装置、物理量検出装置の駆動方法及び撮像装置 |
US20080308928A1 (en) * | 2007-06-13 | 2008-12-18 | Industrial Technology Research Institute | Image sensor module with a three-dimensional die-stacking structure |
JP2010232396A (ja) * | 2009-03-26 | 2010-10-14 | Nikon Corp | 固体撮像装置及びこれを用いたモジュール |
JP2011003961A (ja) * | 2009-06-16 | 2011-01-06 | Dainippon Printing Co Ltd | 撮像素子モジュール |
WO2011058879A1 (ja) * | 2009-11-12 | 2011-05-19 | 日本電気株式会社 | 機能素子内蔵基板、機能素子内蔵基板の製造方法、及び、配線基板 |
WO2011125380A1 (ja) * | 2010-04-08 | 2011-10-13 | 日本電気株式会社 | 半導体素子内蔵配線基板 |
JP2012118060A (ja) * | 2010-11-30 | 2012-06-21 | General Electric Co <Ge> | タイリング可能なセンサアレイ |
JP2013179313A (ja) * | 2005-06-02 | 2013-09-09 | Sony Corp | 半導体イメージセンサ・モジュール |
US20130249101A1 (en) * | 2012-03-23 | 2013-09-26 | Stats Chippac, Ltd. | Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units |
JP2014526139A (ja) * | 2011-06-30 | 2014-10-02 | ムラタ エレクトロニクス オサケユキチュア | システムインパッケージデバイスを製造する方法、および、システムインパッケージデバイス |
JP2015050457A (ja) * | 2013-08-29 | 2015-03-16 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 電子部品内蔵基板及びその製造方法 |
JP2015065479A (ja) * | 2009-03-19 | 2015-04-09 | ソニー株式会社 | 半導体装置とその製造方法、及び電子機器 |
JP2015088498A (ja) * | 2013-10-28 | 2015-05-07 | 株式会社ニコン | 固体撮像装置及び電子カメラ |
US20150138741A1 (en) * | 2013-11-21 | 2015-05-21 | Samsung Electro-Mechanics Co., Ltd. | Chip embedded board and method of manufacturing the same |
JP2015179859A (ja) * | 2012-04-27 | 2015-10-08 | 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. | 縦方向に集積化される背面照射型イメージセンサ装置 |
US20160043047A1 (en) * | 2014-08-07 | 2016-02-11 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package |
JP2016504774A (ja) * | 2013-01-29 | 2016-02-12 | アップル インコーポレイテッド | 超薄型PoPパッケージ |
JP2016048720A (ja) * | 2014-08-27 | 2016-04-07 | 富士通株式会社 | 撮像装置及びその製造方法 |
US20160133614A1 (en) * | 2014-11-07 | 2016-05-12 | Qualcomm Incorporated | Semiconductor package with incorporated inductance element |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013183425A (ja) | 2012-03-05 | 2013-09-12 | Toshiba Corp | カメラモジュール |
-
2017
- 2017-08-17 JP JP2017157302A patent/JP2018078274A/ja active Pending
- 2017-08-21 US US15/681,839 patent/US10153235B2/en active Active
Patent Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001339057A (ja) * | 2000-05-30 | 2001-12-07 | Mitsumasa Koyanagi | 3次元画像処理装置の製造方法 |
JP2003264280A (ja) * | 2002-03-08 | 2003-09-19 | Hamamatsu Photonics Kk | 検出器 |
JP2003309243A (ja) * | 2002-04-15 | 2003-10-31 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
JP2003309213A (ja) * | 2002-04-15 | 2003-10-31 | Ngk Spark Plug Co Ltd | 配線基板 |
JP2005075784A (ja) * | 2003-09-01 | 2005-03-24 | Nagase & Co Ltd | カルボニル化合物の製造方法 |
JP2006059992A (ja) * | 2004-08-19 | 2006-03-02 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
JP2013179313A (ja) * | 2005-06-02 | 2013-09-09 | Sony Corp | 半導体イメージセンサ・モジュール |
JP2007123524A (ja) * | 2005-10-27 | 2007-05-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板 |
JP2008042899A (ja) * | 2006-07-19 | 2008-02-21 | Advanced Chip Engineering Technology Inc | イメージセンサ・モジュールの構造及びウェハーレベル・パッケージの製造方法 |
JP2008048313A (ja) * | 2006-08-21 | 2008-02-28 | Sony Corp | 物理量検出装置、物理量検出装置の駆動方法及び撮像装置 |
US20080308928A1 (en) * | 2007-06-13 | 2008-12-18 | Industrial Technology Research Institute | Image sensor module with a three-dimensional die-stacking structure |
JP2015065479A (ja) * | 2009-03-19 | 2015-04-09 | ソニー株式会社 | 半導体装置とその製造方法、及び電子機器 |
JP2010232396A (ja) * | 2009-03-26 | 2010-10-14 | Nikon Corp | 固体撮像装置及びこれを用いたモジュール |
JP2011003961A (ja) * | 2009-06-16 | 2011-01-06 | Dainippon Printing Co Ltd | 撮像素子モジュール |
WO2011058879A1 (ja) * | 2009-11-12 | 2011-05-19 | 日本電気株式会社 | 機能素子内蔵基板、機能素子内蔵基板の製造方法、及び、配線基板 |
WO2011125380A1 (ja) * | 2010-04-08 | 2011-10-13 | 日本電気株式会社 | 半導体素子内蔵配線基板 |
JP2012118060A (ja) * | 2010-11-30 | 2012-06-21 | General Electric Co <Ge> | タイリング可能なセンサアレイ |
JP2014526139A (ja) * | 2011-06-30 | 2014-10-02 | ムラタ エレクトロニクス オサケユキチュア | システムインパッケージデバイスを製造する方法、および、システムインパッケージデバイス |
US20130249101A1 (en) * | 2012-03-23 | 2013-09-26 | Stats Chippac, Ltd. | Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units |
JP2015179859A (ja) * | 2012-04-27 | 2015-10-08 | 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. | 縦方向に集積化される背面照射型イメージセンサ装置 |
JP2016504774A (ja) * | 2013-01-29 | 2016-02-12 | アップル インコーポレイテッド | 超薄型PoPパッケージ |
JP2015050457A (ja) * | 2013-08-29 | 2015-03-16 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 電子部品内蔵基板及びその製造方法 |
JP2015088498A (ja) * | 2013-10-28 | 2015-05-07 | 株式会社ニコン | 固体撮像装置及び電子カメラ |
US20150138741A1 (en) * | 2013-11-21 | 2015-05-21 | Samsung Electro-Mechanics Co., Ltd. | Chip embedded board and method of manufacturing the same |
US20160043047A1 (en) * | 2014-08-07 | 2016-02-11 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package |
JP2016048720A (ja) * | 2014-08-27 | 2016-04-07 | 富士通株式会社 | 撮像装置及びその製造方法 |
US20160133614A1 (en) * | 2014-11-07 | 2016-05-12 | Qualcomm Incorporated | Semiconductor package with incorporated inductance element |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019230243A1 (ja) * | 2018-05-28 | 2019-12-05 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置 |
WO2021111715A1 (ja) | 2019-12-04 | 2021-06-10 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置および撮像装置の製造方法 |
JP7500876B2 (ja) | 2020-11-13 | 2024-06-17 | エイエムエス-オスラム アーゲー | X線放射の検出のためのモジュールアセンブリ |
WO2023166843A1 (ja) * | 2022-03-01 | 2023-09-07 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置及び電子機器 |
Also Published As
Publication number | Publication date |
---|---|
US10153235B2 (en) | 2018-12-11 |
US20180130750A1 (en) | 2018-05-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10153235B2 (en) | Image sensor device and image sensor module comprising the same | |
US10580812B2 (en) | Fan-out sensor package and camera module including the same | |
US11037971B2 (en) | Fan-out sensor package and optical fingerprint sensor module including the same | |
TWI670841B (zh) | 扇出型感測器封裝以及包含該封裝的光學指紋感測器模組 | |
JP6580728B2 (ja) | ファン−アウト半導体パッケージモジュール | |
CN109935603B (zh) | 扇出型传感器封装件 | |
TWI661527B (zh) | 扇出型感測器封裝與包含該封裝的光學式指紋感測器模組 | |
JP6598890B2 (ja) | ファン−アウト半導体パッケージモジュール | |
KR102005351B1 (ko) | 팬-아웃 센서 패키지 | |
US10923521B2 (en) | Fan-out sensor package and camera module | |
KR102524812B1 (ko) | 반도체 패키지 | |
CN111146188A (zh) | 半导体封装件 | |
CN111785695A (zh) | 半导体封装件 | |
KR102041663B1 (ko) | 이미지 센서 장치 및 이를 포함하는 이미지 센서 모듈 | |
KR20210078952A (ko) | 전자부품 내장기판 | |
KR102513088B1 (ko) | 팬-아웃 센서 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170912 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180914 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181016 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190115 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190618 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20200303 |