JP2014526139A - システムインパッケージデバイスを製造する方法、および、システムインパッケージデバイス - Google Patents
システムインパッケージデバイスを製造する方法、および、システムインパッケージデバイス Download PDFInfo
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- JP2014526139A JP2014526139A JP2014517862A JP2014517862A JP2014526139A JP 2014526139 A JP2014526139 A JP 2014526139A JP 2014517862 A JP2014517862 A JP 2014517862A JP 2014517862 A JP2014517862 A JP 2014517862A JP 2014526139 A JP2014526139 A JP 2014526139A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 59
- 239000000463 material Substances 0.000 claims abstract description 17
- 230000003287 optical effect Effects 0.000 claims description 20
- 238000009826 distribution Methods 0.000 claims description 14
- 239000012530 fluid Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000003566 sealing material Substances 0.000 claims description 2
- 239000011343 solid material Substances 0.000 claims description 2
- 239000000565 sealant Substances 0.000 claims 1
- 238000004513 sizing Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 52
- 238000010586 diagram Methods 0.000 description 20
- 238000013461 design Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 238000012937 correction Methods 0.000 description 3
- 239000008393 encapsulating agent Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000003381 stabilizer Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000005358 geomagnetic field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000002991 molded plastic Substances 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0074—3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
- G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
- G01C19/5783—Mountings or housings not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L19/00—Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
- G01L19/14—Housings
- G01L19/148—Details about the circuit board integration, e.g. integrated with the diaphragm surface or encapsulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P1/00—Details of instruments
- G01P1/02—Housings
- G01P1/023—Housings for acceleration measuring devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P1/00—Details of instruments
- G01P1/02—Housings
- G01P1/026—Housings for speed measuring devices, e.g. pulse generator
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/0802—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0228—Inertial sensors
- B81B2201/0235—Accelerometers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0228—Inertial sensors
- B81B2201/025—Inertial sensors not provided for in B81B2201/0235 - B81B2201/0242
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0257—Microphones or microspeakers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0264—Pressure sensors
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/03—Microengines and actuators
- B81B2201/036—Micropumps
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
- B81B2207/012—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being separate parts in the same package
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/094—Feed-through, via
- B81B2207/095—Feed-through, via through the lid
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L19/00—Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
- G01L19/0061—Electrical connection means
- G01L19/0084—Electrical connection means to the outside of the housing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
Description
本発明はマイクロエレクトロニクスの分野に属し、より具体的には、システムインパッケージ(system-in-package)デバイスの製造方法、および、システムインパッケージデバイスに属し、該システムインパッケージデバイスは、予め定められた寸法の少なくとも1つの第1種のダイ(die)と、予め定められた寸法の少なくとも1つの第2種のダイと、前記システムインデバイス(system-in-device)の少なくとも1つの更なる構成部品とを含むものである。
制限された空間とますます高度になる回路集積のために、電子部品の製造では、部品製造の幅広い分野で多様な要求が生まれている。表面実装される構成部品(components)はサイズ縮小が進み、これにより、大量の部品のプリント配線板上への集積が容易になっている。同様の物理的サイズの縮小傾向は、微小電気機械システム(microelectromechanicalsystems)(MEMS)の分野においても進行中である。そして、このような構成部品のサイズ縮小よりもさらに急速に実装空間の要求が増大したために、設計(design)が進化し極めて高度な集積を可能にし、ついにスタックされた構造にまで至った。
従って、本発明の目的は、システムインパッケージデバイスを製造するための改良された方法、および、その方法で製造されたシステムインパッケージデバイスを提供することである。本発明のこれらの目的は、各独立請求項に記載する特徴の方法、および、システムインパッケージデバイスによりそれぞれ実現される。本発明の好ましい実施態様は、各従属請求項に開示される。
ネイティブな第2ウェハ上における第2種のダイの第2の分割配分にて、該ネイティブな第2ウェハ上に第2の複数の第2種のダイを製作することを有し、上記1つの第2種のダイの上記予め定められた寸法は、前記第2の分割配分によって決定されるものである。
(electrostrictive)素子、圧電(piezoelectric)デバイスである。
以下に、添付の図面を参照して、各実施態様を詳細に説明する。
下記の各実施態様は例示である。明細書中において「或る」、「1つの」または「いくつかの」実施態様ということがあるが、これは、必ずしもこれらの語による言及が同じ実施態様を意味したり、1つの実施態様にのみ適用される特徴を意味したりするものではない。異なる実施態様の特徴を1つずつ組み合わせて更なる実施態様を提供してもよい。
−振動動作における機能要素の形状の周期的変化
−制御信号に応答する、形状の第1の状態から第2の状態への機能要素の形状の静的変化
−機能要素の周期的な位置的変化
−制御信号に応答可能な第1の静的状態から第2の静的状態への機能要素の位置的変化
−特定の電磁放射線の波長帯における電磁放射線に対する機能要素の透明性および/または不透明性
−電磁放射線の放射線源としての役割をすること
−力学的な波用の変換器としての役割をすること
−オンおよび/またはオフにされ得るスイッチング層としての役割をすること
−減衰化(attenuation)層としての役割をすること
−スイッチングボードとしての役割をすること
−配線板(ワイヤリングボード)としての役割をすること
Claims (18)
- システムインパッケージデバイスを作る方法であって、当該方法は、
予め定められた寸法を持った少なくとも1つの第1種のダイと、予め定められた寸法を持った少なくとも1つの第2種のダイと、前記システムインデバイスの少なくとも1つの更なる構成部品とを、前記システムインパッケージデバイスに含めることを有し;
前記第1種のダイおよび前記第2種のダイのうちの少なくとも1つを寸法の再設定のために選択することを有し;
選択されたダイの少なくとも一方の面に材料を加えることを有し、それにより、その加えられる材料と前記選択されたダイとが寸法再設定されたダイ構造を形成するようにし;
前記寸法再設定されたダイ構造上に接続層を形成することを有し;
選択されなかったダイと前記の少なくとも1つの更なる構成部品とを、前記接続層を介して、前記寸法再設定されたダイ構造に接触した状態でマウントできるように、前記寸法再設定されたダイ構造の寸法を設定することを有する;
前記方法。 - 当該方法が、更に:
ネイティブな第1ウェハ上における第1種のダイの第1の分割配分にて、該ネイティブな第1ウェハ上に第1の複数の第1種のダイを製作することを有し、上記1つの第1種のダイの上記予め定められた寸法は、前記第1の分割配分によって決定されるものであり;
ネイティブな第2ウェハ上における第2種のダイの第2の分割配分にて、該ネイティブな第2ウェハ上に第2の複数の第2種のダイを製作することを有し、上記1つの第2種のダイの前記予め定められた寸法は、前記第2の分割配分によって決定されるものである;
請求項1に記載の方法。 - 上記システムインデバイスの少なくとも1つの更なる構成部品が、上記システムインパッケージデバイスの入力および出力の作動のための接続部材である、請求項1または2に記載の方法。
- 当該方法が、2つ以上のダイを、上記寸法再設定されたダイ構造内に含めることを有する、請求項1、2または3に記載の方法。
- 当該方法が、2つ以上のダイを、上記接続層を介して、上記寸法再設定されたダイ構造に接触した状態でマウントすることを有する、請求項1、2または3に記載の方法。
- 当該方法が、流体用の通路を含むダイを、上記システムインパッケージデバイスの上記寸法再設定されたダイ構造に含めることを有する、先行する請求項のいずれかに記載の方法。
- 当該方法が、下記の要素のうちの少なくとも1つを含むダイを、上記システムインパッケージデバイスの上記寸法再設定されたダイ構造に含めることを有し、該要素が:
光学素子、動作センサー、圧力センサー、タイミングデバイス、フィルターデバイス、加速度計、磁力計、マイクロポンプおよびマイクロフォン
である、先行する請求項のいずれかに記載の方法。 - 当該方法が、上記寸法再設定されたダイ構造を貫通して延びる封止材貫通ビアによって、上記接続部材を上記接続層に接続することを有する、請求項3に記載の方法。
- 上記第1種のダイまたは上記第2種のダイが、下記の要素のうちの少なくとも1つを有し、該要素が:
MEMSデバイス、集積半導体回路、ASIC回路、発振器、光学デバイス、光電気デバイス、磁気デバイス、トランスデューサー、センサー、フィルター、スイッチングボード、配線板、磁歪素子、電歪素子、圧電デバイス
である、先行する請求項のいずれかに記載の方法。 - システムインパッケージデバイスであって、当該システムインパッケージデバイスは、
少なくとも1つの第1種のダイを有し、
少なくとも1つの第2種のダイを有し、
当該システムインパッケージデバイスの少なくとも1つの更なる構成部品を有し;
前記第1種のダイおよび前記第2種のダイのうちの少なくとも1つが、前記ダイの少なくとも一方の面に加えられた固体材料によって形成された寸法再設定されたダイ構造に含まれていることを有し;
前記寸法再設定されたダイ構造上の接続層を有し;
選択されなかったダイと、前記少なくとも1つの更なる構成部品とが、前記接続層を介して、前記寸法再設定されたダイ構造に接触してマウントされていることを有する;
前記システムインパッケージデバイス。 - 上記第1種のダイの寸法が、ネイティブな第1ウェハにおけるダイの第1の分割配分によって決定され、
上記第2種のダイの寸法が、ネイティブな第2ウェハにおけるダイの第2の分割配分によって決定される、
請求項10に記載のシステムインパッケージデバイス。 - 上記システムインデバイスの少なくとも1つの更なる構成部品が、当該システムインパッケージデバイスの入力および出力の作動のための接続部材である、請求項10または11に記載のシステムインパッケージデバイス。
- 上記寸法再設定されたダイ構造が、2つ以上のダイを含んでいる、請求項10、11または12に記載のシステムインパッケージデバイス。
- 2つ以上のダイが、上記接続層を介して、上記寸法再設定されたダイ構造に接触している、請求項10、11または12に記載のシステムインパッケージデバイス。
- 上記寸法再設定されたダイ構造が、流体用の通路を提供するダイを含んでいる、請求項10〜14のいずれかに記載のシステムインパッケージデバイス。
- 当該システムインパッケージデバイスが、下記の要素のうちの少なくとも1つを有するダイを含んでおり、該要素が:
光学素子、動作センサー、圧力センサー、タイミングデバイス、フィルターデバイス、加速度計、磁力計、マイクロポンプおよびマイクロフォン
である、請求項10〜15のいずれかに記載のシステムインパッケージデバイス。 - 上記接続部材が、上記寸法再設定されたダイ構造を貫通して延びる封止材貫通ビアによって、上記接続層に接続されている、請求項12に記載のシステムインパッケージデバイス。
- 上記第1種のダイまたは上記第2種のダイが、下記の要素のうちの少なくとも1つを有し、該要素が:
MEMSデバイス、集積半導体回路、ASIC回路、発振器、光学デバイス、光電気デバイス、磁気デバイス、トランスデューサー、センサー、フィルター、スイッチングボード、配線板、磁歪素子、電歪素子、圧電デバイス
である、先行する請求項のいずれかに記載のシステムインパッケージデバイス。
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JP2016213370A (ja) * | 2015-05-12 | 2016-12-15 | 日立化成株式会社 | 半導体装置及び半導体装置の製造方法 |
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JP2020198451A (ja) * | 2020-09-01 | 2020-12-10 | 昭和電工マテリアルズ株式会社 | 半導体装置及び半導体装置の製造方法 |
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Publication number | Publication date |
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EP2727146A1 (en) | 2014-05-07 |
JP6289364B2 (ja) | 2018-03-07 |
CN103765579A (zh) | 2014-04-30 |
CN107720689A (zh) | 2018-02-23 |
JP2018088545A (ja) | 2018-06-07 |
US20150375996A1 (en) | 2015-12-31 |
US20140217615A1 (en) | 2014-08-07 |
WO2013001171A1 (en) | 2013-01-03 |
US9184131B2 (en) | 2015-11-10 |
EP2727146A4 (en) | 2015-09-23 |
JP6450868B2 (ja) | 2019-01-09 |
US9828239B2 (en) | 2017-11-28 |
CN103765579B (zh) | 2017-10-31 |
KR101881732B1 (ko) | 2018-07-27 |
EP2727146B1 (en) | 2020-04-01 |
KR20140088070A (ko) | 2014-07-09 |
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